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[82.65.169.74]) by smtp.gmail.com with ESMTPSA id o4-20020a05600c378400b003e215a796fasm8292361wmr.34.2023.03.13.02.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 02:21:07 -0700 (PDT) References: <20230301183759.16163-1-ddrokosov@sberdevices.ru> <20230301183759.16163-3-ddrokosov@sberdevices.ru> <1jr0u2azfi.fsf@starbuckisacylon.baylibre.com> <20230306200549.7iuedbl27ejfhf6b@CAB-WSD-L081021> <1jlek60zun.fsf@starbuckisacylon.baylibre.com> <20230309182857.a2fzotcejueio23w@CAB-WSD-L081021> User-agent: mu4e 1.8.13; emacs 28.2 From: Jerome Brunet To: Dmitry Rokosov Cc: neil.armstrong@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com, jian.hu@amlogic.com, kernel@sberdevices.ru, rockosov@gmail.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v9 2/5] clk: meson: a1: add Amlogic A1 PLL clock controller driver Date: Mon, 13 Mar 2023 10:18:02 +0100 In-reply-to: <20230309182857.a2fzotcejueio23w@CAB-WSD-L081021> Message-ID: <1j5yb50zxz.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 09 Mar 2023 at 21:28, Dmitry Rokosov wrote: >> >> >> >> This last poke should not bits otherwise handled by parms. >> >> This is a rate init in disguise. >> >> >> > >> > I believe, you are talking about hifi_pll clk_regmap conflicts with >> > hifi_init_regs. The above init sequence shouldn't affect pll regmap setup, >> > it doesn't touch them (we assume that default bit values are all zero): >> > >> > .en = { >> > .reg_off = ANACTRL_HIFIPLL_CTRL0, >> > .shift = 28, >> > .width = 1, >> > }, >> > // init_value = 0x01f18440 >> > // en_mask = 0x10000000 >> > >> > .m = { >> > .reg_off = ANACTRL_HIFIPLL_CTRL0, >> > .shift = 0, >> > .width = 8, >> > }, >> > // init_value = 0x01f18440 >> > // m_mask = 0x0000000f >> >> mask is 0xff with width 8 >> > > Ah, you're right. Anyway, I think this is just init value and it's okay > to set it during initialization and rewrite after in parameter > propagation stage. > ... But the magic pokes are there only to initialize the unmanaged part of the clock regs. I'd like it to be clear and stay that way. So please, clear the managed fields from the initial poke table.