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Mon, 16 Jun 2025 09:27:53 -0700 (PDT) From: Jerome Brunet To: Jian Hu Cc: Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , Stephen Boyd , Michael Turquette , Dmitry Rokosov , robh+dt , Rob Herring , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: Re: [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock In-Reply-To: <4dd25114-212d-44d6-938a-63871750c292@amlogic.com> (Jian Hu's message of "Thu, 12 Jun 2025 21:02:00 +0800") References: <20250509074825.1933254-1-jian.hu@amlogic.com> <20250509074825.1933254-5-jian.hu@amlogic.com> <1jtt5ny6gq.fsf@starbuckisacylon.baylibre.com> <4dd25114-212d-44d6-938a-63871750c292@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Mon, 16 Jun 2025 18:27:53 +0200 Message-ID: <1jh60fd52u.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu 12 Jun 2025 at 21:02, Jian Hu wrote: >>> + >>> +static struct clk_regmap t7_pcie_pll_od =3D { >>> + .data =3D &(struct clk_regmap_div_data){ >>> + .offset =3D ANACTRL_PCIEPLL_CTRL0, >>> + .shift =3D 16, >>> + .width =3D 5, >>> + .flags =3D CLK_DIVIDER_ONE_BASED | >>> + CLK_DIVIDER_ALLOW_ZERO, >> What's the behaviour of the divider on zero then ? > > > If there is no CLK_DIVDER_ALLOW_ZERO, there is a warning when registering > t7_pcie_pll_od. > > like this: > > =C2=A0 ------------[ cut here ]------------ > =C2=A0 WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:140 > divider_recalc_rate+0xfc/0x100 > =C2=A0 pcie_pll_od: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set > =C2=A0 Modules linked in: > =C2=A0CPU: 1 PID: 1 Comm: swapper/0 Not tainted > 5.4.283-09976-ga803e94eed88-dirty #91 > =C2=A0 Hardware name: tm2_t962e2_ab311 (DT) > =C2=A0Call trace: > =C2=A0 [ffffffc020003750+=C2=A0 64][] dump_backtrace+0x= 0/0x1e4 > =C2=A0 [ffffffc020003790+=C2=A0 32][] show_stack+0x24/0= x34 > =C2=A0 [ffffffc0200037b0+=C2=A0 96][] dump_stack+0xbc/0= x108 > =C2=A0[ffffffc020003810+ 144][] __warn+0xf4/0x1b8 > =C2=A0 [ffffffc0200038a0+=C2=A0 64][] warn_slowpath_fmt= +0xac/0xc8 > =C2=A0[ffffffc0200038e0+=C2=A0 64][] divider_recalc_rat= e+0xfc/0x100 > =C2=A0[ffffffc020003920+=C2=A0 80][] > clk_regmap_div_recalc_rate+0x74/0x88 > =C2=A0 [ffffffc020003970+=C2=A0 96][] __clk_register+0x= 62c/0xb78 > > so add it to avoid the warning. That does not really answer my question