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AJvYcCUxmCuMFL9j3UKDxwCaglbaBbWXJkv4OI+8E9Efo0ubBJhyMyZNa/7Kc5yU6TSksWjuh5/F/3X3BOlIil2ENtt5AgmGihuhg6bXfg== X-Gm-Message-State: AOJu0YwLY790E5aNEjI+gxry85T8WI+182tx+/JiK3Q3rjme3M0yvWfY LBWMf7zk7Sd5k+rMY8gpMWGn4hESYSK1+DyV0hKBaavP0M2xv8EhqzApQ7ltN2k= X-Google-Smtp-Source: AGHT+IFsHz1EpicfNBa8SK5EZAZ1T5+dy4IspYfwOFlNMLVrJU9DmGujRx+HhvdOUVgWsVRH7gZz6w== X-Received: by 2002:a05:600c:6a14:b0:41b:f577:373 with SMTP id 5b1f17b1804b1-41feaa38e45mr94830085e9.15.1715603843566; Mon, 13 May 2024 05:37:23 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:5b77:3e5a:a808:339a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42015deac1asm37075625e9.17.2024.05.13.05.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 05:37:23 -0700 (PDT) References: <20240510090933.19464-1-ddrokosov@salutedevices.com> <20240510090933.19464-3-ddrokosov@salutedevices.com> <20240511-secret-barcode-e25c722ddf1d@spud> User-agent: mu4e 1.10.8; emacs 29.2 From: Jerome Brunet To: Conor Dooley Cc: Dmitry Rokosov , neil.armstrong@linaro.org, jbrunet@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com, jian.hu@amlogic.com, kernel@sberdevices.ru, rockosov@gmail.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Date: Mon, 13 May 2024 14:04:41 +0200 In-reply-to: <20240511-secret-barcode-e25c722ddf1d@spud> Message-ID: <1jjzjxzy4d.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Sat 11 May 2024 at 14:08, Conor Dooley wrote: > [[PGP Signed Part:Undecided]] > On Fri, May 10, 2024 at 12:08:54PM +0300, Dmitry Rokosov wrote: >> The 'syspll' PLL is a general-purpose PLL designed specifically for the >> CPU clock. It is capable of producing output frequencies within the >> range of 768MHz to 1536MHz. >> >> The clock source sys_pll_div16, being one of the GEN clock parents, >> plays a crucial role and cannot be tagged as "optional". Unfortunately, >> it was not implemented earlier due to the cpu clock ctrl driver's >> pending status on the TODO list. > > It's fine to not mark it optional in the binding, but it should be > optional in the driver as otherwise backwards compatibility will be > broken. Given this is an integral clock driver, sounds like it would > quite likely break booting on these devices if the driver doesn't treat > syspll_in as optional. > A lesson perhaps in describing the hardware entirely, even if the > drivers don't make use of all the information yet? That is nice but it is only possible if/when we have perfect knowledge of the HW being implemented. I don't know about you, but I rarely get perfect documentation for HW, let alone a public one. Those things are bound to happen as we implement support for the HW and discover how it works, not to mention the mistakes humans will inevitably do. If Linux was only supporting perfectly documented HW, it would not be supporting much of them I suspect. Stable API is already hard with ioctl but there, both sides are perfectly known. That is a fundamental difference with the 'DT ABI' Getting it right on day 1, every time - because things are set in stone afterwards - is unrealistic. As a maintainer, I do spend a disproportionate amount of time checking the bindings submission because I know how painful it gets to fix things up down the line. Unless I missed the simple solution to this problem, we can expect the problem keep happening again and again, no matter the number of lessons learned. > > Cheers, > Conor. > >> >> Signed-off-by: Dmitry Rokosov >> --- >> .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +++++-- >> include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 ++ >> 2 files changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml >> index a59b188a8bf5..fbba57031278 100644 >> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml >> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml >> @@ -26,11 +26,13 @@ properties: >> items: >> - description: input fixpll_in >> - description: input hifipll_in >> + - description: input syspll_in >> >> clock-names: >> items: >> - const: fixpll_in >> - const: hifipll_in >> + - const: syspll_in >> >> required: >> - compatible >> @@ -53,7 +55,8 @@ examples: >> reg = <0 0x7c80 0 0x18c>; >> #clock-cells = <1>; >> clocks = <&clkc_periphs CLKID_FIXPLL_IN>, >> - <&clkc_periphs CLKID_HIFIPLL_IN>; >> - clock-names = "fixpll_in", "hifipll_in"; >> + <&clkc_periphs CLKID_HIFIPLL_IN>, >> + <&clkc_periphs CLKID_SYSPLL_IN>; >> + clock-names = "fixpll_in", "hifipll_in", "syspll_in"; >> }; >> }; >> diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h >> index 2b660c0f2c9f..a702d610589c 100644 >> --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h >> +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h >> @@ -21,5 +21,7 @@ >> #define CLKID_FCLK_DIV5 8 >> #define CLKID_FCLK_DIV7 9 >> #define CLKID_HIFI_PLL 10 >> +#define CLKID_SYS_PLL 11 >> +#define CLKID_SYS_PLL_DIV16 12 >> >> #endif /* __A1_PLL_CLKC_H */ >> -- >> 2.43.0 >> >> > > [[End of PGP Signed Part]] -- Jerome