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AJvYcCWjie6BzUdOtOkO00ILusMlzyu3Ta/u0VgHHHk5aOC0Dn/EzgRG6kHdmtbUEXBYmxVzLdt6MLi7mpk8XAX/b9ZCtti6Y26Xfkyu7w== X-Gm-Message-State: AOJu0YwBpRnSF9sTchN615ikChKxas/u53Ei4B9co+0Moxw8VkJONBAL /e3QpDYbgzNi6kPuIj/XHw+gmQpq0TJ9GXlz3zt8DPiryrVKPoFb8/oPEFvqZFM= X-Google-Smtp-Source: AGHT+IGnkiii1p31wpEBxYvlhM/aMqmsmiEtQ3NQ+1Qn6f87Nt4y/G9/2KcL8KQaX8/8bf+QvAuVbg== X-Received: by 2002:a05:600c:4fcf:b0:420:1585:7a99 with SMTP id 5b1f17b1804b1-42015857b80mr27774355e9.38.1715601871464; Mon, 13 May 2024 05:04:31 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:5b77:3e5a:a808:339a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42013c5fa61sm49472435e9.40.2024.05.13.05.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 05:04:31 -0700 (PDT) References: <20240510090933.19464-1-ddrokosov@salutedevices.com> <20240510090933.19464-5-ddrokosov@salutedevices.com> <20240511-courier-afflicted-e351af5cded2@spud> User-agent: mu4e 1.10.8; emacs 29.2 From: Jerome Brunet To: Conor Dooley Cc: Dmitry Rokosov , neil.armstrong@linaro.org, jbrunet@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com, jian.hu@amlogic.com, kernel@sberdevices.ru, rockosov@gmail.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input Date: Mon, 13 May 2024 14:02:21 +0200 In-reply-to: <20240511-courier-afflicted-e351af5cded2@spud> Message-ID: <1jo799zzn5.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Sat 11 May 2024 at 14:03, Conor Dooley wrote: > [[PGP Signed Part:Undecided]] > On Fri, May 10, 2024 at 12:08:56PM +0300, Dmitry Rokosov wrote: >> The 'sys_pll_div16' input clock is used as one of the sources for the >> GEN clock. >> >> Signed-off-by: Dmitry Rokosov > > Provided that this new clock is optional in the driver, > Acked-by: Conor Dooley The way CCF works, it is not going to crash if DT does not have this. It will be viewed as non-connected input, in a way > > Cheers, > Conor. > >> --- >> .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml >> index 6d84cee1bd75..11862746ba44 100644 >> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml >> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml >> @@ -30,6 +30,7 @@ properties: >> - description: input fixed pll div7 >> - description: input hifi pll >> - description: input oscillator (usually at 24MHz) >> + - description: input sys pll div16 >> >> clock-names: >> items: >> @@ -39,6 +40,7 @@ properties: >> - const: fclk_div7 >> - const: hifi_pll >> - const: xtal >> + - const: sys_pll_div16 >> >> required: >> - compatible >> @@ -65,9 +67,10 @@ examples: >> <&clkc_pll CLKID_FCLK_DIV5>, >> <&clkc_pll CLKID_FCLK_DIV7>, >> <&clkc_pll CLKID_HIFI_PLL>, >> - <&xtal>; >> + <&xtal>, >> + <&clkc_pll CLKID_SYS_PLL_DIV16>; >> clock-names = "fclk_div2", "fclk_div3", >> "fclk_div5", "fclk_div7", >> - "hifi_pll", "xtal"; >> + "hifi_pll", "xtal", "sys_pll_div16"; >> }; >> }; >> -- >> 2.43.0 >> >> > > [[End of PGP Signed Part]] -- Jerome