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Sun, 19 Jul 2026 06:29:45 -0700 (PDT) From: Jerome Brunet To: Chen-Yu Tsai Cc: sashiko-reviews@lists.linux.dev, robh@kernel.org, linux-rtc@vger.kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, Alexandre Belloni , linux-clk Subject: Re: [PATCH v5 2/4] clk: sunxi-ng: div: add read-only operation support In-Reply-To: (Chen-Yu Tsai's message of "Sun, 19 Jul 2026 18:59:33 +0800") References: <20260717-a733-rtc-v5-0-3874cc26abf7@baylibre.com> <20260717-a733-rtc-v5-2-3874cc26abf7@baylibre.com> <20260717154005.444E41F000E9@smtp.kernel.org> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Sun, 19 Jul 2026 15:29:43 +0200 Message-ID: <1jqzkzds54.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On dim. 19 juil. 2026 at 18:59, Chen-Yu Tsai wrote: > >> > + >> > + } else { >> >> [ ... ] >> >> > @@ -143,3 +157,15 @@ const struct clk_ops ccu_div_ops =3D { >> > .set_rate =3D ccu_div_set_rate, >> > }; >> > EXPORT_SYMBOL_NS_GPL(ccu_div_ops, "SUNXI_CCU"); >> > + >> > +const struct clk_ops ccu_rodiv_ops =3D { >> > + .disable =3D ccu_div_disable, >> > + .enable =3D ccu_div_enable, >> > + .is_enabled =3D ccu_div_is_enabled, >> > + >> > + .get_parent =3D ccu_div_get_parent, >> > + >> > + .determine_rate =3D ccu_div_determine_rate, >> > + .recalc_rate =3D ccu_div_recalc_rate, >> > +}; >> >> [Severity: High] >> Could the missing .set_parent callback in ccu_rodiv_ops lead to a silent >> desynchronization between the software clock tree and the hardware? >> >> The struct provides reparenting capabilities via .get_parent and >> .determine_rate, but omits .set_parent. If a rate request causes >> ccu_mux_helper_determine_rate() to evaluate and select a new parent, the >> Common Clock Framework will apply this new parent in software but skip >> updating the hardware since .set_parent is NULL. > > This is an issue. I'm not sure if what Sashiko says actually happens. I think it could. I've defenitely made a mistake here. > But 1. this is "read-only divider", not "read-only mux & divider", The correct way to choose between the 2 is CLK_SET_RATE_NO_REPARENT I think. > so the .set_parent callback should be provided. And 2. this is using > the ccu_mux_determine_rate_helper, so it's possible a clk_set_rate() > call is going to cause a reparent. > > I can add it while applying if there are no other issues. As you prefer, I don't mind sending another version in a few days (giving some review time to patch #1) > > ChenYu > >> This would leave all downstream clock rate calculations incorrect. >> >> -- >> Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260717-a733-rt= c-v5-0-3874cc26abf7@baylibre.com?part=3D2 >> --=20 Jerome