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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id c1-20020a5d5281000000b0030aded83385sm955693wrv.27.2023.06.08.01.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 01:59:39 -0700 (PDT) References: <20230517070215.28463-1-yu.tu@amlogic.com> <20230517070215.28463-4-yu.tu@amlogic.com> <1j5y804q7u.fsf@starbuckisacylon.baylibre.com> <73acf297-3f60-1ce1-2f05-af048aa37199@amlogic.com> User-agent: mu4e 1.8.13; emacs 28.2 From: Jerome Brunet To: Yu Tu , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Conor Dooley , Martin Blumenstingl Cc: kelvin.zhang@amlogic.com, qi.duan@amlogic.com Subject: Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Date: Thu, 08 Jun 2023 10:53:31 +0200 In-reply-to: <73acf297-3f60-1ce1-2f05-af048aa37199@amlogic.com> Message-ID: <1jttvi9vnq.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org >>> + >>> +static struct clk_regmap s4_fclk_div4 = { >>> + .data = &(struct clk_regmap_gate_data){ >>> + .offset = ANACTRL_FIXPLL_CTRL1, >>> + .bit_idx = 21, >>> + }, >>> + .hw.init = &(struct clk_init_data){ >>> + .name = "fclk_div4", >>> + /* >>> + * For more information, please refer to s4_fixed_pll_dco. >>> + */ >> While div2 and div3 got an explanation from previous SoCs, they others - >> like div4/div7/etc ... - have been able to cope with rw ops so far. >> Why is the S4 different for all these clocks ? > > The chip was changed fixed pll for security reasons. > > Fixed PLL registers are not writable in the kernel phase. Write of fixed > PLL-related register will cause the system to crash. > That is definitely worth mentionning >> Requiring RO ops (or fishy clock flags) is usually a sign that a clock >> is used without an appropriate driver. >> Neil is currently dealing with the dt-bindings, please * Adjust your patchset accordingly * Wait for his v2 to land, you'll need it. >>> + .ops = &clk_regmap_gate_ro_ops, >>> + .parent_hws = (const struct clk_hw *[]) { >>> + &s4_fclk_div4_div.hw >>> + }, >>> + .num_parents = 1, >>> + }, >>> +}; >>> +