[PATCH v3 1/5] arm64: dts: renesas: r8a77995: add FCPV nodes

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* [PATCH v3 1/5] arm64: dts: renesas: r8a77995: add FCPV nodes
       [not found] ` <1518602108-1724-1-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
@ 2018-02-14  9:55   ` Kieran Bingham
  2018-02-15 16:28     ` Simon Horman
  0 siblings, 1 reply; 13+ messages in thread
From: Kieran Bingham @ 2018-02-14  9:55 UTC (permalink / raw)
  To: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Simon Horman,
	Laurent Pinchart, Kieran Bingham
  Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list

From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>

The FCPVB handles the interface between the VSPB and memory, while the
FCPVD handles the interface between the VSPD and memory.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cd3c6a30fc47..196a917afea6 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -691,6 +691,33 @@
 			#phy-cells = <0>;
 			status = "disabled";
 		};
+
+		fcpvb0: fcp@fe96f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe96f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 607>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 607>;
+			iommus = <&ipmmu_vp0 5>;
+		};
+
+		fcpvd0: fcp@fea27000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea27000 0 0x200>;
+			clocks = <&cpg CPG_MOD 603>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 603>;
+			iommus = <&ipmmu_vi0 8>;
+		};
+
+		fcpvd1: fcp@fea2f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea2f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 602>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 602>;
+			iommus = <&ipmmu_vi0 9>;
+		};
 	};
 
 	timer {
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 1/5] arm64: dts: renesas: r8a77995: add FCPV nodes
  2018-02-14  9:55   ` [PATCH v3 1/5] arm64: dts: renesas: r8a77995: add FCPV nodes Kieran Bingham
@ 2018-02-15 16:28     ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2018-02-15 16:28 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: linux-renesas-soc, Laurent Pinchart, Kieran Bingham,
	Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list

On Wed, Feb 14, 2018 at 09:55:04AM +0000, Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> 
> The FCPVB handles the interface between the VSPB and memory, while the
> FCPVD handles the interface between the VSPD and memory.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Thanks, applied.

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 2/5] arm64: dts: renesas: r8a77995: add VSP instances
       [not found] <1518602108-1724-1-git-send-email-kbingham@kernel.org>
       [not found] ` <1518602108-1724-1-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
@ 2018-02-14  9:55 ` Kieran Bingham
       [not found]   ` <1518602108-1724-3-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
  2018-02-14  9:55 ` [PATCH v3 3/5] arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs Kieran Bingham
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 13+ messages in thread
From: Kieran Bingham @ 2018-02-14  9:55 UTC (permalink / raw)
  To: linux-renesas-soc, Simon Horman, Laurent Pinchart, Kieran Bingham
  Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list

From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>

The r8a77995 has a VSPBS to support image processing such as blending of
two input images, and has two VSPDs to handle display pipelines with a
DU.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

---
v2:
 - Fix VSPD register map size
 - Squash VSPBS and VSPD patches together

v3:
 - Fix VSPBS register map size too :-)

 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 196a917afea6..0db242114bc5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -692,6 +692,16 @@
 			status = "disabled";
 		};
 
+		vspbs: vsp@fe960000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe960000 0 0x8000>;
+			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 627>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 627>;
+			renesas,fcp = <&fcpvb0>;
+		};
+
 		fcpvb0: fcp@fe96f000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xfe96f000 0 0x200>;
@@ -701,6 +711,16 @@
 			iommus = <&ipmmu_vp0 5>;
 		};
 
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x8000>;
+			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 623>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 623>;
+			renesas,fcp = <&fcpvd0>;
+		};
+
 		fcpvd0: fcp@fea27000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea27000 0 0x200>;
@@ -710,6 +730,16 @@
 			iommus = <&ipmmu_vi0 8>;
 		};
 
+		vspd1: vsp@fea80000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x8000>;
+			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 622>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 622>;
+			renesas,fcp = <&fcpvd1>;
+		};
+
 		fcpvd1: fcp@fea2f000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea2f000 0 0x200>;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread

[parent not found: <1518602108-1724-3-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>]

* Re: [PATCH v3 2/5] arm64: dts: renesas: r8a77995: add VSP instances
       [not found]   ` <1518602108-1724-3-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
@ 2018-02-15 16:33     ` Simon Horman
  2018-02-15 16:41       ` Kieran Bingham
  0 siblings, 1 reply; 13+ messages in thread
From: Simon Horman @ 2018-02-15 16:33 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Laurent Pinchart,
	Kieran Bingham, Kieran Bingham, Magnus Damm, Rob Herring,
	Mark Rutland, Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list

On Wed, Feb 14, 2018 at 09:55:05AM +0000, Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> 
> The r8a77995 has a VSPBS to support image processing such as blending of
> two input images, and has two VSPDs to handle display pipelines with a
> DU.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> 
> ---
> v2:
>  - Fix VSPD register map size
>  - Squash VSPBS and VSPD patches together
> 
> v3:
>  - Fix VSPBS register map size too :-)
> 
>  arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> index 196a917afea6..0db242114bc5 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -692,6 +692,16 @@
>  			status = "disabled";
>  		};
>  
> +		vspbs: vsp@fe960000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfe960000 0 0x8000>;
> +			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 627>;
> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> +			resets = <&cpg 627>;
> +			renesas,fcp = <&fcpvb0>;
> +		};
> +
>  		fcpvb0: fcp@fe96f000 {
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfe96f000 0 0x200>;
> @@ -701,6 +711,16 @@
>  			iommus = <&ipmmu_vp0 5>;
>  		};
>  
> +		vspd0: vsp@fea20000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfea20000 0 0x8000>;
> +			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 623>;
> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> +			resets = <&cpg 623>;
> +			renesas,fcp = <&fcpvd0>;
> +		};
> +
>  		fcpvd0: fcp@fea27000 {
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfea27000 0 0x200>;
> @@ -710,6 +730,16 @@
>  			iommus = <&ipmmu_vi0 8>;
>  		};
>  
> +		vspd1: vsp@fea80000 {

The above should be:

		vspd1: vsp@fea28000 {

> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfea28000 0 0x8000>;
> +			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 622>;
> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> +			resets = <&cpg 622>;
> +			renesas,fcp = <&fcpvd1>;
> +		};
> +
>  		fcpvd1: fcp@fea2f000 {
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfea2f000 0 0x200>;
> -- 
> 2.7.4
> 
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^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 2/5] arm64: dts: renesas: r8a77995: add VSP instances
  2018-02-15 16:33     ` Simon Horman
@ 2018-02-15 16:41       ` Kieran Bingham
       [not found]         ` <7db13491-f4f6-4c7c-e9e3-c1e91b0054b6-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
  0 siblings, 1 reply; 13+ messages in thread
From: Kieran Bingham @ 2018-02-15 16:41 UTC (permalink / raw)
  To: Simon Horman
  Cc: linux-renesas-soc, Laurent Pinchart, Kieran Bingham,
	Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list

Hi Simon,

On 15/02/18 16:33, Simon Horman wrote:
> On Wed, Feb 14, 2018 at 09:55:05AM +0000, Kieran Bingham wrote:
>> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>>
>> The r8a77995 has a VSPBS to support image processing such as blending of
>> two input images, and has two VSPDs to handle display pipelines with a
>> DU.
>>
>> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>>
>> ---
>> v2:
>>  - Fix VSPD register map size
>>  - Squash VSPBS and VSPD patches together
>>
>> v3:
>>  - Fix VSPBS register map size too :-)
>>
>>  arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++++
>>  1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> index 196a917afea6..0db242114bc5 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> @@ -692,6 +692,16 @@
>>  			status = "disabled";
>>  		};
>>  
>> +		vspbs: vsp@fe960000 {
>> +			compatible = "renesas,vsp2";
>> +			reg = <0 0xfe960000 0 0x8000>;
>> +			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&cpg CPG_MOD 627>;
>> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>> +			resets = <&cpg 627>;
>> +			renesas,fcp = <&fcpvb0>;
>> +		};
>> +
>>  		fcpvb0: fcp@fe96f000 {
>>  			compatible = "renesas,fcpv";
>>  			reg = <0 0xfe96f000 0 0x200>;
>> @@ -701,6 +711,16 @@
>>  			iommus = <&ipmmu_vp0 5>;
>>  		};
>>  
>> +		vspd0: vsp@fea20000 {
>> +			compatible = "renesas,vsp2";
>> +			reg = <0 0xfea20000 0 0x8000>;
>> +			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&cpg CPG_MOD 623>;
>> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>> +			resets = <&cpg 623>;
>> +			renesas,fcp = <&fcpvd0>;
>> +		};
>> +
>>  		fcpvd0: fcp@fea27000 {
>>  			compatible = "renesas,fcpv";
>>  			reg = <0 0xfea27000 0 0x200>;
>> @@ -710,6 +730,16 @@
>>  			iommus = <&ipmmu_vi0 8>;
>>  		};
>>  
>> +		vspd1: vsp@fea80000 {
> 
> The above should be:
> 
> 		vspd1: vsp@fea28000 {

Good spot.

</me looks to datasheet> That is correct.

Would you like me to resubmit this patch ? Or will you fix this up locally?

--
Regards

Kieran


> 
>> +			compatible = "renesas,vsp2";
>> +			reg = <0 0xfea28000 0 0x8000>;
>> +			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&cpg CPG_MOD 622>;
>> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>> +			resets = <&cpg 622>;
>> +			renesas,fcp = <&fcpvd1>;
>> +		};
>> +
>>  		fcpvd1: fcp@fea2f000 {
>>  			compatible = "renesas,fcpv";
>>  			reg = <0 0xfea2f000 0 0x200>;
>> -- 
>> 2.7.4
>>

^ permalink raw reply	[flat|nested] 13+ messages in thread

[parent not found: <7db13491-f4f6-4c7c-e9e3-c1e91b0054b6-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>]

* Re: [PATCH v3 2/5] arm64: dts: renesas: r8a77995: add VSP instances
       [not found]         ` <7db13491-f4f6-4c7c-e9e3-c1e91b0054b6-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
@ 2018-02-15 16:56           ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2018-02-15 16:56 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Laurent Pinchart,
	Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list

On Thu, Feb 15, 2018 at 04:41:58PM +0000, Kieran Bingham wrote:
> Hi Simon,
> 
> On 15/02/18 16:33, Simon Horman wrote:
> > On Wed, Feb 14, 2018 at 09:55:05AM +0000, Kieran Bingham wrote:
> >> From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> >>
> >> The r8a77995 has a VSPBS to support image processing such as blending of
> >> two input images, and has two VSPDs to handle display pipelines with a
> >> DU.
> >>
> >> Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> >> Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> >>
> >> ---
> >> v2:
> >>  - Fix VSPD register map size
> >>  - Squash VSPBS and VSPD patches together
> >>
> >> v3:
> >>  - Fix VSPBS register map size too :-)
> >>
> >>  arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++++
> >>  1 file changed, 30 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> >> index 196a917afea6..0db242114bc5 100644
> >> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> >> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> >> @@ -692,6 +692,16 @@
> >>  			status = "disabled";
> >>  		};
> >>  
> >> +		vspbs: vsp@fe960000 {
> >> +			compatible = "renesas,vsp2";
> >> +			reg = <0 0xfe960000 0 0x8000>;
> >> +			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
> >> +			clocks = <&cpg CPG_MOD 627>;
> >> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> >> +			resets = <&cpg 627>;
> >> +			renesas,fcp = <&fcpvb0>;
> >> +		};
> >> +
> >>  		fcpvb0: fcp@fe96f000 {
> >>  			compatible = "renesas,fcpv";
> >>  			reg = <0 0xfe96f000 0 0x200>;
> >> @@ -701,6 +711,16 @@
> >>  			iommus = <&ipmmu_vp0 5>;
> >>  		};
> >>  
> >> +		vspd0: vsp@fea20000 {
> >> +			compatible = "renesas,vsp2";
> >> +			reg = <0 0xfea20000 0 0x8000>;
> >> +			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> >> +			clocks = <&cpg CPG_MOD 623>;
> >> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> >> +			resets = <&cpg 623>;
> >> +			renesas,fcp = <&fcpvd0>;
> >> +		};
> >> +
> >>  		fcpvd0: fcp@fea27000 {
> >>  			compatible = "renesas,fcpv";
> >>  			reg = <0 0xfea27000 0 0x200>;
> >> @@ -710,6 +730,16 @@
> >>  			iommus = <&ipmmu_vi0 8>;
> >>  		};
> >>  
> >> +		vspd1: vsp@fea80000 {
> > 
> > The above should be:
> > 
> > 		vspd1: vsp@fea28000 {
> 
> Good spot.
> 
> </me looks to datasheet> That is correct.
> 
> Would you like me to resubmit this patch ? Or will you fix this up locally?

Thanks for confirming.

I noticed this using make dtbs W=1

I have fixed this up locally and applied your patch. The result is:


From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Subject: [PATCH] arm64: dts: renesas: r8a77995: add VSP instances

The r8a77995 has a VSPBS to support image processing such as blending of
two input images, and has two VSPDs to handle display pipelines with a
DU.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
[simon: updated base address of vsp node to fea28000]
Signed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 196a917afea6..0db242114bc5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -692,6 +692,16 @@
 			status = "disabled";
 		};
 
+		vspbs: vsp@fe960000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe960000 0 0x8000>;
+			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 627>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 627>;
+			renesas,fcp = <&fcpvb0>;
+		};
+
 		fcpvb0: fcp@fe96f000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xfe96f000 0 0x200>;
@@ -701,6 +711,16 @@
 			iommus = <&ipmmu_vp0 5>;
 		};
 
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x8000>;
+			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 623>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 623>;
+			renesas,fcp = <&fcpvd0>;
+		};
+
 		fcpvd0: fcp@fea27000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea27000 0 0x200>;
@@ -710,6 +730,16 @@
 			iommus = <&ipmmu_vi0 8>;
 		};
 
+		vspd1: vsp@fea80000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x8000>;
+			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 622>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 622>;
+			renesas,fcp = <&fcpvd1>;
+		};
+
 		fcpvd1: fcp@fea2f000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea2f000 0 0x200>;
-- 
2.11.0

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^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [PATCH v3 3/5] arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs
       [not found] <1518602108-1724-1-git-send-email-kbingham@kernel.org>
       [not found] ` <1518602108-1724-1-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
  2018-02-14  9:55 ` [PATCH v3 2/5] arm64: dts: renesas: r8a77995: add VSP instances Kieran Bingham
@ 2018-02-14  9:55 ` Kieran Bingham
       [not found]   ` <1518602108-1724-4-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
  2018-02-14  9:55 ` [PATCH v3 4/5] arm64: dts: renesas: r8a7795: " Kieran Bingham
  2018-02-14  9:55 ` [PATCH v3 5/5] arm64: dts: renesas: r8a7796: " Kieran Bingham
  4 siblings, 1 reply; 13+ messages in thread
From: Kieran Bingham @ 2018-02-14  9:55 UTC (permalink / raw)
  To: linux-renesas-soc, Simon Horman, Laurent Pinchart, Kieran Bingham
  Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list

From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>

The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index ed553338b4d4..1adfe6cad268 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -80,7 +80,7 @@
 
 	vspd3: vsp@fea38000 {
 		compatible = "renesas,vsp2";
-		reg = <0 0xfea38000 0 0x4000>;
+		reg = <0 0xfea38000 0 0x8000>;
 		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cpg CPG_MOD 620>;
 		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread

[parent not found: <1518602108-1724-4-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>]

* Re: [PATCH v3 3/5] arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs
       [not found]   ` <1518602108-1724-4-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
@ 2018-02-14 10:08     ` Laurent Pinchart
  2018-02-16 13:35       ` Simon Horman
  0 siblings, 1 reply; 13+ messages in thread
From: Laurent Pinchart @ 2018-02-14 10:08 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Simon Horman,
	Kieran Bingham, Kieran Bingham, Magnus Damm, Rob Herring,
	Mark Rutland, Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list

Hi Kieran,

Thank you for the patch.

On Wednesday, 14 February 2018 11:55:06 EET Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> 
> The VSPD includes a CLUT on RPF2. Ensure that the register space is
> mapped correctly to support this.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>

Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>

> ---
>  arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
> b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index
> ed553338b4d4..1adfe6cad268 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
> @@ -80,7 +80,7 @@
> 
>  	vspd3: vsp@fea38000 {
>  		compatible = "renesas,vsp2";
> -		reg = <0 0xfea38000 0 0x4000>;
> +		reg = <0 0xfea38000 0 0x8000>;
>  		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&cpg CPG_MOD 620>;
>  		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

-- 
Regards,

Laurent Pinchart

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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 3/5] arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs
  2018-02-14 10:08     ` Laurent Pinchart
@ 2018-02-16 13:35       ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2018-02-16 13:35 UTC (permalink / raw)
  To: Laurent Pinchart
  Cc: Kieran Bingham, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
	Kieran Bingham, Kieran Bingham, Magnus Damm, Rob Herring,
	Mark Rutland, Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list

On Wed, Feb 14, 2018 at 12:08:56PM +0200, Laurent Pinchart wrote:
> Hi Kieran,
> 
> Thank you for the patch.
> 
> On Wednesday, 14 February 2018 11:55:06 EET Kieran Bingham wrote:
> > From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> > 
> > The VSPD includes a CLUT on RPF2. Ensure that the register space is
> > mapped correctly to support this.
> > 
> > Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> 
> Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>

Thanks, applied.
--
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^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 4/5] arm64: dts: renesas: r8a7795: Fix register mappings on VSPs
       [not found] <1518602108-1724-1-git-send-email-kbingham@kernel.org>
                   ` (2 preceding siblings ...)
  2018-02-14  9:55 ` [PATCH v3 3/5] arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs Kieran Bingham
@ 2018-02-14  9:55 ` Kieran Bingham
  2018-02-16 13:36   ` Simon Horman
  2018-02-14  9:55 ` [PATCH v3 5/5] arm64: dts: renesas: r8a7796: " Kieran Bingham
  4 siblings, 1 reply; 13+ messages in thread
From: Kieran Bingham @ 2018-02-14  9:55 UTC (permalink / raw)
  To: linux-renesas-soc, Simon Horman, Laurent Pinchart, Kieran Bingham
  Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list

From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>

The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 1f32340af2d1..772991db8820 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -2607,7 +2607,7 @@
 
 		vspd0: vsp@fea20000 {
 			compatible = "renesas,vsp2";
-			reg = <0 0xfea20000 0 0x4000>;
+			reg = <0 0xfea20000 0 0x8000>;
 			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 623>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2627,7 +2627,7 @@
 
 		vspd1: vsp@fea28000 {
 			compatible = "renesas,vsp2";
-			reg = <0 0xfea28000 0 0x4000>;
+			reg = <0 0xfea28000 0 0x8000>;
 			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 622>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2647,7 +2647,7 @@
 
 		vspd2: vsp@fea30000 {
 			compatible = "renesas,vsp2";
-			reg = <0 0xfea30000 0 0x4000>;
+			reg = <0 0xfea30000 0 0x8000>;
 			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 621>;
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 4/5] arm64: dts: renesas: r8a7795: Fix register mappings on VSPs
  2018-02-14  9:55 ` [PATCH v3 4/5] arm64: dts: renesas: r8a7795: " Kieran Bingham
@ 2018-02-16 13:36   ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2018-02-16 13:36 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: linux-renesas-soc, Laurent Pinchart, Kieran Bingham, Mark Rutland,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Catalin Marinas, Magnus Damm, open list, Will Deacon, Rob Herring,
	Kieran Bingham, moderated list:ARM64 PORT AARCH64 ARCHITECTURE

On Wed, Feb 14, 2018 at 09:55:07AM +0000, Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> 
> The VSPD includes a CLUT on RPF2. Ensure that the register space is
> mapped correctly to support this.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Thanks, applied

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 5/5] arm64: dts: renesas: r8a7796: Fix register mappings on VSPs
       [not found] <1518602108-1724-1-git-send-email-kbingham@kernel.org>
                   ` (3 preceding siblings ...)
  2018-02-14  9:55 ` [PATCH v3 4/5] arm64: dts: renesas: r8a7795: " Kieran Bingham
@ 2018-02-14  9:55 ` Kieran Bingham
  2018-02-16 13:37   ` Simon Horman
  4 siblings, 1 reply; 13+ messages in thread
From: Kieran Bingham @ 2018-02-14  9:55 UTC (permalink / raw)
  To: linux-renesas-soc, Simon Horman, Laurent Pinchart, Kieran Bingham
  Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
	Catalin Marinas, Will Deacon,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list

From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>

The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 60755117cba5..3fe5566e0630 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -2285,7 +2285,7 @@
 
 		vspd0: vsp@fea20000 {
 			compatible = "renesas,vsp2";
-			reg = <0 0xfea20000 0 0x4000>;
+			reg = <0 0xfea20000 0 0x8000>;
 			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 623>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2305,7 +2305,7 @@
 
 		vspd1: vsp@fea28000 {
 			compatible = "renesas,vsp2";
-			reg = <0 0xfea28000 0 0x4000>;
+			reg = <0 0xfea28000 0 0x8000>;
 			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 622>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2325,7 +2325,7 @@
 
 		vspd2: vsp@fea30000 {
 			compatible = "renesas,vsp2";
-			reg = <0 0xfea30000 0 0x4000>;
+			reg = <0 0xfea30000 0 0x8000>;
 			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 621>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 5/5] arm64: dts: renesas: r8a7796: Fix register mappings on VSPs
  2018-02-14  9:55 ` [PATCH v3 5/5] arm64: dts: renesas: r8a7796: " Kieran Bingham
@ 2018-02-16 13:37   ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2018-02-16 13:37 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: linux-renesas-soc, Laurent Pinchart, Kieran Bingham, Mark Rutland,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Catalin Marinas, Magnus Damm, open list, Will Deacon, Rob Herring,
	Kieran Bingham, moderated list:ARM64 PORT AARCH64 ARCHITECTURE

On Wed, Feb 14, 2018 at 09:55:08AM +0000, Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> 
> The VSPD includes a CLUT on RPF2. Ensure that the register space is
> mapped correctly to support this.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Thanks, applied.

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2018-02-16 13:37 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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     [not found] ` <1518602108-1724-1-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2018-02-14  9:55   ` [PATCH v3 1/5] arm64: dts: renesas: r8a77995: add FCPV nodes Kieran Bingham
2018-02-15 16:28     ` Simon Horman
2018-02-14  9:55 ` [PATCH v3 2/5] arm64: dts: renesas: r8a77995: add VSP instances Kieran Bingham
     [not found]   ` <1518602108-1724-3-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2018-02-15 16:33     ` Simon Horman
2018-02-15 16:41       ` Kieran Bingham
     [not found]         ` <7db13491-f4f6-4c7c-e9e3-c1e91b0054b6-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
2018-02-15 16:56           ` Simon Horman
2018-02-14  9:55 ` [PATCH v3 3/5] arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs Kieran Bingham
     [not found]   ` <1518602108-1724-4-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2018-02-14 10:08     ` Laurent Pinchart
2018-02-16 13:35       ` Simon Horman
2018-02-14  9:55 ` [PATCH v3 4/5] arm64: dts: renesas: r8a7795: " Kieran Bingham
2018-02-16 13:36   ` Simon Horman
2018-02-14  9:55 ` [PATCH v3 5/5] arm64: dts: renesas: r8a7796: " Kieran Bingham
2018-02-16 13:37   ` Simon Horman

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