From mboxrd@z Thu Jan 1 00:00:00 1970 From: Russell King - ARM Linux Subject: Re: RFC: ARM Boot standard for passing device tree blob Date: Fri, 26 Mar 2010 23:03:43 +0000 Message-ID: <20100326230343.GC29179@n2100.arm.linux.org.uk> References: <20100325210409.GH24984@n2100.arm.linux.org.uk> <1269610665.807.51.camel@e102109-lin.cambridge.arm.com> <4BACF238.3040405@firmworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org To: Grant Likely Cc: Nicolas Pitre , Catalin Marinas , devicetree-discuss , Philippe Robin , David Rusling , Jeremy Kerr , Dave P Martin , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Fri, Mar 26, 2010 at 01:52:24PM -0600, Grant Likely wrote: > I could change the statement to something like, "virtually tagged or > indexed data cache(s) must be off", or drop the statement entirely > since it is implied by the requirement that the MMU must be off. 1. We're not going down the path of having differing conditions for different caches; to do so would mean that we'd need to have two entirely different sets of code to handle booting in the kernel. 2. No ARM CPU supports having the D-cache enabled without the MMU; the data cache needs to be told via the page tables what can be cached and what can't - it needs to be told that RAM can cached but IO devices must not be. In short, the MMU must always be off, which in turn means the D-cache must always be disabled.