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* ePAPR 1.1 to do list
@ 2010-08-30 21:34 Yoder Stuart-B08248
       [not found] ` <9696D7A991D0824DBA8DFAC74A9C5FA306688C2F-ofAVchDyotYzzZk0BCvKg5jmvxFtTJ+o0e7PPNI6Mm0@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Yoder Stuart-B08248 @ 2010-08-30 21:34 UTC (permalink / raw)
  To: parch-QRwYI7m9GJLYtjvyW6yDsg, devicetree-discuss

I've consolidated what I am aware of with respect to errors found in
1.0,
clarifications needed, and new mechanisms to go into ePAPR 1.1 into
a single list.

Let me know if you are aware of anything else.

ePAPR 1.1 To Do
---------------

1. Fix typos, misc cleanup

   -device_type="simple-bus" in 8572 soc node example (p.96)
   -p.51, line 27-- ET_EXEC is 0x2 not 0x1
   -p.41, broken cross reference
   -missing period on virtual reg on ns16550

2. Representation of hw threads in device trees

   -proposal:
 
<http://lists.ozlabs.org/pipermail/devicetree-discuss/2010-March/001927.
html>

3. Provide way for client program to determine type of
   MMU, without parsing device tree

     -proposal:
       -specify an enum value in R8
       -convey MMU type in dev tree as well

4. Define new spin table enable method that specifies
   that spin table is mapped cacheable and coherent
     -proposal:
        -"spin-table-v2"

5. more compact/consolidated representation of CPU nodes
   -if there are 16 or 64 identical CPUs specifying all
    properties in each can get very verbose
   -proposal:
      -move common properties to /cpus

6. Provide mechanism on CPU node to convey non-probeable
   aspects of which Power arch categories are implemented

7. For IMAs clarify
     -some places say virt must equal phys
     -but requirements on p.53 don't say that
     -how do OSes determine the physical address of the IMA
        -initial-mapped-area is optional

8. For DMA devices, define standard property that conveys the
   the address width a device is capable of?  e.g. a PCI
   device that can only address 32-bits.

9. stdout/stdin alias

10. ns16550 binding
   -why is number of interrupt specifiers undefined?

11. Multi-level caches (p. 18)
   -comment saying cache nodes must/shall be under a cpu node
    necessarily doesn't make sense
       -should qualify it saying-- it the node does not have another
place
        to stick it, use one of the cpu nodes

12. "label" property
   -make is standard

Regards,
Stuart

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2011-01-11 22:26 UTC | newest]

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-- links below jump to the message on this page --
2010-08-30 21:34 ePAPR 1.1 to do list Yoder Stuart-B08248
     [not found] ` <9696D7A991D0824DBA8DFAC74A9C5FA306688C2F-ofAVchDyotYzzZk0BCvKg5jmvxFtTJ+o0e7PPNI6Mm0@public.gmane.org>
2010-08-30 22:33   ` [Power.org:parch] " Scott Wood
     [not found]     ` <20100830173314.446aae02-1MYqz8GpK7RekFaExTCHk1jVikpgYyvb5NbjCUgZEJk@public.gmane.org>
2010-08-31  1:00       ` David Gibson
2010-09-13 18:17   ` Scott Wood
     [not found]     ` <20100913131752.54981fb1-1MYqz8GpK7RekFaExTCHk1jVikpgYyvb5NbjCUgZEJk@public.gmane.org>
2010-09-20  2:44       ` David Gibson
2011-01-11 22:14       ` Yoder Stuart-B08248
     [not found]         ` <9F6FE96B71CF29479FF1CDC8046E150301D94E-TcFNo7jSaXM0vywKSws3iq4g8xLGJsHaLnY5E4hWTkheoWH0uzbU5w@public.gmane.org>
2011-01-11 22:26           ` Scott Wood

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