From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Brown Subject: Re: Regarding hw irq to Linux irq mapping on ARM Date: Wed, 22 Sep 2010 11:54:39 +0100 Message-ID: <20100922105439.GB20986@sirena.org.uk> References: <20100922105111.GA20986@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20100922105111.GA20986@sirena.org.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Grant Likely Cc: Lorenzo Pieralisi , Benjamin Herrenschmidt , devicetree-discuss , linux-arm-kernel@lists.infradead.org, Jeremy Kerr , Eric Miao , Thomas Gleixner , Shaju Abraham List-Id: devicetree@vger.kernel.org On Wed, Sep 22, 2010 at 11:51:11AM +0100, Mark Brown wrote: > On Wed, Sep 22, 2010 at 12:08:17AM -0300, Grant Likely wrote: > > What's the irq handling latency on those? Glad I haven't had to deal > > with any of them yet. > Milisecondish, but depends on bus congestion and bus type. You need to > schedule a thread which then does one but typically more register I/O > operations on the device (read one or more IRQ status registers, and > typically write back to acknowledge the interrupts as well). These tend > for obvious reasons to be for low volume interrupts like jack detection. Incidentally, if you want to look at an implementation the wm831x contains an implementation of such a controller (in drivers/mfd/wm831x-irq.c) the structure of which has been cloned for quite a few of these chips.