Re: [PATCH 10/15] x86/ioapic: Add OF bindings for IO-APIC

[Sebastian Andrzej Siewior <bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>]

* Grant Likely | 2011-01-11 16:53:53 [-0700]:

>> +void __init ioapic_add_ofnode(struct device_node *np)
>> +{
>> +	int i;
>> +	int ret;
>> +	struct resource r;
>> +
>> +	ret = of_address_to_resource(np, 0, &r);
>> +	if (ret) {
>> +		printk(KERN_ERR "Failed to obtain address for %s\n",
>> +				np->full_name);
>> +		return;
>> +	}
>> +
>> +	for (i = 0; i < nr_ioapics; i++) {
>> +		if (r.start == mp_ioapics[i].apicaddr) {
>> +			struct irq_domain *id;
>> +
>> +			mp_of_ioapic[i].node = np;
>> +			id = kzalloc(sizeof(*id), GFP_KERNEL);
>> +			BUG_ON(!id);
>> +			id->controller = np;
>> +			id->xlate = ioapic_xlate;
>> +			id->priv = (void *)i;
>> +			add_interrupt_host(id);
>> +			return;
>> +		}
>
>I'm confused here.  Are there multiple ioapic's described by a single
>device tree node?

Yes, the CE4100 has two IO-APICs. It looks like the first one is
responsible for the "legacy devices" (like RTC) and the second one is
used for the "extra devices" like SPI controller, USB, ... The UART
however is not on the first IO-APIC but on the second.

Those two IO-APICs are not cascaded. The device tree contains the line
number of device to the io apic. The kernel computes then interrupt
number based on gsi_base + line_number where gsi_base is incremented by
the number of entries[0]. This interrupt number (gsi_base + line) is then
sent via apic bus to lapic which reports it as the active interrupt
source.

Sebastian