From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jamie Iles Subject: Re: [PATCHv2 08/10] ARM: u300: convert to MULTI_IRQ_HANDLER Date: Wed, 28 Sep 2011 13:03:40 +0100 Message-ID: <20110928120340.GH17204@pulham.picochip.com> References: <1317206507-18867-1-git-send-email-jamie@jamieiles.com> <1317206507-18867-9-git-send-email-jamie@jamieiles.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Linus Walleij Cc: kgene.kim@samsung.com, linux@arm.linux.org.uk, linus.walleij@stericsson.com, devicetree-discuss@lists.ozlabs.org, rob.herring@calxeda.com, hsweeten@visionengravers.com, rajeev-dlh.kumar@st.com, ben-linux@fluff.org, STEricsson_nomadik_linux@list.st.com, Jamie Iles , rubini@unipv.it, linux-arm-kernel@lists.infradead.org, rmallon@gmail.com List-Id: devicetree@vger.kernel.org Hi Linus, On Wed, Sep 28, 2011 at 01:03:34PM +0200, Linus Walleij wrote: > Hold your horses: > = > On Wed, Sep 28, 2011 at 12:41 PM, Jamie Iles wrote: > = > > diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/m= ach-u300/include/mach/entry-macro.S > > index 20731ae..7181d6a 100644 > > --- a/arch/arm/mach-u300/include/mach/entry-macro.S > > +++ b/arch/arm/mach-u300/include/mach/entry-macro.S > > @@ -8,33 +8,9 @@ > > =A0* Low-level IRQ helper macros for ST-Ericsson U300 > > =A0* Author: Linus Walleij > > =A0*/ > > -#include > > -#include > > > > =A0 =A0 =A0 =A0.macro =A0disable_fiq > > =A0 =A0 =A0 =A0.endm > > > > - =A0 =A0 =A0 .macro =A0get_irqnr_preamble, base, tmp > > - =A0 =A0 =A0 .endm > > - > > =A0 =A0 =A0 =A0.macro =A0arch_ret_to_user, tmp1, tmp2 > > =A0 =A0 =A0 =A0.endm > > - > > - =A0 =A0 =A0 .macro =A0get_irqnr_and_base, irqnr, irqstat, base, tmp > > - =A0 =A0 =A0 ldr =A0 =A0 \base, =3D U300_AHB_PER_VIRT_BASE-U300_AHB_PE= R_PHYS_BASE+U300_INTCON0_BASE > > - =A0 =A0 =A0 ldr =A0 =A0 \irqstat, [\base, #VIC_IRQ_STATUS] @ get mask= ed status > > - =A0 =A0 =A0 mov =A0 =A0 \irqnr, #0 > > - =A0 =A0 =A0 teq =A0 =A0 \irqstat, #0 > > - =A0 =A0 =A0 bne =A0 =A0 1002f > > -1001: =A0ldr =A0 =A0 \base, =3D U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PH= YS_BASE+U300_INTCON1_BASE > > - =A0 =A0 =A0 ldr =A0 =A0 \irqstat, [\base, #VIC_IRQ_STATUS] @ get mask= ed status > > - =A0 =A0 =A0 mov =A0 =A0 \irqnr, #32 > > - =A0 =A0 =A0 teq =A0 =A0 \irqstat, #0 > > - =A0 =A0 =A0 beq =A0 =A0 1003f > > -1002: =A0tst =A0 =A0 \irqstat, #1 > > - =A0 =A0 =A0 bne =A0 =A0 1003f > > - =A0 =A0 =A0 add =A0 =A0 \irqnr, \irqnr, #1 > > - =A0 =A0 =A0 movs =A0 =A0\irqstat, \irqstat, lsr #1 > > - =A0 =A0 =A0 bne =A0 =A0 1002b > > -1003: =A0 =A0 =A0 =A0 =A0/* EQ will be set if no irqs pending */ > > - =A0 =A0 =A0 .endm > = > When I inspect patch 2 in this series I get the feeling that it assumes t= hat > there is one and only one VIC bank with 32 interrupts involved. This is > not the case in the U300, it has 64 possible IRQ sources by OR:in the > output IRQ signal from two VIC:s and feeding the resulting IRQ line > into the CPU. No, it will handle more than one vic, and it will check them in the = order the vic_init() is called. I've tested this on picoxcell that has = 2 vic's in the same configuration as this. > So in the code above we first check the 32 bits at the first VIC instance, > and if that is zero we go on to check the other 32 bits. > = > vic_single_handle_irq() needs to be modified to handle several > ranges or atleast two. The platform IRQ handler is actually vic_handle_irq() that internally = calls vic_single_handle_irq() for each registered vic (in the order of = registration). > Note that in mach-u300/core.c we initialize each VIC like this: > vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); > vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); > = > So I think the easiest may be to let vic_init() add registered VIC > ranges to a list or array, and increas some num_vics variable > to that vic_single_handle_irq() can traverse both ranges in > order. Jamie