[PATCH 7/9] arm/tegra: emc: device tree bindings

[PATCH 7/9] arm/tegra: emc: device tree bindings

[Olof Johansson]

Device tree bindings for the EMC tables on tegra.

Signed-off-by: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
Cc: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
---
 .../devicetree/bindings/arm/tegra/emc.txt          |  100 ++++++++++++++++++++
 arch/arm/boot/dts/tegra20.dtsi                     |    7 ++
 2 files changed, 107 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/emc.txt

diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt b/Documentation/devicetree/bindings/arm/tegra/emc.txt
new file mode 100644
index 0000000..09335f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/emc.txt
@@ -0,0 +1,100 @@
+Embedded Memory Controller
+
+Properties:
+- name : Should be emc
+- #address-cells : Should be 1
+- #size-cells : Should be 0
+- compatible : Should contain "nvidia,tegra20-emc".
+- reg : Offset and length of the register set for the device
+- nvidia,use-ram-code : If present, the sub-nodes will be addressed
+  and chosen using the ramcode board selector. If omitted, only one
+  set of tables can be present and said tables will be used
+  irrespective of ram-code configuration.
+
+Child device nodes describe the memory settings for different configurations and clock rates.
+
+Example:
+
+	emc@7000f400 {
+		#address-cells = < 1 >;
+		#size-cells = < 0 >;
+		compatible = "nvidia,tegra20-emc";
+		reg = <0x7000f4000 0x200>;
+	}
+
+
+Embedded Memory Controller ram-code table
+
+If the emc node has the nvidia,use-ram-code property present, then the
+next level of nodes below the emc table are used to specify which settings
+apply for which ram-code settings.
+
+If the emc node lacks the nvidia,use-ram-code property, this level is omitted
+and the tables are stored directly under the emc node (see below).
+
+Properties:
+
+- name : Should be emc-tables
+- nvidia,ram-code : the binary representation of the ram-code board strappings
+  for which this node (and children) are valid.
+
+
+
+Embedded Memory Controller configuration table
+
+This is a table containing the EMC register settings for the various
+operating speeds of the memory controller. They are always located as
+subnodes of the emc controller node.
+
+There are two ways of specifying which tables to use:
+
+* The simplest is if there is just one set of tables in the device tree,
+  and they will always be used (based on which frequency is used).
+  This is the preferred method, especially when firmware can fill in
+  this information based on the specific system information and just
+  pass it on to the kernel.
+
+* The slightly more complex one is when more than one memory configuration
+  might exist on the system.  The Tegra20 platform handles this during
+  early boot by selecting one out of possible 4 memory settings based
+  on a 2-pin "ram code" bootstrap setting on the board. The values of
+  these strappings can be read through a register in the SoC, and thus
+  used to select which tables to use.
+
+Properties:
+- name : Should be emc-table
+- compatible : Should contain "nvidia,tegra20-emc-table".
+- reg : either an opaque enumerator to tell different tables apart, or
+  the valid frequency for which the table should be used (in kHz).
+- clock-frequency : the clock frequency for the EMC at which this
+  table should be used (in kHz).
+- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
+  for operation at the 'clock-frequency' setting.
+  The order and contents of the registers are:
+    RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
+    WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
+    PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
+    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
+    ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
+    ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
+    CFG_CLKTRIM_1, CFG_CLKTRIM_2
+
+		emc-table@166000 {
+			reg = <166000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 166000 >;
+			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 >;
+		};
+
+		emc-table@333000 {
+			reg = <333000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 333000 >;
+			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 >;
+		};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3da7afd..c162241 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -120,6 +120,13 @@
 		interrupts = < 0 91 0x04 >;
 	};
 
+	emc@7000f400 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-emc";
+		reg = <0x7000f400 0x200>;
+	};
+
 	sdhci@c8000000 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000000 0x200>;
-- 
1.7.8.GIT

Re: [PATCH 7/9] arm/tegra: emc: device tree bindings

[Grant Likely]

On Thu, Dec 22, 2011 at 04:17:46PM -0800, Olof Johansson wrote:
> Device tree bindings for the EMC tables on tegra.
> 
> Signed-off-by: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
> Cc: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org

Okay by me.

Acked-by: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>

> ---
>  .../devicetree/bindings/arm/tegra/emc.txt          |  100 ++++++++++++++++++++
>  arch/arm/boot/dts/tegra20.dtsi                     |    7 ++
>  2 files changed, 107 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/emc.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt b/Documentation/devicetree/bindings/arm/tegra/emc.txt
> new file mode 100644
> index 0000000..09335f8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/emc.txt
> @@ -0,0 +1,100 @@
> +Embedded Memory Controller
> +
> +Properties:
> +- name : Should be emc
> +- #address-cells : Should be 1
> +- #size-cells : Should be 0
> +- compatible : Should contain "nvidia,tegra20-emc".
> +- reg : Offset and length of the register set for the device
> +- nvidia,use-ram-code : If present, the sub-nodes will be addressed
> +  and chosen using the ramcode board selector. If omitted, only one
> +  set of tables can be present and said tables will be used
> +  irrespective of ram-code configuration.
> +
> +Child device nodes describe the memory settings for different configurations and clock rates.
> +
> +Example:
> +
> +	emc@7000f400 {
> +		#address-cells = < 1 >;
> +		#size-cells = < 0 >;
> +		compatible = "nvidia,tegra20-emc";
> +		reg = <0x7000f4000 0x200>;
> +	}
> +
> +
> +Embedded Memory Controller ram-code table
> +
> +If the emc node has the nvidia,use-ram-code property present, then the
> +next level of nodes below the emc table are used to specify which settings
> +apply for which ram-code settings.
> +
> +If the emc node lacks the nvidia,use-ram-code property, this level is omitted
> +and the tables are stored directly under the emc node (see below).
> +
> +Properties:
> +
> +- name : Should be emc-tables
> +- nvidia,ram-code : the binary representation of the ram-code board strappings
> +  for which this node (and children) are valid.
> +
> +
> +
> +Embedded Memory Controller configuration table
> +
> +This is a table containing the EMC register settings for the various
> +operating speeds of the memory controller. They are always located as
> +subnodes of the emc controller node.
> +
> +There are two ways of specifying which tables to use:
> +
> +* The simplest is if there is just one set of tables in the device tree,
> +  and they will always be used (based on which frequency is used).
> +  This is the preferred method, especially when firmware can fill in
> +  this information based on the specific system information and just
> +  pass it on to the kernel.
> +
> +* The slightly more complex one is when more than one memory configuration
> +  might exist on the system.  The Tegra20 platform handles this during
> +  early boot by selecting one out of possible 4 memory settings based
> +  on a 2-pin "ram code" bootstrap setting on the board. The values of
> +  these strappings can be read through a register in the SoC, and thus
> +  used to select which tables to use.
> +
> +Properties:
> +- name : Should be emc-table
> +- compatible : Should contain "nvidia,tegra20-emc-table".
> +- reg : either an opaque enumerator to tell different tables apart, or
> +  the valid frequency for which the table should be used (in kHz).
> +- clock-frequency : the clock frequency for the EMC at which this
> +  table should be used (in kHz).
> +- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
> +  for operation at the 'clock-frequency' setting.
> +  The order and contents of the registers are:
> +    RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
> +    WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
> +    PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
> +    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
> +    ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
> +    ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
> +    CFG_CLKTRIM_1, CFG_CLKTRIM_2
> +
> +		emc-table@166000 {
> +			reg = <166000>;
> +			compatible = "nvidia,tegra20-emc-table";
> +			clock-frequency = < 166000 >;
> +			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> +						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> +						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> +						 0 0 0 0 >;
> +		};
> +
> +		emc-table@333000 {
> +			reg = <333000>;
> +			compatible = "nvidia,tegra20-emc-table";
> +			clock-frequency = < 333000 >;
> +			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> +						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> +						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> +						 0 0 0 0 >;
> +		};
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 3da7afd..c162241 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -120,6 +120,13 @@
>  		interrupts = < 0 91 0x04 >;
>  	};
>  
> +	emc@7000f400 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "nvidia,tegra20-emc";
> +		reg = <0x7000f400 0x200>;
> +	};
> +
>  	sdhci@c8000000 {
>  		compatible = "nvidia,tegra20-sdhci";
>  		reg = <0xc8000000 0x200>;
> -- 
> 1.7.8.GIT
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss

RE: [PATCH 7/9] arm/tegra: emc: device tree bindings

[Stephen Warren]

Olof Johansson wrote at Thursday, December 22, 2011 5:18 PM:
> Device tree bindings for the EMC tables on tegra.
...
> diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt
...
> +Embedded Memory Controller ram-code table
...
> +- name : Should be emc-tables
> +- nvidia,ram-code : the binary representation of the ram-code board strappings
> +  for which this node (and children) are valid.
...
> +Embedded Memory Controller configuration table
...
> +- name : Should be emc-table
> +- compatible : Should contain "nvidia,tegra20-emc-table".
> +- reg : either an opaque enumerator to tell different tables apart, or
...

One more thought:

For consistency, should the "emc-tables" node also require a compatible
value? I suppose the existence of an "nvidia,ram-code" property is quite
likely to be indication enough that the node is compatible, but I wonder
if we shouldn't require and check an explicit compatible value at this
level too?

-- 
nvpublic

Re: [PATCH 7/9] arm/tegra: emc: device tree bindings

[Olof Johansson]

On Thu, Jan 5, 2012 at 4:01 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> Olof Johansson wrote at Thursday, December 22, 2011 5:18 PM:
>> Device tree bindings for the EMC tables on tegra.
> ...
>> diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt
> ...
>> +Embedded Memory Controller ram-code table
> ...
>> +- name : Should be emc-tables
>> +- nvidia,ram-code : the binary representation of the ram-code board strappings
>> +  for which this node (and children) are valid.
> ...
>> +Embedded Memory Controller configuration table
> ...
>> +- name : Should be emc-table
>> +- compatible : Should contain "nvidia,tegra20-emc-table".
>> +- reg : either an opaque enumerator to tell different tables apart, or
> ...
>
> One more thought:
>
> For consistency, should the "emc-tables" node also require a compatible
> value? I suppose the existence of an "nvidia,ram-code" property is quite
> likely to be indication enough that the node is compatible, but I wonder
> if we shouldn't require and check an explicit compatible value at this
> level too?

I can add it, it's trivial to add another check in
tegra_emc_ramcode_devnode, but I don't think there's much need to
bother. As long as nothing else is added that uses nvidia,ram-code as
a property we'll be OK, and we can control that.


-Olof

Re: [PATCH 7/9] arm/tegra: emc: device tree bindings

[Simon Glass]

Hi Olof,

On Thu, Jan 5, 2012 at 5:20 PM, Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> wrote:
> On Thu, Jan 5, 2012 at 4:01 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> Olof Johansson wrote at Thursday, December 22, 2011 5:18 PM:
>>> Device tree bindings for the EMC tables on tegra.
>> ...
>>> diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt
>> ...
>>> +Embedded Memory Controller ram-code table
>> ...
>>> +- name : Should be emc-tables
>>> +- nvidia,ram-code : the binary representation of the ram-code board strappings
>>> +  for which this node (and children) are valid.
>> ...
>>> +Embedded Memory Controller configuration table
>> ...
>>> +- name : Should be emc-table
>>> +- compatible : Should contain "nvidia,tegra20-emc-table".
>>> +- reg : either an opaque enumerator to tell different tables apart, or
>> ...
>>
>> One more thought:
>>
>> For consistency, should the "emc-tables" node also require a compatible
>> value? I suppose the existence of an "nvidia,ram-code" property is quite
>> likely to be indication enough that the node is compatible, but I wonder
>> if we shouldn't require and check an explicit compatible value at this
>> level too?
>
> I can add it, it's trivial to add another check in
> tegra_emc_ramcode_devnode, but I don't think there's much need to
> bother. As long as nothing else is added that uses nvidia,ram-code as
> a property we'll be OK, and we can control that.

I am looking at maybe bringing this into U-Boot.

Do you have an example of the ram-code table? Would it look something like this?

emc@7000f400 {
	#address-cells = < 1 >;
	#size-cells = < 0 >;
	compatible = "nvidia,tegra20-emc";
	reg = <0x7000f4000 0x200>;
	nvidia,use-ram-code;

	emc-tables@0 {
		nvidia,ram-code = <0>;
		compatible = "nvidia,tegra20-emc-tables";
		emc-table@166000 {
			reg = <166000>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = < 166000 >;
			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
						0 0 0 0 0 0 0 0 0 0 0 0 0 0
						0 0 0 0 0 0 0 0 0 0 0 0 0 0
						0 0 0 0 >;
		};
	};
	emc-tables@1 {
		nvidia,ram-code = <1>;
		compatible = "nvidia,tegra20-emc-tables";
		emc-table@333000 {
			reg = <333000>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = < 333000 >;
			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
						0 0 0 0 0 0 0 0 0 0 0 0 0 0
						0 0 0 0 0 0 0 0 0 0 0 0 0 0
						0 0 0 0 >;
		};
	};
	... @2, @3 follow
};

Also, can/should we be able to specify a frequency to override the strapping?

Regards,
Simon

>
>
> -Olof
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss

RE: [PATCH 7/9] arm/tegra: emc: device tree bindings

[Stephen Warren]

Simon Glass wrote at Thursday, January 12, 2012 1:04 PM:
> On Thu, Jan 5, 2012 at 5:20 PM, Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> wrote:
> > On Thu, Jan 5, 2012 at 4:01 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> >> Olof Johansson wrote at Thursday, December 22, 2011 5:18 PM:
> >>> Device tree bindings for the EMC tables on tegra.
...
> I am looking at maybe bringing this into U-Boot.
> 
> Do you have an example of the ram-code table? Would it look something like this?

There's an example for Seaboard here:

http://patchwork.ozlabs.org/patch/132929/

The base EMC node was added earlier in the patch series:

http://patchwork.ozlabs.org/patch/132928/

-- 
nvpublic

Re: [PATCH 7/9] arm/tegra: emc: device tree bindings

[Simon Glass]

Hi Stephen,

On Thu, Jan 12, 2012 at 12:50 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> Simon Glass wrote at Thursday, January 12, 2012 1:04 PM:
>> On Thu, Jan 5, 2012 at 5:20 PM, Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> wrote:
>> > On Thu, Jan 5, 2012 at 4:01 PM, Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> >> Olof Johansson wrote at Thursday, December 22, 2011 5:18 PM:
>> >>> Device tree bindings for the EMC tables on tegra.
> ...
>> I am looking at maybe bringing this into U-Boot.
>>
>> Do you have an example of the ram-code table? Would it look something like this?
>
> There's an example for Seaboard here:
>
> http://patchwork.ozlabs.org/patch/132929/
>
> The base EMC node was added earlier in the patch series:
>
> http://patchwork.ozlabs.org/patch/132928/

Thanks for that. There is a single level example, but from what I can
tell it will do fine for U-Boot.

Regards,
Simon

>
> --
> nvpublic
>

Re: [PATCH 7/9] arm/tegra: emc: device tree bindings

[Simon Glass]

Hi Olof,

On Thu, Dec 22, 2011 at 4:17 PM, Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> wrote:
> Device tree bindings for the EMC tables on tegra.
>
> Signed-off-by: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
> Cc: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> ---
>  .../devicetree/bindings/arm/tegra/emc.txt          |  100 ++++++++++++++++++++
>  arch/arm/boot/dts/tegra20.dtsi                     |    7 ++
>  2 files changed, 107 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/emc.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt b/Documentation/devicetree/bindings/arm/tegra/emc.txt
> new file mode 100644
> index 0000000..09335f8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/emc.txt
> @@ -0,0 +1,100 @@
> +Embedded Memory Controller
> +
> +Properties:
> +- name : Should be emc
> +- #address-cells : Should be 1
> +- #size-cells : Should be 0
> +- compatible : Should contain "nvidia,tegra20-emc".
> +- reg : Offset and length of the register set for the device
> +- nvidia,use-ram-code : If present, the sub-nodes will be addressed
> +  and chosen using the ramcode board selector. If omitted, only one
> +  set of tables can be present and said tables will be used
> +  irrespective of ram-code configuration.
> +
> +Child device nodes describe the memory settings for different configurations and clock rates.
> +
> +Example:
> +
> +       emc@7000f400 {
> +               #address-cells = < 1 >;
> +               #size-cells = < 0 >;
> +               compatible = "nvidia,tegra20-emc";
> +               reg = <0x7000f4000 0x200>;

Minor point - that should be 0x7000f400.

Regards,
SImon