From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: An extremely simplified pinctrl bindings proposal Date: Mon, 6 Feb 2012 11:03:15 -0800 Message-ID: <20120206190315.GU1426@atomide.com> References: <74CDBE0F657A3D45AFBB94109FB122FF178E5D3160@HQMAIL01.nvidia.com> <4F2F6AE2.1040504@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org To: Linus Walleij Cc: "cjb-2X9k7bc8m7Mdnm+yROfE0A@public.gmane.org" , Dong Aisheng , "devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" , "Sascha Hauer (s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org)" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org" , "kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: devicetree@vger.kernel.org * Linus Walleij [120206 08:58]: > On Mon, Feb 6, 2012 at 6:53 AM, Stephen Warren wrote: > > I will certainly finalize the pinctrl subsystem as-is, adding the > pin configurations states as the last major piece. If for nothing > else it provides some understanding of the problem space. > > I think we should keep both for the time being and consider the > alternative approach when patches appear. So if/when someone > creates a new subsystem like this, drivers can move over to it on a > per-driver basis. If there are zero drivers left in pinctrl it can be > deleted. Yes it seems that we can easily do both. So far the only change needed for pinctrl drivers containing no data is that we should make the string names optional and structure debugfs around the physical register addresses instead. I'm basically just setting the mux register physcal address as the pin name for now to work around this. Regards, Tony