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From: Grant Likely <grant.likely@secretlab.ca>
To: David Daney <david.daney@cavium.com>,
	Rob Herring <robherring2@gmail.com>
Cc: David Daney <ddaney.cavm@gmail.com>,
	linux-mips@linux-mips.org, ralf@linux-mips.org,
	devicetree-discuss@lists.ozlabs.org,
	Rob Herring <rob.herring@calxeda.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts.
Date: Fri, 02 Mar 2012 12:07:44 -0700	[thread overview]
Message-ID: <20120302190744.571E03E1C63@localhost> (raw)
In-Reply-To: <4F510B8E.3070201@cavium.com>

On Fri, 02 Mar 2012 10:03:58 -0800, David Daney <david.daney@cavium.com> wrote:
> On 03/02/2012 06:22 AM, Rob Herring wrote:
> [...]
> >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> >> index ce30e2f..01344ae 100644
> >> --- a/arch/mips/Kconfig
> >> +++ b/arch/mips/Kconfig
> >> @@ -1432,6 +1432,7 @@ config CPU_CAVIUM_OCTEON
> >>   	select WEAK_ORDERING
> >>   	select CPU_SUPPORTS_HIGHMEM
> >>   	select CPU_SUPPORTS_HUGEPAGES
> >> +	select IRQ_DOMAIN
> >
> > IIRC, Grant has a patch cued up that enables IRQ_DOMAIN for all of MIPS.
> >
> 
> Indeed, I now see it in linux-next.  I will remove this one.
> 
> >>   	help
> >>   	  The Cavium Octeon processor is a highly integrated chip containing
> >>   	  many ethernet hardware widgets for networking tasks. The processor
> >> diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
> >> index bdcedd3..e9f2f6c 100644
> >> --- a/arch/mips/cavium-octeon/octeon-irq.c
> >> +++ b/arch/mips/cavium-octeon/octeon-irq.c
> [...]
> >> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq,
> >> +					      unsigned int line,
> >> +					      unsigned int bit,
> >> +					      struct irq_domain *domain,
> >>   					      struct irq_chip *chip,
> >>   					      irq_flow_handler_t handler)
> >>   {
> >> +	struct irq_data *irqd;
> >>   	union octeon_ciu_chip_data cd;
> >>
> >>   	irq_set_chip_and_handler(irq, chip, handler);
> >> -
> >>   	cd.l = 0;
> >>   	cd.s.line = line;
> >>   	cd.s.bit = bit;
> >>
> >>   	irq_set_chip_data(irq, cd.p);
> >>   	octeon_irq_ciu_to_irq[line][bit] = irq;
> >> +
> >> +	irqd = irq_get_irq_data(irq);
> >> +	irqd->hwirq = line<<  6 | bit;
> >> +	irqd->domain = domain;
> >
> > I think the domain code will set these.
> 
> It is my understanding that the domain code only does this for:
> 
> o irq_domain_add_legacy()
> 
> o irq_create_direct_mapping()
> 
> o irq_create_mapping()
> 
> We use none of those.  So I do it here.
> 
> If there is a better way, I am open to suggestions.

irq_create_mapping is called by irq_create_of_mapping() which is
in turn called by irq_of_parse_and-map().  irq_domain always
manages the hwirq and domain values.  Driver code cannot manipulate
them manually.

g.

  reply	other threads:[~2012-03-02 19:07 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-01  0:56 [PATCH v6 0/5] MIPS: Octeon: Use Device Tree David Daney
2012-03-01  0:56 ` [PATCH v6 1/5] MIPS: Octeon: Add device tree source files David Daney
     [not found] ` <1330563422-14078-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-03-01  0:56   ` [PATCH v6 2/5] MIPS: Don't define early_init_devtree() and device_tree_init() in prom.c for CPU_CAVIUM_OCTEON David Daney
2012-03-01  0:57 ` [PATCH v6 3/5] MIPS: Octeon: Add irq handlers for GPIO interrupts David Daney
2012-03-01  0:57 ` [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts David Daney
2012-03-02 14:22   ` Rob Herring
2012-03-02 18:03     ` David Daney
2012-03-02 19:07       ` Grant Likely [this message]
2012-03-02 19:29         ` David Daney
     [not found]           ` <4F511FB0.5070901-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
2012-03-03 19:35             ` Rob Herring
     [not found]               ` <4F527285.1020500-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-03-04  5:09                 ` David Daney
2012-03-09  5:57                   ` Grant Likely
2012-03-09 18:45                     ` David Daney
2012-03-09 21:07                       ` Rob Herring
2012-03-10  0:08                         ` David Daney
     [not found]                           ` <4F5A9B75.8090301-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-03-10 16:20                             ` Rob Herring
2012-03-03 19:38       ` Rob Herring
2012-03-04  5:41         ` David Daney
2012-03-02 19:02   ` Grant Likely
2012-03-01  0:57 ` [PATCH v6 5/5] MIPS: Octeon: Initialize and fixup device tree David Daney

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