From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Gibson Subject: Re: Two different interrupt-parents Date: Mon, 16 Apr 2012 14:53:08 +1000 Message-ID: <20120416045308.GH4625@truffala.fritz.box> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org To: Sethi Varun-B16395 Cc: devicetree-discuss , "jonsmirl-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" List-Id: devicetree@vger.kernel.org On Mon, Apr 16, 2012 at 04:14:25AM +0000, Sethi Varun-B16395 wrote: > You can use a 4 cell interrupt specifier (we use that in case of embedded power architecture platforms) > - First cell corresponds to one of the four cascade lines (coming from the cascaded pic) > - Second cell provides the interrupt sense information > - Third one tells the interrupt subtype (in your case should be the cascade power interrupt type) > - Fourth cell communicates the interrupt number corresponding to the cascaded pic. > > There would be a single interrupt parent, which is the system interrupt controller. You would have > to translate the four cell interrupt specifier and also add cascaded interrupt handling > for the shared interrupt line. No, don't do that. Use the interrupt-map technique described in the thread that got linked earlier. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson