From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH 1/2] iommu/tegra: smmu: Add device tree support for SMMU Date: Fri, 11 May 2012 11:46:25 +0200 Message-ID: <20120511094625.GA11750@amd.com> References: <1336636221-31575-1-git-send-email-hdoyu@nvidia.com> <1336636221-31575-2-git-send-email-hdoyu@nvidia.com> <4FAC2041.7030405@wwwdotorg.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Return-path: Content-Disposition: inline In-Reply-To: <4FAC2041.7030405-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Stephen Warren Cc: Hiroshi DOYU , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Grant Likely , Rob Herring , Rob Landley , Ohad Ben-Cohen , Tony Lindgren , Jiri Kosina , Thierry Reding , devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On Thu, May 10, 2012 at 02:08:33PM -0600, Stephen Warren wrote: > On 05/10/2012 01:50 AM, Hiroshi DOYU wrote: > > The necessary info is expected to pass from DT. > > > > For more precise resource reservation, there shouldn't be any > > overlapping of register range between SMMU and MC. SMMU register > > offset needs to be calculated correctly, based on its register bank. > > > > Signed-off-by: Hiroshi DOYU > > Acked-by: Stephen Warren > > I expect patch 1 will go through the IOMMU tree, and I'll take patch 2 > through the Tegra tree. Any reason for splitting it up? The patches touch mostly drivers/iommu. So to avoid conflicts its probably the best to apply them together. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632