From: Borislav Petkov <borislav.petkov@amd.com>
To: Rob Herring <robherring2@gmail.com>
Cc: Mauro Carvalho Chehab <mchehab@redhat.com>,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree-discuss@lists.ozlabs.org
Subject: Re: [PATCH 1/2] edac: add support for Calxeda highbank memory controller
Date: Thu, 7 Jun 2012 14:44:52 +0200 [thread overview]
Message-ID: <20120607124452.GE11153@aftab.osrc.amd.com> (raw)
In-Reply-To: <4FCFE028.10005@gmail.com>
On Wed, Jun 06, 2012 at 05:56:40PM -0500, Rob Herring wrote:
> > Hmm... I suspect that memories by DIMM chip select/channel at Calxeda,
> > as it is using just 1 cs/channel. It probably makes more sense to add new layer
> > type(s) to properly represent the way your memory controller addresses it, if
> > Calxeda doesn't work with DIMMs.
>
> Not sure I follow. DIMMs are supported, but only a newer JEDEC form
> factor (DDR3 72-bit mini DIMM). The h/w pretty much fixed to a single
> 4GB DIMM. The controller is 1 72-bit channel.
Me too, why would this need a new define although those are more-or-less
normal DIMMs (modulo the form factor)?
--
Regards/Gruss,
Boris.
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
GM: Alberto Bozzo
Reg: Dornach, Landkreis Muenchen
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next prev parent reply other threads:[~2012-06-07 12:44 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-06 22:02 [PATCH 0/2] EDAC support for Calxeda Highbank Rob Herring
2012-06-06 22:02 ` [PATCH 1/2] edac: add support for Calxeda highbank memory controller Rob Herring
2012-06-06 22:34 ` Mauro Carvalho Chehab
2012-06-06 22:56 ` Rob Herring
2012-06-07 12:43 ` Borislav Petkov
2012-06-07 12:44 ` Borislav Petkov [this message]
2012-06-11 15:22 ` Mauro Carvalho Chehab
2012-06-08 1:12 ` Rob Herring
2012-06-11 15:25 ` Mauro Carvalho Chehab
2012-06-06 22:02 ` [PATCH 2/2] edac: add support for Calxeda highbank L2 cache ecc Rob Herring
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