[PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for samsung SoCs

[PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for samsung SoCs

[Praveen Paneri]

This patch set introduces a phy driver for samsung SoCs. It uses the existing
transceiver infrastructure to provide phy control functions. Use of this driver
can be extended for usb host phy as well. Over the period of time all the phy
related code for most of the samsung SoCs can be integrated here.
Removing the existing phy code from mach-s3c64xx but not from other machine 
code.This driver is tested with smdk6410 and Exynos4210(with DT).

Praveen Paneri (5):
  usb: phy: samsung: Introducing usb phy driver for hsotg
  usb: s3c-hsotg: Adding phy driver support
  ARM: S3C64XX: Removing old phy setup code
  ARM: S3C64XX: Enabling sec_usbphy driver
  ARM: Exynos4210: Enabling sec_usbphy driver

 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
 arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
 arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    5 +-
 arch/arm/mach-s3c64xx/mach-smartq.c                |    6 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    5 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
 arch/arm/plat-samsung/devs.c                       |   32 ++
 arch/arm/plat-samsung/include/plat/devs.h          |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
 drivers/usb/gadget/s3c-hsotg.c                     |   38 ++-
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/sec_usbphy.c                       |  354 ++++++++++++++++++++
 drivers/usb/phy/sec_usbphy.h                       |   48 +++
 include/linux/platform_data/s3c-hsotg.h            |    5 +
 19 files changed, 533 insertions(+), 88 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/sec_usbphy.c
 create mode 100644 drivers/usb/phy/sec_usbphy.h

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[PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Praveen Paneri]

This driver uses usb_phy interface to interact with s3c-hsotg. Supports
phy_init and phy_shutdown functions to enable/disable phy. Tested with
smdk6410 and smdkv310. More SoCs can be brought under later.

Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/sec_usbphy.c                       |  354 ++++++++++++++++++++
 drivers/usb/phy/sec_usbphy.h                       |   48 +++
 include/linux/platform_data/s3c-hsotg.h            |    5 +
 6 files changed, 425 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/sec_usbphy.c
 create mode 100644 drivers/usb/phy/sec_usbphy.h

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
new file mode 100644
index 0000000..fefd9c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -0,0 +1,9 @@
+* Samsung's usb phy transceiver
+
+The Samsung's phy transceiver is used for controlling usb otg phy for
+s3c-hsotg usb device controller.
+
+Required properties:
+- compatible : should be "samsung,exynos4210-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+	region.
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index e7cf84f..abbebe2 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -15,3 +15,11 @@ config USB_ISP1301
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called isp1301.
+
+config SEC_USBPHY
+       bool "Samsung USB PHY controller Driver"
+       depends on USB_S3C_HSOTG
+       select USB_OTG_UTILS
+       help
+         Enable this to support Samsung USB phy controller for samsung
+         SoCs.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..6bb66f0 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,3 +5,4 @@
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
+obj-$(CONFIG_SEC_USBPHY)		+= sec_usbphy.o
diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
new file mode 100644
index 0000000..33119eb
--- /dev/null
+++ b/drivers/usb/phy/sec_usbphy.c
@@ -0,0 +1,354 @@
+/* linux/drivers/usb/phy/sec_usbphy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/usb/otg.h>
+#include <linux/platform_data/s3c-hsotg.h>
+
+#include "sec_usbphy.h"
+
+enum sec_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_EXYNOS4210,
+};
+
+/*
+ * struct sec_usbphy - transceiver driver state
+ * @phy: transceiver structure
+ * @plat: platform data
+ * @dev: The parent device supplied to the probe function
+ * @clk: usb phy clock
+ * @regs: usb phy register memory base
+ * @cpu_type: machine identifier
+ */
+struct sec_usbphy {
+	struct usb_phy	phy;
+	struct s3c_usbphy_plat *plat;
+	struct device	*dev;
+	struct clk	*clk;
+	void __iomem	*regs;
+	int		cpu_type;
+};
+
+#define phy_to_sec(x)		container_of((x), struct sec_usbphy, phy)
+
+/*
+ * Enables or disables the phy clock
+ * returns 0 on success else the error
+ */
+static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
+{
+	if (on) {
+		if (!sec->clk) {
+			sec->clk = clk_get(sec->dev, "otg");
+			if (IS_ERR(sec->clk)) {
+				dev_err(sec->dev, "Failed to get otg clock\n");
+				return PTR_ERR(sec->clk);
+			}
+		}
+		clk_enable(sec->clk);
+	} else {
+		clk_disable(sec->clk);
+		clk_put(sec->clk);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns reference clock frequency
+ */
+static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
+{
+	struct clk *ref_clk;
+	int refclk_freq = 0;
+
+	ref_clk = clk_get(sec->dev, "xusbxti");
+	if (IS_ERR(ref_clk)) {
+		dev_err(sec->dev, "Failed to get reference clock\n");
+		return PTR_ERR(ref_clk);
+	}
+
+	switch (clk_get_rate(ref_clk)) {
+	case 12 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
+		break;
+	case 24 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
+		break;
+	default:
+	case 48 * MHZ:
+		/* default reference clock */
+		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
+		break;
+	}
+	clk_put(ref_clk);
+
+	return refclk_freq;
+}
+
+static void sec_usbphy_enable(struct sec_usbphy *sec)
+{
+	void __iomem *regs = sec->regs;
+	u32 phypwr;
+	u32 phyclk;
+	u32 rstcon;
+
+	/* set clock frequency for PLL */
+	phyclk = sec_usbphy_get_refclk_freq(sec);
+	phypwr = readl(regs + S3C_PHYPWR);
+	rstcon = readl(regs + S3C_RSTCON);
+
+	switch (sec->cpu_type) {
+	case TYPE_S3C64XX:
+		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
+		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+	default:
+		break;
+	}
+
+	writel(phyclk, regs + S3C_PHYCLK);
+	/* set to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+	/* reset all ports of PHY and Link */
+	writel(rstcon, regs + S3C_RSTCON);
+	udelay(10);
+	rstcon &= ~S3C_RSTCON_PHY;
+	writel(rstcon, regs + S3C_RSTCON);
+}
+
+static void sec_usbphy_disable(struct sec_usbphy *sec)
+{
+	void __iomem *regs = sec->regs;
+	u32 phypwr;
+
+	phypwr = readl(regs + S3C_PHYPWR);
+
+	switch (sec->cpu_type) {
+	case TYPE_S3C64XX:
+		phypwr |= S3C_PHYPWR_NORMAL_MASK;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
+	default:
+		break;
+	}
+
+	/* unset to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+}
+
+/*
+ * The function passed to the usb driver for phy initialization
+ */
+static int sec_usbphy_init(struct usb_phy *phy)
+{
+	struct sec_usbphy *sec;
+	int ret = 0;
+
+	sec = phy_to_sec(phy);
+
+	/* Enable the phy clock */
+	ret = sec_usbphy_clk_control(sec, true);
+	if (ret) {
+		dev_err(sec->dev, "phy clock enable failed\n");
+		return ret;
+	}
+
+	/* Disable phy isolation */
+	if (sec->plat && sec->plat->pmu_isolation)
+		sec->plat->pmu_isolation(false);
+
+	/* Initialize usb phy registers */
+	sec_usbphy_enable(sec);
+	return ret;
+}
+
+/*
+ * The function passed to the usb driver for phy shutdown
+ */
+static void sec_usbphy_shutdown(struct usb_phy *phy)
+{
+	struct sec_usbphy *sec;
+
+	sec = phy_to_sec(phy);
+
+	/* De-initialize usb phy registers */
+	sec_usbphy_disable(sec);
+
+	/* Enable phy isolation */
+	if (sec->plat && sec->plat->pmu_isolation)
+		sec->plat->pmu_isolation(true);
+
+	/* Disable the phy clock */
+	sec_usbphy_clk_control(sec, false);
+}
+
+static const struct of_device_id sec_usbphy_dt_match[];
+
+static inline int sec_usbphy_get_driver_data(struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+	int data;
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(sec_usbphy_dt_match, pdev->dev.of_node);
+		data = (int) match->data;
+		return data;
+	}
+#endif
+	return platform_get_device_id(pdev)->driver_data;
+}
+
+static int __devinit sec_usbphy_probe(struct platform_device *pdev)
+{
+	struct sec_usbphy *sec;
+	struct s3c_usbphy_plat *pdata;
+	struct device *dev = &pdev->dev;
+	struct resource *phy_mem;
+	void __iomem	*phy_base;
+	int	ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
+		return -EINVAL;
+	}
+
+	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!phy_mem) {
+		dev_err(dev, "%s: missing mem resource\n", __func__);
+		return -ENODEV;
+	}
+
+	phy_base = devm_request_and_ioremap(dev, phy_mem);
+	if (!phy_base) {
+		dev_err(dev, "%s: register mapping failed\n", __func__);
+		return -ENXIO;
+	}
+
+	sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
+	if (!sec)
+		return -ENOMEM;
+
+	sec->dev		= &pdev->dev;
+	sec->plat		= pdata;
+	sec->regs		= phy_base;
+	sec->phy.dev		= sec->dev;
+	sec->phy.label		= "sec-usbphy";
+	sec->phy.init		= sec_usbphy_init;
+	sec->phy.shutdown	= sec_usbphy_shutdown;
+	sec->cpu_type		= sec_usbphy_get_driver_data(pdev);
+
+	ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
+	if (ret)
+		goto err;
+
+	platform_set_drvdata(pdev, sec);
+
+	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
+err:
+	return ret;
+}
+
+static int __exit sec_usbphy_remove(struct platform_device *pdev)
+{
+	struct sec_usbphy *sec = platform_get_drvdata(pdev);
+
+	usb_remove_phy(&sec->phy);
+
+	if (sec->clk) {
+		clk_put(sec->clk);
+		sec->clk = NULL;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id sec_usbphy_dt_match[] = {
+	{
+		.compatible = "samsung,s3c64xx-usbphy",
+		.data = (void *)TYPE_S3C64XX,
+	}, {
+		.compatible = "samsung,exynos4210-usbphy",
+		.data = (void *)TYPE_EXYNOS4210,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
+#else
+#define sec_usbphy_dt_match NULL
+#endif
+
+static struct platform_device_id sec_usbphy_driver_ids[] = {
+	{
+		.name		= "s3c64xx-usbphy",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "exynos4210-usbphy",
+		.driver_data	= TYPE_EXYNOS4210,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
+
+static struct platform_driver sec_usbphy_driver = {
+	.probe		= sec_usbphy_probe,
+	.remove		= __devexit_p(sec_usbphy_remove),
+	.id_table	= sec_usbphy_driver_ids,
+	.driver		= {
+		.name	= "sec-usbphy",
+		.owner	= THIS_MODULE,
+		.of_match_table = sec_usbphy_dt_match,
+	},
+};
+
+static int __init sec_usbphy_driver_init(void)
+{
+	return platform_driver_register(&sec_usbphy_driver);
+}
+subsys_initcall(sec_usbphy_driver_init);
+
+static void __exit sec_usbphy_driver_exit(void)
+{
+	return platform_driver_unregister(&sec_usbphy_driver);
+}
+module_exit(sec_usbphy_driver_exit);
+
+MODULE_DESCRIPTION("Samsung USB phy controller");
+MODULE_AUTHOR("Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sec-usbphy");
diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
new file mode 100644
index 0000000..06e81d4
--- /dev/null
+++ b/drivers/usb/phy/sec_usbphy.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ * Author: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __SEC_USBPHY_H
+#define __SEC_USBPHY_H
+
+#define S3C_PHYPWR				(0x00)
+
+#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
+#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
+/* For Exynos4 */
+#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
+#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
+
+#define S3C_PHYCLK				(0x04)
+
+#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
+#define S3C_PHYCLK_EXT_OSC			(1 << 5)
+#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
+#define S3C_PHYCLK_ID_PULL			(1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
+#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
+
+#define S3C_RSTCON				(0x08)
+
+#define S3C_RSTCON_PHYCLK			(1 << 2)
+#define S3C_RSTCON_HCLK				(1 << 1)
+#define S3C_RSTCON_PHY				(1 << 0)
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#endif /* __SEC_USBPHY_H */
diff --git a/include/linux/platform_data/s3c-hsotg.h b/include/linux/platform_data/s3c-hsotg.h
index 8b79e09..25ed31e 100644
--- a/include/linux/platform_data/s3c-hsotg.h
+++ b/include/linux/platform_data/s3c-hsotg.h
@@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
 	int (*phy_exit)(struct platform_device *pdev, int type);
 };
 
+struct s3c_usbphy_plat {
+	void (*pmu_isolation)(int on);
+};
+
 extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
+extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
 
 #endif /* __LINUX_USB_S3C_HSOTG_H */
-- 
1.7.1

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Re: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Heiko Stübner]

Hi Praveen,

Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
> phy_init and phy_shutdown functions to enable/disable phy. Tested with
> smdk6410 and smdkv310. More SoCs can be brought under later.

Looks cool.

>From what I've seen the phy controllers on newer Samsung SoCs are still 
somewhat similar to the one on my s3c2416/2450 machines. So hopefully at some 
point after the driver has settled, I'll find the time to add support for 
these to the phy driver.

Out of curiosity, what does the "sec" in sec_usbphy for?



> Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>


Heiko


> ---
>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>  drivers/usb/phy/Kconfig                            |    8 +
>  drivers/usb/phy/Makefile                           |    1 +
>  drivers/usb/phy/sec_usbphy.c                       |  354
> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h                       | 
>  48 +++
>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>  6 files changed, 425 insertions(+), 0 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
> 100644 drivers/usb/phy/sec_usbphy.c
>  create mode 100644 drivers/usb/phy/sec_usbphy.h
> 
> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file mode
> 100644
> index 0000000..fefd9c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> @@ -0,0 +1,9 @@
> +* Samsung's usb phy transceiver
> +
> +The Samsung's phy transceiver is used for controlling usb otg phy for
> +s3c-hsotg usb device controller.
> +
> +Required properties:
> +- compatible : should be "samsung,exynos4210-usbphy"
> +- reg : base physical address of the phy registers and length of memory
> mapped +	region.
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index e7cf84f..abbebe2 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -15,3 +15,11 @@ config USB_ISP1301
> 
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called isp1301.
> +
> +config SEC_USBPHY
> +       bool "Samsung USB PHY controller Driver"
> +       depends on USB_S3C_HSOTG
> +       select USB_OTG_UTILS
> +       help
> +         Enable this to support Samsung USB phy controller for samsung
> +         SoCs.
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index eca095b..6bb66f0 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -5,3 +5,4 @@
>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
> 
>  obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
> +obj-$(CONFIG_SEC_USBPHY)		+= sec_usbphy.o
> diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
> new file mode 100644
> index 0000000..33119eb
> --- /dev/null
> +++ b/drivers/usb/phy/sec_usbphy.c
> @@ -0,0 +1,354 @@
> +/* linux/drivers/usb/phy/sec_usbphy.c
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> + *
> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
> controller + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> +*/
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/usb/otg.h>
> +#include <linux/platform_data/s3c-hsotg.h>
> +
> +#include "sec_usbphy.h"
> +
> +enum sec_cpu_type {
> +	TYPE_S3C64XX,
> +	TYPE_EXYNOS4210,
> +};
> +
> +/*
> + * struct sec_usbphy - transceiver driver state
> + * @phy: transceiver structure
> + * @plat: platform data
> + * @dev: The parent device supplied to the probe function
> + * @clk: usb phy clock
> + * @regs: usb phy register memory base
> + * @cpu_type: machine identifier
> + */
> +struct sec_usbphy {
> +	struct usb_phy	phy;
> +	struct s3c_usbphy_plat *plat;
> +	struct device	*dev;
> +	struct clk	*clk;
> +	void __iomem	*regs;
> +	int		cpu_type;
> +};
> +
> +#define phy_to_sec(x)		container_of((x), struct sec_usbphy, phy)
> +
> +/*
> + * Enables or disables the phy clock
> + * returns 0 on success else the error
> + */
> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
> +{
> +	if (on) {
> +		if (!sec->clk) {
> +			sec->clk = clk_get(sec->dev, "otg");
> +			if (IS_ERR(sec->clk)) {
> +				dev_err(sec->dev, "Failed to get otg clock\n");
> +				return PTR_ERR(sec->clk);
> +			}
> +		}
> +		clk_enable(sec->clk);
> +	} else {
> +		clk_disable(sec->clk);
> +		clk_put(sec->clk);
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Returns reference clock frequency
> + */
> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
> +{
> +	struct clk *ref_clk;
> +	int refclk_freq = 0;
> +
> +	ref_clk = clk_get(sec->dev, "xusbxti");
> +	if (IS_ERR(ref_clk)) {
> +		dev_err(sec->dev, "Failed to get reference clock\n");
> +		return PTR_ERR(ref_clk);
> +	}
> +
> +	switch (clk_get_rate(ref_clk)) {
> +	case 12 * MHZ:
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
> +		break;
> +	case 24 * MHZ:
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
> +		break;
> +	default:
> +	case 48 * MHZ:
> +		/* default reference clock */
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
> +		break;
> +	}
> +	clk_put(ref_clk);
> +
> +	return refclk_freq;
> +}
> +
> +static void sec_usbphy_enable(struct sec_usbphy *sec)
> +{
> +	void __iomem *regs = sec->regs;
> +	u32 phypwr;
> +	u32 phyclk;
> +	u32 rstcon;
> +
> +	/* set clock frequency for PLL */
> +	phyclk = sec_usbphy_get_refclk_freq(sec);
> +	phypwr = readl(regs + S3C_PHYPWR);
> +	rstcon = readl(regs + S3C_RSTCON);
> +
> +	switch (sec->cpu_type) {
> +	case TYPE_S3C64XX:
> +		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
> +		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
> +		rstcon |= S3C_RSTCON_PHY;
> +		break;
> +	case TYPE_EXYNOS4210:
> +		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
> +		rstcon |= S3C_RSTCON_PHY;
> +	default:
> +		break;
> +	}
> +
> +	writel(phyclk, regs + S3C_PHYCLK);
> +	/* set to normal of PHY0 */
> +	writel(phypwr, regs + S3C_PHYPWR);
> +	/* reset all ports of PHY and Link */
> +	writel(rstcon, regs + S3C_RSTCON);
> +	udelay(10);
> +	rstcon &= ~S3C_RSTCON_PHY;
> +	writel(rstcon, regs + S3C_RSTCON);
> +}
> +
> +static void sec_usbphy_disable(struct sec_usbphy *sec)
> +{
> +	void __iomem *regs = sec->regs;
> +	u32 phypwr;
> +
> +	phypwr = readl(regs + S3C_PHYPWR);
> +
> +	switch (sec->cpu_type) {
> +	case TYPE_S3C64XX:
> +		phypwr |= S3C_PHYPWR_NORMAL_MASK;
> +		break;
> +	case TYPE_EXYNOS4210:
> +		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
> +	default:
> +		break;
> +	}
> +
> +	/* unset to normal of PHY0 */
> +	writel(phypwr, regs + S3C_PHYPWR);
> +}
> +
> +/*
> + * The function passed to the usb driver for phy initialization
> + */
> +static int sec_usbphy_init(struct usb_phy *phy)
> +{
> +	struct sec_usbphy *sec;
> +	int ret = 0;
> +
> +	sec = phy_to_sec(phy);
> +
> +	/* Enable the phy clock */
> +	ret = sec_usbphy_clk_control(sec, true);
> +	if (ret) {
> +		dev_err(sec->dev, "phy clock enable failed\n");
> +		return ret;
> +	}
> +
> +	/* Disable phy isolation */
> +	if (sec->plat && sec->plat->pmu_isolation)
> +		sec->plat->pmu_isolation(false);
> +
> +	/* Initialize usb phy registers */
> +	sec_usbphy_enable(sec);
> +	return ret;
> +}
> +
> +/*
> + * The function passed to the usb driver for phy shutdown
> + */
> +static void sec_usbphy_shutdown(struct usb_phy *phy)
> +{
> +	struct sec_usbphy *sec;
> +
> +	sec = phy_to_sec(phy);
> +
> +	/* De-initialize usb phy registers */
> +	sec_usbphy_disable(sec);
> +
> +	/* Enable phy isolation */
> +	if (sec->plat && sec->plat->pmu_isolation)
> +		sec->plat->pmu_isolation(true);
> +
> +	/* Disable the phy clock */
> +	sec_usbphy_clk_control(sec, false);
> +}
> +
> +static const struct of_device_id sec_usbphy_dt_match[];
> +
> +static inline int sec_usbphy_get_driver_data(struct platform_device *pdev)
> +{
> +#ifdef CONFIG_OF
> +	int data;
> +	if (pdev->dev.of_node) {
> +		const struct of_device_id *match;
> +		match = of_match_node(sec_usbphy_dt_match, pdev->dev.of_node);
> +		data = (int) match->data;
> +		return data;
> +	}
> +#endif
> +	return platform_get_device_id(pdev)->driver_data;
> +}
> +
> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
> +{
> +	struct sec_usbphy *sec;
> +	struct s3c_usbphy_plat *pdata;
> +	struct device *dev = &pdev->dev;
> +	struct resource *phy_mem;
> +	void __iomem	*phy_base;
> +	int	ret;
> +
> +	pdata = pdev->dev.platform_data;
> +	if (!pdata) {
> +		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
> +		return -EINVAL;
> +	}
> +
> +	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!phy_mem) {
> +		dev_err(dev, "%s: missing mem resource\n", __func__);
> +		return -ENODEV;
> +	}
> +
> +	phy_base = devm_request_and_ioremap(dev, phy_mem);
> +	if (!phy_base) {
> +		dev_err(dev, "%s: register mapping failed\n", __func__);
> +		return -ENXIO;
> +	}
> +
> +	sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
> +	if (!sec)
> +		return -ENOMEM;
> +
> +	sec->dev		= &pdev->dev;
> +	sec->plat		= pdata;
> +	sec->regs		= phy_base;
> +	sec->phy.dev		= sec->dev;
> +	sec->phy.label		= "sec-usbphy";
> +	sec->phy.init		= sec_usbphy_init;
> +	sec->phy.shutdown	= sec_usbphy_shutdown;
> +	sec->cpu_type		= sec_usbphy_get_driver_data(pdev);
> +
> +	ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
> +	if (ret)
> +		goto err;
> +
> +	platform_set_drvdata(pdev, sec);
> +
> +	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
> +err:
> +	return ret;
> +}
> +
> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
> +{
> +	struct sec_usbphy *sec = platform_get_drvdata(pdev);
> +
> +	usb_remove_phy(&sec->phy);
> +
> +	if (sec->clk) {
> +		clk_put(sec->clk);
> +		sec->clk = NULL;
> +	}
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id sec_usbphy_dt_match[] = {
> +	{
> +		.compatible = "samsung,s3c64xx-usbphy",
> +		.data = (void *)TYPE_S3C64XX,
> +	}, {
> +		.compatible = "samsung,exynos4210-usbphy",
> +		.data = (void *)TYPE_EXYNOS4210,
> +	},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
> +#else
> +#define sec_usbphy_dt_match NULL
> +#endif
> +
> +static struct platform_device_id sec_usbphy_driver_ids[] = {
> +	{
> +		.name		= "s3c64xx-usbphy",
> +		.driver_data	= TYPE_S3C64XX,
> +	}, {
> +		.name		= "exynos4210-usbphy",
> +		.driver_data	= TYPE_EXYNOS4210,
> +	},
> +	{},
> +};
> +
> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
> +
> +static struct platform_driver sec_usbphy_driver = {
> +	.probe		= sec_usbphy_probe,
> +	.remove		= __devexit_p(sec_usbphy_remove),
> +	.id_table	= sec_usbphy_driver_ids,
> +	.driver		= {
> +		.name	= "sec-usbphy",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = sec_usbphy_dt_match,
> +	},
> +};
> +
> +static int __init sec_usbphy_driver_init(void)
> +{
> +	return platform_driver_register(&sec_usbphy_driver);
> +}
> +subsys_initcall(sec_usbphy_driver_init);
> +
> +static void __exit sec_usbphy_driver_exit(void)
> +{
> +	return platform_driver_unregister(&sec_usbphy_driver);
> +}
> +module_exit(sec_usbphy_driver_exit);
> +
> +MODULE_DESCRIPTION("Samsung USB phy controller");
> +MODULE_AUTHOR("Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:sec-usbphy");
> diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
> new file mode 100644
> index 0000000..06e81d4
> --- /dev/null
> +++ b/drivers/usb/phy/sec_usbphy.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> + * Author: Yulgon Kim <yulgon.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> + * Author: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> + *
> + * This program is free software; you can redistribute  it and/or modify
> it + * under  the terms of  the GNU General  Public License as published
> by the + * Free Software Foundation;  either version 2 of the  License, or
> (at your + * option) any later version.
> + */
> +
> +#ifndef __SEC_USBPHY_H
> +#define __SEC_USBPHY_H
> +
> +#define S3C_PHYPWR				(0x00)
> +
> +#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
> +#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
> +#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
> +#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
> +/* For Exynos4 */
> +#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
> +#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
> +
> +#define S3C_PHYCLK				(0x04)
> +
> +#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
> +#define S3C_PHYCLK_EXT_OSC			(1 << 5)
> +#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
> +#define S3C_PHYCLK_ID_PULL			(1 << 2)
> +#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
> +#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
> +#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
> +#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
> +#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
> +
> +#define S3C_RSTCON				(0x08)
> +
> +#define S3C_RSTCON_PHYCLK			(1 << 2)
> +#define S3C_RSTCON_HCLK				(1 << 1)
> +#define S3C_RSTCON_PHY				(1 << 0)
> +
> +#ifndef MHZ
> +#define MHZ (1000*1000)
> +#endif
> +
> +#endif /* __SEC_USBPHY_H */
> diff --git a/include/linux/platform_data/s3c-hsotg.h
> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
> --- a/include/linux/platform_data/s3c-hsotg.h
> +++ b/include/linux/platform_data/s3c-hsotg.h
> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>  	int (*phy_exit)(struct platform_device *pdev, int type);
>  };
> 
> +struct s3c_usbphy_plat {
> +	void (*pmu_isolation)(int on);
> +};
> +
>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
> 
>  #endif /* __LINUX_USB_S3C_HSOTG_H */

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Re: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Praveen Paneri]

Hi Heiko,

On Mon, Aug 6, 2012 at 3:24 AM, Heiko Stübner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> wrote:
> Hi Praveen,
>
> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>> smdk6410 and smdkv310. More SoCs can be brought under later.
>
> Looks cool.
Thanks
>
> From what I've seen the phy controllers on newer Samsung SoCs are still
> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at some
> point after the driver has settled, I'll find the time to add support for
> these to the phy driver.
Yes! that's great.
>
> Out of curiosity, what does the "sec" in sec_usbphy for?
Its Samsung Electronics Co. :)

Praveen
>
>
>
>> Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>
> Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
>
>
> Heiko
>
>
>> ---
>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>  drivers/usb/phy/Kconfig                            |    8 +
>>  drivers/usb/phy/Makefile                           |    1 +
>>  drivers/usb/phy/sec_usbphy.c                       |  354
>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h                       |
>>  48 +++
>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>  create mode 100644
>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>> 100644 drivers/usb/phy/sec_usbphy.c
>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>
>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file mode
>> 100644
>> index 0000000..fefd9c8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> @@ -0,0 +1,9 @@
>> +* Samsung's usb phy transceiver
>> +
>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>> +s3c-hsotg usb device controller.
>> +
>> +Required properties:
>> +- compatible : should be "samsung,exynos4210-usbphy"
>> +- reg : base physical address of the phy registers and length of memory
>> mapped +      region.
>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> index e7cf84f..abbebe2 100644
>> --- a/drivers/usb/phy/Kconfig
>> +++ b/drivers/usb/phy/Kconfig
>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>
>>         To compile this driver as a module, choose M here: the
>>         module will be called isp1301.
>> +
>> +config SEC_USBPHY
>> +       bool "Samsung USB PHY controller Driver"
>> +       depends on USB_S3C_HSOTG
>> +       select USB_OTG_UTILS
>> +       help
>> +         Enable this to support Samsung USB phy controller for samsung
>> +         SoCs.
>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>> index eca095b..6bb66f0 100644
>> --- a/drivers/usb/phy/Makefile
>> +++ b/drivers/usb/phy/Makefile
>> @@ -5,3 +5,4 @@
>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>
>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>> diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
>> new file mode 100644
>> index 0000000..33119eb
>> --- /dev/null
>> +++ b/drivers/usb/phy/sec_usbphy.c
>> @@ -0,0 +1,354 @@
>> +/* linux/drivers/usb/phy/sec_usbphy.c
>> + *
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + *              http://www.samsung.com
>> + *
>> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> + *
>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>> controller + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>> +*/
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/usb/otg.h>
>> +#include <linux/platform_data/s3c-hsotg.h>
>> +
>> +#include "sec_usbphy.h"
>> +
>> +enum sec_cpu_type {
>> +     TYPE_S3C64XX,
>> +     TYPE_EXYNOS4210,
>> +};
>> +
>> +/*
>> + * struct sec_usbphy - transceiver driver state
>> + * @phy: transceiver structure
>> + * @plat: platform data
>> + * @dev: The parent device supplied to the probe function
>> + * @clk: usb phy clock
>> + * @regs: usb phy register memory base
>> + * @cpu_type: machine identifier
>> + */
>> +struct sec_usbphy {
>> +     struct usb_phy  phy;
>> +     struct s3c_usbphy_plat *plat;
>> +     struct device   *dev;
>> +     struct clk      *clk;
>> +     void __iomem    *regs;
>> +     int             cpu_type;
>> +};
>> +
>> +#define phy_to_sec(x)                container_of((x), struct sec_usbphy, phy)
>> +
>> +/*
>> + * Enables or disables the phy clock
>> + * returns 0 on success else the error
>> + */
>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>> +{
>> +     if (on) {
>> +             if (!sec->clk) {
>> +                     sec->clk = clk_get(sec->dev, "otg");
>> +                     if (IS_ERR(sec->clk)) {
>> +                             dev_err(sec->dev, "Failed to get otg clock\n");
>> +                             return PTR_ERR(sec->clk);
>> +                     }
>> +             }
>> +             clk_enable(sec->clk);
>> +     } else {
>> +             clk_disable(sec->clk);
>> +             clk_put(sec->clk);
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +/*
>> + * Returns reference clock frequency
>> + */
>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>> +{
>> +     struct clk *ref_clk;
>> +     int refclk_freq = 0;
>> +
>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>> +     if (IS_ERR(ref_clk)) {
>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>> +             return PTR_ERR(ref_clk);
>> +     }
>> +
>> +     switch (clk_get_rate(ref_clk)) {
>> +     case 12 * MHZ:
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>> +             break;
>> +     case 24 * MHZ:
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>> +             break;
>> +     default:
>> +     case 48 * MHZ:
>> +             /* default reference clock */
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>> +             break;
>> +     }
>> +     clk_put(ref_clk);
>> +
>> +     return refclk_freq;
>> +}
>> +
>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>> +{
>> +     void __iomem *regs = sec->regs;
>> +     u32 phypwr;
>> +     u32 phyclk;
>> +     u32 rstcon;
>> +
>> +     /* set clock frequency for PLL */
>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>> +     phypwr = readl(regs + S3C_PHYPWR);
>> +     rstcon = readl(regs + S3C_RSTCON);
>> +
>> +     switch (sec->cpu_type) {
>> +     case TYPE_S3C64XX:
>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>> +             rstcon |= S3C_RSTCON_PHY;
>> +             break;
>> +     case TYPE_EXYNOS4210:
>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>> +             rstcon |= S3C_RSTCON_PHY;
>> +     default:
>> +             break;
>> +     }
>> +
>> +     writel(phyclk, regs + S3C_PHYCLK);
>> +     /* set to normal of PHY0 */
>> +     writel(phypwr, regs + S3C_PHYPWR);
>> +     /* reset all ports of PHY and Link */
>> +     writel(rstcon, regs + S3C_RSTCON);
>> +     udelay(10);
>> +     rstcon &= ~S3C_RSTCON_PHY;
>> +     writel(rstcon, regs + S3C_RSTCON);
>> +}
>> +
>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>> +{
>> +     void __iomem *regs = sec->regs;
>> +     u32 phypwr;
>> +
>> +     phypwr = readl(regs + S3C_PHYPWR);
>> +
>> +     switch (sec->cpu_type) {
>> +     case TYPE_S3C64XX:
>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>> +             break;
>> +     case TYPE_EXYNOS4210:
>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>> +     default:
>> +             break;
>> +     }
>> +
>> +     /* unset to normal of PHY0 */
>> +     writel(phypwr, regs + S3C_PHYPWR);
>> +}
>> +
>> +/*
>> + * The function passed to the usb driver for phy initialization
>> + */
>> +static int sec_usbphy_init(struct usb_phy *phy)
>> +{
>> +     struct sec_usbphy *sec;
>> +     int ret = 0;
>> +
>> +     sec = phy_to_sec(phy);
>> +
>> +     /* Enable the phy clock */
>> +     ret = sec_usbphy_clk_control(sec, true);
>> +     if (ret) {
>> +             dev_err(sec->dev, "phy clock enable failed\n");
>> +             return ret;
>> +     }
>> +
>> +     /* Disable phy isolation */
>> +     if (sec->plat && sec->plat->pmu_isolation)
>> +             sec->plat->pmu_isolation(false);
>> +
>> +     /* Initialize usb phy registers */
>> +     sec_usbphy_enable(sec);
>> +     return ret;
>> +}
>> +
>> +/*
>> + * The function passed to the usb driver for phy shutdown
>> + */
>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>> +{
>> +     struct sec_usbphy *sec;
>> +
>> +     sec = phy_to_sec(phy);
>> +
>> +     /* De-initialize usb phy registers */
>> +     sec_usbphy_disable(sec);
>> +
>> +     /* Enable phy isolation */
>> +     if (sec->plat && sec->plat->pmu_isolation)
>> +             sec->plat->pmu_isolation(true);
>> +
>> +     /* Disable the phy clock */
>> +     sec_usbphy_clk_control(sec, false);
>> +}
>> +
>> +static const struct of_device_id sec_usbphy_dt_match[];
>> +
>> +static inline int sec_usbphy_get_driver_data(struct platform_device *pdev)
>> +{
>> +#ifdef CONFIG_OF
>> +     int data;
>> +     if (pdev->dev.of_node) {
>> +             const struct of_device_id *match;
>> +             match = of_match_node(sec_usbphy_dt_match, pdev->dev.of_node);
>> +             data = (int) match->data;
>> +             return data;
>> +     }
>> +#endif
>> +     return platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>> +{
>> +     struct sec_usbphy *sec;
>> +     struct s3c_usbphy_plat *pdata;
>> +     struct device *dev = &pdev->dev;
>> +     struct resource *phy_mem;
>> +     void __iomem    *phy_base;
>> +     int     ret;
>> +
>> +     pdata = pdev->dev.platform_data;
>> +     if (!pdata) {
>> +             dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
>> +             return -EINVAL;
>> +     }
>> +
>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +     if (!phy_mem) {
>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>> +             return -ENODEV;
>> +     }
>> +
>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>> +     if (!phy_base) {
>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>> +             return -ENXIO;
>> +     }
>> +
>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>> +     if (!sec)
>> +             return -ENOMEM;
>> +
>> +     sec->dev                = &pdev->dev;
>> +     sec->plat               = pdata;
>> +     sec->regs               = phy_base;
>> +     sec->phy.dev            = sec->dev;
>> +     sec->phy.label          = "sec-usbphy";
>> +     sec->phy.init           = sec_usbphy_init;
>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>> +
>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>> +     if (ret)
>> +             goto err;
>> +
>> +     platform_set_drvdata(pdev, sec);
>> +
>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>> +err:
>> +     return ret;
>> +}
>> +
>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>> +{
>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>> +
>> +     usb_remove_phy(&sec->phy);
>> +
>> +     if (sec->clk) {
>> +             clk_put(sec->clk);
>> +             sec->clk = NULL;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>> +     {
>> +             .compatible = "samsung,s3c64xx-usbphy",
>> +             .data = (void *)TYPE_S3C64XX,
>> +     }, {
>> +             .compatible = "samsung,exynos4210-usbphy",
>> +             .data = (void *)TYPE_EXYNOS4210,
>> +     },
>> +     {},
>> +};
>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>> +#else
>> +#define sec_usbphy_dt_match NULL
>> +#endif
>> +
>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>> +     {
>> +             .name           = "s3c64xx-usbphy",
>> +             .driver_data    = TYPE_S3C64XX,
>> +     }, {
>> +             .name           = "exynos4210-usbphy",
>> +             .driver_data    = TYPE_EXYNOS4210,
>> +     },
>> +     {},
>> +};
>> +
>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>> +
>> +static struct platform_driver sec_usbphy_driver = {
>> +     .probe          = sec_usbphy_probe,
>> +     .remove         = __devexit_p(sec_usbphy_remove),
>> +     .id_table       = sec_usbphy_driver_ids,
>> +     .driver         = {
>> +             .name   = "sec-usbphy",
>> +             .owner  = THIS_MODULE,
>> +             .of_match_table = sec_usbphy_dt_match,
>> +     },
>> +};
>> +
>> +static int __init sec_usbphy_driver_init(void)
>> +{
>> +     return platform_driver_register(&sec_usbphy_driver);
>> +}
>> +subsys_initcall(sec_usbphy_driver_init);
>> +
>> +static void __exit sec_usbphy_driver_exit(void)
>> +{
>> +     return platform_driver_unregister(&sec_usbphy_driver);
>> +}
>> +module_exit(sec_usbphy_driver_exit);
>> +
>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>> +MODULE_AUTHOR("Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:sec-usbphy");
>> diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
>> new file mode 100644
>> index 0000000..06e81d4
>> --- /dev/null
>> +++ b/drivers/usb/phy/sec_usbphy.h
>> @@ -0,0 +1,48 @@
>> +/*
>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> + * Author: Yulgon Kim <yulgon.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> + * Author: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute  it and/or modify
>> it + * under  the terms of  the GNU General  Public License as published
>> by the + * Free Software Foundation;  either version 2 of the  License, or
>> (at your + * option) any later version.
>> + */
>> +
>> +#ifndef __SEC_USBPHY_H
>> +#define __SEC_USBPHY_H
>> +
>> +#define S3C_PHYPWR                           (0x00)
>> +
>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>> +/* For Exynos4 */
>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>> +
>> +#define S3C_PHYCLK                           (0x04)
>> +
>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>> +
>> +#define S3C_RSTCON                           (0x08)
>> +
>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>> +#define S3C_RSTCON_PHY                               (1 << 0)
>> +
>> +#ifndef MHZ
>> +#define MHZ (1000*1000)
>> +#endif
>> +
>> +#endif /* __SEC_USBPHY_H */
>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>> --- a/include/linux/platform_data/s3c-hsotg.h
>> +++ b/include/linux/platform_data/s3c-hsotg.h
>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>  };
>>
>> +struct s3c_usbphy_plat {
>> +     void (*pmu_isolation)(int on);
>> +};
>> +
>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>
>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>
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Re: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Kyungmin Park]

Hi Praveen,

On 8/6/12, Praveen Paneri <p.paneri@samsung.com> wrote:
> Hi Heiko,
>
> On Mon, Aug 6, 2012 at 3:24 AM, Heiko Stübner <heiko@sntech.de> wrote:
>> Hi Praveen,
>>
>> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>
>> Looks cool.
> Thanks
>>
>> From what I've seen the phy controllers on newer Samsung SoCs are still
>> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
>> some
>> point after the driver has settled, I'll find the time to add support for
>> these to the phy driver.
> Yes! that's great.
>>
>> Out of curiosity, what does the "sec" in sec_usbphy for?
> Its Samsung Electronics Co. :)
I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
'sec' prefix for samsung drivers.

Thank you,
Kyungmin Park
>
> Praveen
>>
>>
>>
>>> Signed-off-by: Praveen Paneri <p.paneri@samsung.com>
>>
>> Acked-by: Heiko Stuebner <heiko@sntech.de>
>>
>>
>> Heiko
>>
>>
>>> ---
>>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>>  drivers/usb/phy/Kconfig                            |    8 +
>>>  drivers/usb/phy/Makefile                           |    1 +
>>>  drivers/usb/phy/sec_usbphy.c                       |  354
>>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>>> |
>>>  48 +++
>>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>>  create mode 100644
>>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>>> 100644 drivers/usb/phy/sec_usbphy.c
>>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file mode
>>> 100644
>>> index 0000000..fefd9c8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> @@ -0,0 +1,9 @@
>>> +* Samsung's usb phy transceiver
>>> +
>>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>>> +s3c-hsotg usb device controller.
>>> +
>>> +Required properties:
>>> +- compatible : should be "samsung,exynos4210-usbphy"
>>> +- reg : base physical address of the phy registers and length of memory
>>> mapped +      region.
>>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>>> index e7cf84f..abbebe2 100644
>>> --- a/drivers/usb/phy/Kconfig
>>> +++ b/drivers/usb/phy/Kconfig
>>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>>
>>>         To compile this driver as a module, choose M here: the
>>>         module will be called isp1301.
>>> +
>>> +config SEC_USBPHY
>>> +       bool "Samsung USB PHY controller Driver"
>>> +       depends on USB_S3C_HSOTG
>>> +       select USB_OTG_UTILS
>>> +       help
>>> +         Enable this to support Samsung USB phy controller for samsung
>>> +         SoCs.
>>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>>> index eca095b..6bb66f0 100644
>>> --- a/drivers/usb/phy/Makefile
>>> +++ b/drivers/usb/phy/Makefile
>>> @@ -5,3 +5,4 @@
>>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>>
>>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>>> diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
>>> new file mode 100644
>>> index 0000000..33119eb
>>> --- /dev/null
>>> +++ b/drivers/usb/phy/sec_usbphy.c
>>> @@ -0,0 +1,354 @@
>>> +/* linux/drivers/usb/phy/sec_usbphy.c
>>> + *
>>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>>> + *              http://www.samsung.com
>>> + *
>>> + * Author: Praveen Paneri <p.paneri@samsung.com>
>>> + *
>>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>>> controller + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>>> +*/
>>> +
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/err.h>
>>> +#include <linux/io.h>
>>> +#include <linux/of.h>
>>> +#include <linux/usb/otg.h>
>>> +#include <linux/platform_data/s3c-hsotg.h>
>>> +
>>> +#include "sec_usbphy.h"
>>> +
>>> +enum sec_cpu_type {
>>> +     TYPE_S3C64XX,
>>> +     TYPE_EXYNOS4210,
>>> +};
>>> +
>>> +/*
>>> + * struct sec_usbphy - transceiver driver state
>>> + * @phy: transceiver structure
>>> + * @plat: platform data
>>> + * @dev: The parent device supplied to the probe function
>>> + * @clk: usb phy clock
>>> + * @regs: usb phy register memory base
>>> + * @cpu_type: machine identifier
>>> + */
>>> +struct sec_usbphy {
>>> +     struct usb_phy  phy;
>>> +     struct s3c_usbphy_plat *plat;
>>> +     struct device   *dev;
>>> +     struct clk      *clk;
>>> +     void __iomem    *regs;
>>> +     int             cpu_type;
>>> +};
>>> +
>>> +#define phy_to_sec(x)                container_of((x), struct
>>> sec_usbphy, phy)
>>> +
>>> +/*
>>> + * Enables or disables the phy clock
>>> + * returns 0 on success else the error
>>> + */
>>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>>> +{
>>> +     if (on) {
>>> +             if (!sec->clk) {
>>> +                     sec->clk = clk_get(sec->dev, "otg");
>>> +                     if (IS_ERR(sec->clk)) {
>>> +                             dev_err(sec->dev, "Failed to get otg
>>> clock\n");
>>> +                             return PTR_ERR(sec->clk);
>>> +                     }
>>> +             }
>>> +             clk_enable(sec->clk);
>>> +     } else {
>>> +             clk_disable(sec->clk);
>>> +             clk_put(sec->clk);
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +/*
>>> + * Returns reference clock frequency
>>> + */
>>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>>> +{
>>> +     struct clk *ref_clk;
>>> +     int refclk_freq = 0;
>>> +
>>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>>> +     if (IS_ERR(ref_clk)) {
>>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>>> +             return PTR_ERR(ref_clk);
>>> +     }
>>> +
>>> +     switch (clk_get_rate(ref_clk)) {
>>> +     case 12 * MHZ:
>>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>>> +             break;
>>> +     case 24 * MHZ:
>>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>>> +             break;
>>> +     default:
>>> +     case 48 * MHZ:
>>> +             /* default reference clock */
>>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>>> +             break;
>>> +     }
>>> +     clk_put(ref_clk);
>>> +
>>> +     return refclk_freq;
>>> +}
>>> +
>>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>>> +{
>>> +     void __iomem *regs = sec->regs;
>>> +     u32 phypwr;
>>> +     u32 phyclk;
>>> +     u32 rstcon;
>>> +
>>> +     /* set clock frequency for PLL */
>>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> +     rstcon = readl(regs + S3C_RSTCON);
>>> +
>>> +     switch (sec->cpu_type) {
>>> +     case TYPE_S3C64XX:
>>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>>> +             rstcon |= S3C_RSTCON_PHY;
>>> +             break;
>>> +     case TYPE_EXYNOS4210:
>>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>>> +             rstcon |= S3C_RSTCON_PHY;
>>> +     default:
>>> +             break;
>>> +     }
>>> +
>>> +     writel(phyclk, regs + S3C_PHYCLK);
>>> +     /* set to normal of PHY0 */
>>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> +     /* reset all ports of PHY and Link */
>>> +     writel(rstcon, regs + S3C_RSTCON);
>>> +     udelay(10);
>>> +     rstcon &= ~S3C_RSTCON_PHY;
>>> +     writel(rstcon, regs + S3C_RSTCON);
>>> +}
>>> +
>>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>>> +{
>>> +     void __iomem *regs = sec->regs;
>>> +     u32 phypwr;
>>> +
>>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> +
>>> +     switch (sec->cpu_type) {
>>> +     case TYPE_S3C64XX:
>>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>>> +             break;
>>> +     case TYPE_EXYNOS4210:
>>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>>> +     default:
>>> +             break;
>>> +     }
>>> +
>>> +     /* unset to normal of PHY0 */
>>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> +}
>>> +
>>> +/*
>>> + * The function passed to the usb driver for phy initialization
>>> + */
>>> +static int sec_usbphy_init(struct usb_phy *phy)
>>> +{
>>> +     struct sec_usbphy *sec;
>>> +     int ret = 0;
>>> +
>>> +     sec = phy_to_sec(phy);
>>> +
>>> +     /* Enable the phy clock */
>>> +     ret = sec_usbphy_clk_control(sec, true);
>>> +     if (ret) {
>>> +             dev_err(sec->dev, "phy clock enable failed\n");
>>> +             return ret;
>>> +     }
>>> +
>>> +     /* Disable phy isolation */
>>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> +             sec->plat->pmu_isolation(false);
>>> +
>>> +     /* Initialize usb phy registers */
>>> +     sec_usbphy_enable(sec);
>>> +     return ret;
>>> +}
>>> +
>>> +/*
>>> + * The function passed to the usb driver for phy shutdown
>>> + */
>>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>>> +{
>>> +     struct sec_usbphy *sec;
>>> +
>>> +     sec = phy_to_sec(phy);
>>> +
>>> +     /* De-initialize usb phy registers */
>>> +     sec_usbphy_disable(sec);
>>> +
>>> +     /* Enable phy isolation */
>>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> +             sec->plat->pmu_isolation(true);
>>> +
>>> +     /* Disable the phy clock */
>>> +     sec_usbphy_clk_control(sec, false);
>>> +}
>>> +
>>> +static const struct of_device_id sec_usbphy_dt_match[];
>>> +
>>> +static inline int sec_usbphy_get_driver_data(struct platform_device
>>> *pdev)
>>> +{
>>> +#ifdef CONFIG_OF
>>> +     int data;
>>> +     if (pdev->dev.of_node) {
>>> +             const struct of_device_id *match;
>>> +             match = of_match_node(sec_usbphy_dt_match,
>>> pdev->dev.of_node);
>>> +             data = (int) match->data;
>>> +             return data;
>>> +     }
>>> +#endif
>>> +     return platform_get_device_id(pdev)->driver_data;
>>> +}
>>> +
>>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>>> +{
>>> +     struct sec_usbphy *sec;
>>> +     struct s3c_usbphy_plat *pdata;
>>> +     struct device *dev = &pdev->dev;
>>> +     struct resource *phy_mem;
>>> +     void __iomem    *phy_base;
>>> +     int     ret;
>>> +
>>> +     pdata = pdev->dev.platform_data;
>>> +     if (!pdata) {
>>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>>> __func__);
>>> +             return -EINVAL;
>>> +     }
>>> +
>>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +     if (!phy_mem) {
>>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>>> +             return -ENODEV;
>>> +     }
>>> +
>>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>>> +     if (!phy_base) {
>>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>>> +             return -ENXIO;
>>> +     }
>>> +
>>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>>> +     if (!sec)
>>> +             return -ENOMEM;
>>> +
>>> +     sec->dev                = &pdev->dev;
>>> +     sec->plat               = pdata;
>>> +     sec->regs               = phy_base;
>>> +     sec->phy.dev            = sec->dev;
>>> +     sec->phy.label          = "sec-usbphy";
>>> +     sec->phy.init           = sec_usbphy_init;
>>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>>> +
>>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>>> +     if (ret)
>>> +             goto err;
>>> +
>>> +     platform_set_drvdata(pdev, sec);
>>> +
>>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>>> +err:
>>> +     return ret;
>>> +}
>>> +
>>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>>> +{
>>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>>> +
>>> +     usb_remove_phy(&sec->phy);
>>> +
>>> +     if (sec->clk) {
>>> +             clk_put(sec->clk);
>>> +             sec->clk = NULL;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_OF
>>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>>> +     {
>>> +             .compatible = "samsung,s3c64xx-usbphy",
>>> +             .data = (void *)TYPE_S3C64XX,
>>> +     }, {
>>> +             .compatible = "samsung,exynos4210-usbphy",
>>> +             .data = (void *)TYPE_EXYNOS4210,
>>> +     },
>>> +     {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>>> +#else
>>> +#define sec_usbphy_dt_match NULL
>>> +#endif
>>> +
>>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>>> +     {
>>> +             .name           = "s3c64xx-usbphy",
>>> +             .driver_data    = TYPE_S3C64XX,
>>> +     }, {
>>> +             .name           = "exynos4210-usbphy",
>>> +             .driver_data    = TYPE_EXYNOS4210,
>>> +     },
>>> +     {},
>>> +};
>>> +
>>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>>> +
>>> +static struct platform_driver sec_usbphy_driver = {
>>> +     .probe          = sec_usbphy_probe,
>>> +     .remove         = __devexit_p(sec_usbphy_remove),
>>> +     .id_table       = sec_usbphy_driver_ids,
>>> +     .driver         = {
>>> +             .name   = "sec-usbphy",
>>> +             .owner  = THIS_MODULE,
>>> +             .of_match_table = sec_usbphy_dt_match,
>>> +     },
>>> +};
>>> +
>>> +static int __init sec_usbphy_driver_init(void)
>>> +{
>>> +     return platform_driver_register(&sec_usbphy_driver);
>>> +}
>>> +subsys_initcall(sec_usbphy_driver_init);
>>> +
>>> +static void __exit sec_usbphy_driver_exit(void)
>>> +{
>>> +     return platform_driver_unregister(&sec_usbphy_driver);
>>> +}
>>> +module_exit(sec_usbphy_driver_exit);
>>> +
>>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>>> +MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
>>> +MODULE_LICENSE("GPL");
>>> +MODULE_ALIAS("platform:sec-usbphy");
>>> diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
>>> new file mode 100644
>>> index 0000000..06e81d4
>>> --- /dev/null
>>> +++ b/drivers/usb/phy/sec_usbphy.h
>>> @@ -0,0 +1,48 @@
>>> +/*
>>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>>> + * Author: Yulgon Kim <yulgon.kim@samsung.com>
>>> + * Author: Joonyoung Shim <jy0922.shim@samsung.com>
>>> + * Author: Praveen Paneri <p.paneri@samsung.com>
>>> + *
>>> + * This program is free software; you can redistribute  it and/or
>>> modify
>>> it + * under  the terms of  the GNU General  Public License as published
>>> by the + * Free Software Foundation;  either version 2 of the  License,
>>> or
>>> (at your + * option) any later version.
>>> + */
>>> +
>>> +#ifndef __SEC_USBPHY_H
>>> +#define __SEC_USBPHY_H
>>> +
>>> +#define S3C_PHYPWR                           (0x00)
>>> +
>>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>>> +/* For Exynos4 */
>>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>>> +
>>> +#define S3C_PHYCLK                           (0x04)
>>> +
>>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>>> +
>>> +#define S3C_RSTCON                           (0x08)
>>> +
>>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>>> +#define S3C_RSTCON_PHY                               (1 << 0)
>>> +
>>> +#ifndef MHZ
>>> +#define MHZ (1000*1000)
>>> +#endif
>>> +
>>> +#endif /* __SEC_USBPHY_H */
>>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>>> --- a/include/linux/platform_data/s3c-hsotg.h
>>> +++ b/include/linux/platform_data/s3c-hsotg.h
>>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>>  };
>>>
>>> +struct s3c_usbphy_plat {
>>> +     void (*pmu_isolation)(int on);
>>> +};
>>> +
>>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>>
>>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>>
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>

Re: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Heiko Stübner]

Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
> Hi Praveen,
> 
> On 8/6/12, Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> > Hi Heiko,
> > 
> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko Stübner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> wrote:
> >> Hi Praveen,
> >> 
> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
> >>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
> >> 
> >> Looks cool.
> > 
> > Thanks
> > 
> >> From what I've seen the phy controllers on newer Samsung SoCs are still
> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
> >> some
> >> point after the driver has settled, I'll find the time to add support
> >> for these to the phy driver.
> > 
> > Yes! that's great.
> > 
> >> Out of curiosity, what does the "sec" in sec_usbphy for?
> > 
> > Its Samsung Electronics Co. :)
> 
> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
> 'sec' prefix for samsung drivers.

I'd second that. All new generic samsung drivers look like this (i.e. gpio-
samsung, pwm-samsung).

Just checked the datasheets again. This general phy type is used in some form 
down to the S3C2443, so I'd prefer something with samsung in the name :-)


Heiko

> 
> Thank you,
> Kyungmin Park
> 
> > Praveen
> > 
> >>> Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >> 
> >> Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> >> 
> >> 
> >> Heiko
> >> 
> >>> ---
> >>> 
> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
> >>>  drivers/usb/phy/Kconfig                            |    8 +
> >>>  drivers/usb/phy/Makefile                           |    1 +
> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
> >>> 
> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
> >>> 
> >>>  48 +++
> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
> >>>  create mode 100644
> >>> 
> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
> >>> 100644 drivers/usb/phy/sec_usbphy.c
> >>> 
> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
> >>> 
> >>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
> >>> mode 100644
> >>> index 0000000..fefd9c8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> >>> @@ -0,0 +1,9 @@
> >>> +* Samsung's usb phy transceiver
> >>> +
> >>> +The Samsung's phy transceiver is used for controlling usb otg phy for
> >>> +s3c-hsotg usb device controller.
> >>> +
> >>> +Required properties:
> >>> +- compatible : should be "samsung,exynos4210-usbphy"
> >>> +- reg : base physical address of the phy registers and length of
> >>> memory mapped +      region.
> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> >>> index e7cf84f..abbebe2 100644
> >>> --- a/drivers/usb/phy/Kconfig
> >>> +++ b/drivers/usb/phy/Kconfig
> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
> >>> 
> >>>         To compile this driver as a module, choose M here: the
> >>>         module will be called isp1301.
> >>> 
> >>> +
> >>> +config SEC_USBPHY
> >>> +       bool "Samsung USB PHY controller Driver"
> >>> +       depends on USB_S3C_HSOTG
> >>> +       select USB_OTG_UTILS
> >>> +       help
> >>> +         Enable this to support Samsung USB phy controller for samsung
> >>> +         SoCs.
> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> >>> index eca095b..6bb66f0 100644
> >>> --- a/drivers/usb/phy/Makefile
> >>> +++ b/drivers/usb/phy/Makefile
> >>> @@ -5,3 +5,4 @@
> >>> 
> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
> >>>  
> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
> >>> 
> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
> >>> index 0000000..33119eb
> >>> --- /dev/null
> >>> +++ b/drivers/usb/phy/sec_usbphy.c
> >>> @@ -0,0 +1,354 @@
> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
> >>> + *
> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> >>> + *              http://www.samsung.com
> >>> + *
> >>> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >>> + *
> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
> >>> controller + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> modify + * it under the terms of the GNU General Public License
> >>> version 2 as + * published by the Free Software Foundation.
> >>> + *
> >>> + * This program is distributed in the hope that it will be useful,
> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> + * GNU General Public License for more details.
> >>> + *
> >>> + * You should have received a copy of the GNU General Public License
> >>> + * along with this program; if not, write to the Free Software
> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> >>> +*/
> >>> +
> >>> +#include <linux/module.h>
> >>> +#include <linux/platform_device.h>
> >>> +#include <linux/clk.h>
> >>> +#include <linux/delay.h>
> >>> +#include <linux/err.h>
> >>> +#include <linux/io.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/usb/otg.h>
> >>> +#include <linux/platform_data/s3c-hsotg.h>
> >>> +
> >>> +#include "sec_usbphy.h"
> >>> +
> >>> +enum sec_cpu_type {
> >>> +     TYPE_S3C64XX,
> >>> +     TYPE_EXYNOS4210,
> >>> +};
> >>> +
> >>> +/*
> >>> + * struct sec_usbphy - transceiver driver state
> >>> + * @phy: transceiver structure
> >>> + * @plat: platform data
> >>> + * @dev: The parent device supplied to the probe function
> >>> + * @clk: usb phy clock
> >>> + * @regs: usb phy register memory base
> >>> + * @cpu_type: machine identifier
> >>> + */
> >>> +struct sec_usbphy {
> >>> +     struct usb_phy  phy;
> >>> +     struct s3c_usbphy_plat *plat;
> >>> +     struct device   *dev;
> >>> +     struct clk      *clk;
> >>> +     void __iomem    *regs;
> >>> +     int             cpu_type;
> >>> +};
> >>> +
> >>> +#define phy_to_sec(x)                container_of((x), struct
> >>> sec_usbphy, phy)
> >>> +
> >>> +/*
> >>> + * Enables or disables the phy clock
> >>> + * returns 0 on success else the error
> >>> + */
> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
> >>> +{
> >>> +     if (on) {
> >>> +             if (!sec->clk) {
> >>> +                     sec->clk = clk_get(sec->dev, "otg");
> >>> +                     if (IS_ERR(sec->clk)) {
> >>> +                             dev_err(sec->dev, "Failed to get otg
> >>> clock\n");
> >>> +                             return PTR_ERR(sec->clk);
> >>> +                     }
> >>> +             }
> >>> +             clk_enable(sec->clk);
> >>> +     } else {
> >>> +             clk_disable(sec->clk);
> >>> +             clk_put(sec->clk);
> >>> +     }
> >>> +
> >>> +     return 0;
> >>> +}
> >>> +
> >>> +/*
> >>> + * Returns reference clock frequency
> >>> + */
> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
> >>> +{
> >>> +     struct clk *ref_clk;
> >>> +     int refclk_freq = 0;
> >>> +
> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
> >>> +     if (IS_ERR(ref_clk)) {
> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
> >>> +             return PTR_ERR(ref_clk);
> >>> +     }
> >>> +
> >>> +     switch (clk_get_rate(ref_clk)) {
> >>> +     case 12 * MHZ:
> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
> >>> +             break;
> >>> +     case 24 * MHZ:
> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
> >>> +             break;
> >>> +     default:
> >>> +     case 48 * MHZ:
> >>> +             /* default reference clock */
> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
> >>> +             break;
> >>> +     }
> >>> +     clk_put(ref_clk);
> >>> +
> >>> +     return refclk_freq;
> >>> +}
> >>> +
> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
> >>> +{
> >>> +     void __iomem *regs = sec->regs;
> >>> +     u32 phypwr;
> >>> +     u32 phyclk;
> >>> +     u32 rstcon;
> >>> +
> >>> +     /* set clock frequency for PLL */
> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
> >>> +     phypwr = readl(regs + S3C_PHYPWR);
> >>> +     rstcon = readl(regs + S3C_RSTCON);
> >>> +
> >>> +     switch (sec->cpu_type) {
> >>> +     case TYPE_S3C64XX:
> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
> >>> +             rstcon |= S3C_RSTCON_PHY;
> >>> +             break;
> >>> +     case TYPE_EXYNOS4210:
> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
> >>> +             rstcon |= S3C_RSTCON_PHY;
> >>> +     default:
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     writel(phyclk, regs + S3C_PHYCLK);
> >>> +     /* set to normal of PHY0 */
> >>> +     writel(phypwr, regs + S3C_PHYPWR);
> >>> +     /* reset all ports of PHY and Link */
> >>> +     writel(rstcon, regs + S3C_RSTCON);
> >>> +     udelay(10);
> >>> +     rstcon &= ~S3C_RSTCON_PHY;
> >>> +     writel(rstcon, regs + S3C_RSTCON);
> >>> +}
> >>> +
> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
> >>> +{
> >>> +     void __iomem *regs = sec->regs;
> >>> +     u32 phypwr;
> >>> +
> >>> +     phypwr = readl(regs + S3C_PHYPWR);
> >>> +
> >>> +     switch (sec->cpu_type) {
> >>> +     case TYPE_S3C64XX:
> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
> >>> +             break;
> >>> +     case TYPE_EXYNOS4210:
> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
> >>> +     default:
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     /* unset to normal of PHY0 */
> >>> +     writel(phypwr, regs + S3C_PHYPWR);
> >>> +}
> >>> +
> >>> +/*
> >>> + * The function passed to the usb driver for phy initialization
> >>> + */
> >>> +static int sec_usbphy_init(struct usb_phy *phy)
> >>> +{
> >>> +     struct sec_usbphy *sec;
> >>> +     int ret = 0;
> >>> +
> >>> +     sec = phy_to_sec(phy);
> >>> +
> >>> +     /* Enable the phy clock */
> >>> +     ret = sec_usbphy_clk_control(sec, true);
> >>> +     if (ret) {
> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
> >>> +             return ret;
> >>> +     }
> >>> +
> >>> +     /* Disable phy isolation */
> >>> +     if (sec->plat && sec->plat->pmu_isolation)
> >>> +             sec->plat->pmu_isolation(false);
> >>> +
> >>> +     /* Initialize usb phy registers */
> >>> +     sec_usbphy_enable(sec);
> >>> +     return ret;
> >>> +}
> >>> +
> >>> +/*
> >>> + * The function passed to the usb driver for phy shutdown
> >>> + */
> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
> >>> +{
> >>> +     struct sec_usbphy *sec;
> >>> +
> >>> +     sec = phy_to_sec(phy);
> >>> +
> >>> +     /* De-initialize usb phy registers */
> >>> +     sec_usbphy_disable(sec);
> >>> +
> >>> +     /* Enable phy isolation */
> >>> +     if (sec->plat && sec->plat->pmu_isolation)
> >>> +             sec->plat->pmu_isolation(true);
> >>> +
> >>> +     /* Disable the phy clock */
> >>> +     sec_usbphy_clk_control(sec, false);
> >>> +}
> >>> +
> >>> +static const struct of_device_id sec_usbphy_dt_match[];
> >>> +
> >>> +static inline int sec_usbphy_get_driver_data(struct platform_device
> >>> *pdev)
> >>> +{
> >>> +#ifdef CONFIG_OF
> >>> +     int data;
> >>> +     if (pdev->dev.of_node) {
> >>> +             const struct of_device_id *match;
> >>> +             match = of_match_node(sec_usbphy_dt_match,
> >>> pdev->dev.of_node);
> >>> +             data = (int) match->data;
> >>> +             return data;
> >>> +     }
> >>> +#endif
> >>> +     return platform_get_device_id(pdev)->driver_data;
> >>> +}
> >>> +
> >>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
> >>> +{
> >>> +     struct sec_usbphy *sec;
> >>> +     struct s3c_usbphy_plat *pdata;
> >>> +     struct device *dev = &pdev->dev;
> >>> +     struct resource *phy_mem;
> >>> +     void __iomem    *phy_base;
> >>> +     int     ret;
> >>> +
> >>> +     pdata = pdev->dev.platform_data;
> >>> +     if (!pdata) {
> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
> >>> __func__);
> >>> +             return -EINVAL;
> >>> +     }
> >>> +
> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>> +     if (!phy_mem) {
> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
> >>> +             return -ENODEV;
> >>> +     }
> >>> +
> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
> >>> +     if (!phy_base) {
> >>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
> >>> +             return -ENXIO;
> >>> +     }
> >>> +
> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
> >>> +     if (!sec)
> >>> +             return -ENOMEM;
> >>> +
> >>> +     sec->dev                = &pdev->dev;
> >>> +     sec->plat               = pdata;
> >>> +     sec->regs               = phy_base;
> >>> +     sec->phy.dev            = sec->dev;
> >>> +     sec->phy.label          = "sec-usbphy";
> >>> +     sec->phy.init           = sec_usbphy_init;
> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
> >>> +
> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
> >>> +     if (ret)
> >>> +             goto err;
> >>> +
> >>> +     platform_set_drvdata(pdev, sec);
> >>> +
> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
> >>> +err:
> >>> +     return ret;
> >>> +}
> >>> +
> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
> >>> +{
> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
> >>> +
> >>> +     usb_remove_phy(&sec->phy);
> >>> +
> >>> +     if (sec->clk) {
> >>> +             clk_put(sec->clk);
> >>> +             sec->clk = NULL;
> >>> +     }
> >>> +
> >>> +     return 0;
> >>> +}
> >>> +
> >>> +#ifdef CONFIG_OF
> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
> >>> +     {
> >>> +             .compatible = "samsung,s3c64xx-usbphy",
> >>> +             .data = (void *)TYPE_S3C64XX,
> >>> +     }, {
> >>> +             .compatible = "samsung,exynos4210-usbphy",
> >>> +             .data = (void *)TYPE_EXYNOS4210,
> >>> +     },
> >>> +     {},
> >>> +};
> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
> >>> +#else
> >>> +#define sec_usbphy_dt_match NULL
> >>> +#endif
> >>> +
> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
> >>> +     {
> >>> +             .name           = "s3c64xx-usbphy",
> >>> +             .driver_data    = TYPE_S3C64XX,
> >>> +     }, {
> >>> +             .name           = "exynos4210-usbphy",
> >>> +             .driver_data    = TYPE_EXYNOS4210,
> >>> +     },
> >>> +     {},
> >>> +};
> >>> +
> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
> >>> +
> >>> +static struct platform_driver sec_usbphy_driver = {
> >>> +     .probe          = sec_usbphy_probe,
> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
> >>> +     .id_table       = sec_usbphy_driver_ids,
> >>> +     .driver         = {
> >>> +             .name   = "sec-usbphy",
> >>> +             .owner  = THIS_MODULE,
> >>> +             .of_match_table = sec_usbphy_dt_match,
> >>> +     },
> >>> +};
> >>> +
> >>> +static int __init sec_usbphy_driver_init(void)
> >>> +{
> >>> +     return platform_driver_register(&sec_usbphy_driver);
> >>> +}
> >>> +subsys_initcall(sec_usbphy_driver_init);
> >>> +
> >>> +static void __exit sec_usbphy_driver_exit(void)
> >>> +{
> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
> >>> +}
> >>> +module_exit(sec_usbphy_driver_exit);
> >>> +
> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
> >>> +MODULE_LICENSE("GPL");
> >>> +MODULE_ALIAS("platform:sec-usbphy");
> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
> >>> index 0000000..06e81d4
> >>> --- /dev/null
> >>> +++ b/drivers/usb/phy/sec_usbphy.h
> >>> @@ -0,0 +1,48 @@
> >>> +/*
> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> >>> + * Author: Yulgon Kim <yulgon.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >>> + * Author: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >>> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >>> + *
> >>> + * This program is free software; you can redistribute  it and/or
> >>> modify
> >>> it + * under  the terms of  the GNU General  Public License as
> >>> published by the + * Free Software Foundation;  either version 2 of
> >>> the  License, or
> >>> (at your + * option) any later version.
> >>> + */
> >>> +
> >>> +#ifndef __SEC_USBPHY_H
> >>> +#define __SEC_USBPHY_H
> >>> +
> >>> +#define S3C_PHYPWR                           (0x00)
> >>> +
> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
> >>> +/* For Exynos4 */
> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
> >>> +
> >>> +#define S3C_PHYCLK                           (0x04)
> >>> +
> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
> >>> +
> >>> +#define S3C_RSTCON                           (0x08)
> >>> +
> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
> >>> +
> >>> +#ifndef MHZ
> >>> +#define MHZ (1000*1000)
> >>> +#endif
> >>> +
> >>> +#endif /* __SEC_USBPHY_H */
> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
> >>> --- a/include/linux/platform_data/s3c-hsotg.h
> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
> >>> 
> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
> >>>  
> >>>  };
> >>> 
> >>> +struct s3c_usbphy_plat {
> >>> +     void (*pmu_isolation)(int on);
> >>> +};
> >>> +
> >>> 
> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
> >>> 
> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
> >>> 
> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
> >> 
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> >> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-samsung-soc" in
> > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Praveen Paneri]

Hi,

On Mon, Aug 6, 2012 at 2:53 PM, Heiko Stübner <heiko@sntech.de> wrote:
> Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
>> Hi Praveen,
>>
>> On 8/6/12, Praveen Paneri <p.paneri@samsung.com> wrote:
>> > Hi Heiko,
>> >
>> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko Stübner <heiko@sntech.de> wrote:
>> >> Hi Praveen,
>> >>
>> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>> >>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
>> >>
>> >> Looks cool.
>> >
>> > Thanks
>> >
>> >> From what I've seen the phy controllers on newer Samsung SoCs are still
>> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
>> >> some
>> >> point after the driver has settled, I'll find the time to add support
>> >> for these to the phy driver.
>> >
>> > Yes! that's great.
>> >
>> >> Out of curiosity, what does the "sec" in sec_usbphy for?
>> >
>> > Its Samsung Electronics Co. :)
>>
>> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
>> 'sec' prefix for samsung drivers.
>
> I'd second that. All new generic samsung drivers look like this (i.e. gpio-
> samsung, pwm-samsung).
>
> Just checked the datasheets again. This general phy type is used in some form
> down to the S3C2443, so I'd prefer something with samsung in the name :-)
Yes! That makes sense. I will change the name to samsung_usbphy

Praveen
>
>
> Heiko
>
>>
>> Thank you,
>> Kyungmin Park
>>
>> > Praveen
>> >
>> >>> Signed-off-by: Praveen Paneri <p.paneri@samsung.com>
>> >>
>> >> Acked-by: Heiko Stuebner <heiko@sntech.de>
>> >>
>> >>
>> >> Heiko
>> >>
>> >>> ---
>> >>>
>> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>> >>>  drivers/usb/phy/Kconfig                            |    8 +
>> >>>  drivers/usb/phy/Makefile                           |    1 +
>> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
>> >>>
>> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>> >>>
>> >>>  48 +++
>> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
>> >>>  create mode 100644
>> >>>
>> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>> >>> 100644 drivers/usb/phy/sec_usbphy.c
>> >>>
>> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>> >>>
>> >>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
>> >>> mode 100644
>> >>> index 0000000..fefd9c8
>> >>> --- /dev/null
>> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> >>> @@ -0,0 +1,9 @@
>> >>> +* Samsung's usb phy transceiver
>> >>> +
>> >>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>> >>> +s3c-hsotg usb device controller.
>> >>> +
>> >>> +Required properties:
>> >>> +- compatible : should be "samsung,exynos4210-usbphy"
>> >>> +- reg : base physical address of the phy registers and length of
>> >>> memory mapped +      region.
>> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> >>> index e7cf84f..abbebe2 100644
>> >>> --- a/drivers/usb/phy/Kconfig
>> >>> +++ b/drivers/usb/phy/Kconfig
>> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
>> >>>
>> >>>         To compile this driver as a module, choose M here: the
>> >>>         module will be called isp1301.
>> >>>
>> >>> +
>> >>> +config SEC_USBPHY
>> >>> +       bool "Samsung USB PHY controller Driver"
>> >>> +       depends on USB_S3C_HSOTG
>> >>> +       select USB_OTG_UTILS
>> >>> +       help
>> >>> +         Enable this to support Samsung USB phy controller for samsung
>> >>> +         SoCs.
>> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>> >>> index eca095b..6bb66f0 100644
>> >>> --- a/drivers/usb/phy/Makefile
>> >>> +++ b/drivers/usb/phy/Makefile
>> >>> @@ -5,3 +5,4 @@
>> >>>
>> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>> >>>
>> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>> >>>
>> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
>> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
>> >>> index 0000000..33119eb
>> >>> --- /dev/null
>> >>> +++ b/drivers/usb/phy/sec_usbphy.c
>> >>> @@ -0,0 +1,354 @@
>> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
>> >>> + *
>> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> >>> + *              http://www.samsung.com
>> >>> + *
>> >>> + * Author: Praveen Paneri <p.paneri@samsung.com>
>> >>> + *
>> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>> >>> controller + *
>> >>> + * This program is free software; you can redistribute it and/or
>> >>> modify + * it under the terms of the GNU General Public License
>> >>> version 2 as + * published by the Free Software Foundation.
>> >>> + *
>> >>> + * This program is distributed in the hope that it will be useful,
>> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> >>> + * GNU General Public License for more details.
>> >>> + *
>> >>> + * You should have received a copy of the GNU General Public License
>> >>> + * along with this program; if not, write to the Free Software
>> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>> >>> +*/
>> >>> +
>> >>> +#include <linux/module.h>
>> >>> +#include <linux/platform_device.h>
>> >>> +#include <linux/clk.h>
>> >>> +#include <linux/delay.h>
>> >>> +#include <linux/err.h>
>> >>> +#include <linux/io.h>
>> >>> +#include <linux/of.h>
>> >>> +#include <linux/usb/otg.h>
>> >>> +#include <linux/platform_data/s3c-hsotg.h>
>> >>> +
>> >>> +#include "sec_usbphy.h"
>> >>> +
>> >>> +enum sec_cpu_type {
>> >>> +     TYPE_S3C64XX,
>> >>> +     TYPE_EXYNOS4210,
>> >>> +};
>> >>> +
>> >>> +/*
>> >>> + * struct sec_usbphy - transceiver driver state
>> >>> + * @phy: transceiver structure
>> >>> + * @plat: platform data
>> >>> + * @dev: The parent device supplied to the probe function
>> >>> + * @clk: usb phy clock
>> >>> + * @regs: usb phy register memory base
>> >>> + * @cpu_type: machine identifier
>> >>> + */
>> >>> +struct sec_usbphy {
>> >>> +     struct usb_phy  phy;
>> >>> +     struct s3c_usbphy_plat *plat;
>> >>> +     struct device   *dev;
>> >>> +     struct clk      *clk;
>> >>> +     void __iomem    *regs;
>> >>> +     int             cpu_type;
>> >>> +};
>> >>> +
>> >>> +#define phy_to_sec(x)                container_of((x), struct
>> >>> sec_usbphy, phy)
>> >>> +
>> >>> +/*
>> >>> + * Enables or disables the phy clock
>> >>> + * returns 0 on success else the error
>> >>> + */
>> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>> >>> +{
>> >>> +     if (on) {
>> >>> +             if (!sec->clk) {
>> >>> +                     sec->clk = clk_get(sec->dev, "otg");
>> >>> +                     if (IS_ERR(sec->clk)) {
>> >>> +                             dev_err(sec->dev, "Failed to get otg
>> >>> clock\n");
>> >>> +                             return PTR_ERR(sec->clk);
>> >>> +                     }
>> >>> +             }
>> >>> +             clk_enable(sec->clk);
>> >>> +     } else {
>> >>> +             clk_disable(sec->clk);
>> >>> +             clk_put(sec->clk);
>> >>> +     }
>> >>> +
>> >>> +     return 0;
>> >>> +}
>> >>> +
>> >>> +/*
>> >>> + * Returns reference clock frequency
>> >>> + */
>> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>> >>> +{
>> >>> +     struct clk *ref_clk;
>> >>> +     int refclk_freq = 0;
>> >>> +
>> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>> >>> +     if (IS_ERR(ref_clk)) {
>> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>> >>> +             return PTR_ERR(ref_clk);
>> >>> +     }
>> >>> +
>> >>> +     switch (clk_get_rate(ref_clk)) {
>> >>> +     case 12 * MHZ:
>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>> >>> +             break;
>> >>> +     case 24 * MHZ:
>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>> >>> +             break;
>> >>> +     default:
>> >>> +     case 48 * MHZ:
>> >>> +             /* default reference clock */
>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>> >>> +             break;
>> >>> +     }
>> >>> +     clk_put(ref_clk);
>> >>> +
>> >>> +     return refclk_freq;
>> >>> +}
>> >>> +
>> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>> >>> +{
>> >>> +     void __iomem *regs = sec->regs;
>> >>> +     u32 phypwr;
>> >>> +     u32 phyclk;
>> >>> +     u32 rstcon;
>> >>> +
>> >>> +     /* set clock frequency for PLL */
>> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>> >>> +     rstcon = readl(regs + S3C_RSTCON);
>> >>> +
>> >>> +     switch (sec->cpu_type) {
>> >>> +     case TYPE_S3C64XX:
>> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>> >>> +             rstcon |= S3C_RSTCON_PHY;
>> >>> +             break;
>> >>> +     case TYPE_EXYNOS4210:
>> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>> >>> +             rstcon |= S3C_RSTCON_PHY;
>> >>> +     default:
>> >>> +             break;
>> >>> +     }
>> >>> +
>> >>> +     writel(phyclk, regs + S3C_PHYCLK);
>> >>> +     /* set to normal of PHY0 */
>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>> >>> +     /* reset all ports of PHY and Link */
>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>> >>> +     udelay(10);
>> >>> +     rstcon &= ~S3C_RSTCON_PHY;
>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>> >>> +}
>> >>> +
>> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>> >>> +{
>> >>> +     void __iomem *regs = sec->regs;
>> >>> +     u32 phypwr;
>> >>> +
>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>> >>> +
>> >>> +     switch (sec->cpu_type) {
>> >>> +     case TYPE_S3C64XX:
>> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>> >>> +             break;
>> >>> +     case TYPE_EXYNOS4210:
>> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>> >>> +     default:
>> >>> +             break;
>> >>> +     }
>> >>> +
>> >>> +     /* unset to normal of PHY0 */
>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>> >>> +}
>> >>> +
>> >>> +/*
>> >>> + * The function passed to the usb driver for phy initialization
>> >>> + */
>> >>> +static int sec_usbphy_init(struct usb_phy *phy)
>> >>> +{
>> >>> +     struct sec_usbphy *sec;
>> >>> +     int ret = 0;
>> >>> +
>> >>> +     sec = phy_to_sec(phy);
>> >>> +
>> >>> +     /* Enable the phy clock */
>> >>> +     ret = sec_usbphy_clk_control(sec, true);
>> >>> +     if (ret) {
>> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
>> >>> +             return ret;
>> >>> +     }
>> >>> +
>> >>> +     /* Disable phy isolation */
>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>> >>> +             sec->plat->pmu_isolation(false);
>> >>> +
>> >>> +     /* Initialize usb phy registers */
>> >>> +     sec_usbphy_enable(sec);
>> >>> +     return ret;
>> >>> +}
>> >>> +
>> >>> +/*
>> >>> + * The function passed to the usb driver for phy shutdown
>> >>> + */
>> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>> >>> +{
>> >>> +     struct sec_usbphy *sec;
>> >>> +
>> >>> +     sec = phy_to_sec(phy);
>> >>> +
>> >>> +     /* De-initialize usb phy registers */
>> >>> +     sec_usbphy_disable(sec);
>> >>> +
>> >>> +     /* Enable phy isolation */
>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>> >>> +             sec->plat->pmu_isolation(true);
>> >>> +
>> >>> +     /* Disable the phy clock */
>> >>> +     sec_usbphy_clk_control(sec, false);
>> >>> +}
>> >>> +
>> >>> +static const struct of_device_id sec_usbphy_dt_match[];
>> >>> +
>> >>> +static inline int sec_usbphy_get_driver_data(struct platform_device
>> >>> *pdev)
>> >>> +{
>> >>> +#ifdef CONFIG_OF
>> >>> +     int data;
>> >>> +     if (pdev->dev.of_node) {
>> >>> +             const struct of_device_id *match;
>> >>> +             match = of_match_node(sec_usbphy_dt_match,
>> >>> pdev->dev.of_node);
>> >>> +             data = (int) match->data;
>> >>> +             return data;
>> >>> +     }
>> >>> +#endif
>> >>> +     return platform_get_device_id(pdev)->driver_data;
>> >>> +}
>> >>> +
>> >>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>> >>> +{
>> >>> +     struct sec_usbphy *sec;
>> >>> +     struct s3c_usbphy_plat *pdata;
>> >>> +     struct device *dev = &pdev->dev;
>> >>> +     struct resource *phy_mem;
>> >>> +     void __iomem    *phy_base;
>> >>> +     int     ret;
>> >>> +
>> >>> +     pdata = pdev->dev.platform_data;
>> >>> +     if (!pdata) {
>> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>> >>> __func__);
>> >>> +             return -EINVAL;
>> >>> +     }
>> >>> +
>> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> >>> +     if (!phy_mem) {
>> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>> >>> +             return -ENODEV;
>> >>> +     }
>> >>> +
>> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>> >>> +     if (!phy_base) {
>> >>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>> >>> +             return -ENXIO;
>> >>> +     }
>> >>> +
>> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>> >>> +     if (!sec)
>> >>> +             return -ENOMEM;
>> >>> +
>> >>> +     sec->dev                = &pdev->dev;
>> >>> +     sec->plat               = pdata;
>> >>> +     sec->regs               = phy_base;
>> >>> +     sec->phy.dev            = sec->dev;
>> >>> +     sec->phy.label          = "sec-usbphy";
>> >>> +     sec->phy.init           = sec_usbphy_init;
>> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>> >>> +
>> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>> >>> +     if (ret)
>> >>> +             goto err;
>> >>> +
>> >>> +     platform_set_drvdata(pdev, sec);
>> >>> +
>> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>> >>> +err:
>> >>> +     return ret;
>> >>> +}
>> >>> +
>> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>> >>> +{
>> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>> >>> +
>> >>> +     usb_remove_phy(&sec->phy);
>> >>> +
>> >>> +     if (sec->clk) {
>> >>> +             clk_put(sec->clk);
>> >>> +             sec->clk = NULL;
>> >>> +     }
>> >>> +
>> >>> +     return 0;
>> >>> +}
>> >>> +
>> >>> +#ifdef CONFIG_OF
>> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>> >>> +     {
>> >>> +             .compatible = "samsung,s3c64xx-usbphy",
>> >>> +             .data = (void *)TYPE_S3C64XX,
>> >>> +     }, {
>> >>> +             .compatible = "samsung,exynos4210-usbphy",
>> >>> +             .data = (void *)TYPE_EXYNOS4210,
>> >>> +     },
>> >>> +     {},
>> >>> +};
>> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>> >>> +#else
>> >>> +#define sec_usbphy_dt_match NULL
>> >>> +#endif
>> >>> +
>> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>> >>> +     {
>> >>> +             .name           = "s3c64xx-usbphy",
>> >>> +             .driver_data    = TYPE_S3C64XX,
>> >>> +     }, {
>> >>> +             .name           = "exynos4210-usbphy",
>> >>> +             .driver_data    = TYPE_EXYNOS4210,
>> >>> +     },
>> >>> +     {},
>> >>> +};
>> >>> +
>> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>> >>> +
>> >>> +static struct platform_driver sec_usbphy_driver = {
>> >>> +     .probe          = sec_usbphy_probe,
>> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
>> >>> +     .id_table       = sec_usbphy_driver_ids,
>> >>> +     .driver         = {
>> >>> +             .name   = "sec-usbphy",
>> >>> +             .owner  = THIS_MODULE,
>> >>> +             .of_match_table = sec_usbphy_dt_match,
>> >>> +     },
>> >>> +};
>> >>> +
>> >>> +static int __init sec_usbphy_driver_init(void)
>> >>> +{
>> >>> +     return platform_driver_register(&sec_usbphy_driver);
>> >>> +}
>> >>> +subsys_initcall(sec_usbphy_driver_init);
>> >>> +
>> >>> +static void __exit sec_usbphy_driver_exit(void)
>> >>> +{
>> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
>> >>> +}
>> >>> +module_exit(sec_usbphy_driver_exit);
>> >>> +
>> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
>> >>> +MODULE_LICENSE("GPL");
>> >>> +MODULE_ALIAS("platform:sec-usbphy");
>> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
>> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
>> >>> index 0000000..06e81d4
>> >>> --- /dev/null
>> >>> +++ b/drivers/usb/phy/sec_usbphy.h
>> >>> @@ -0,0 +1,48 @@
>> >>> +/*
>> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> >>> + * Author: Yulgon Kim <yulgon.kim@samsung.com>
>> >>> + * Author: Joonyoung Shim <jy0922.shim@samsung.com>
>> >>> + * Author: Praveen Paneri <p.paneri@samsung.com>
>> >>> + *
>> >>> + * This program is free software; you can redistribute  it and/or
>> >>> modify
>> >>> it + * under  the terms of  the GNU General  Public License as
>> >>> published by the + * Free Software Foundation;  either version 2 of
>> >>> the  License, or
>> >>> (at your + * option) any later version.
>> >>> + */
>> >>> +
>> >>> +#ifndef __SEC_USBPHY_H
>> >>> +#define __SEC_USBPHY_H
>> >>> +
>> >>> +#define S3C_PHYPWR                           (0x00)
>> >>> +
>> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>> >>> +/* For Exynos4 */
>> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>> >>> +
>> >>> +#define S3C_PHYCLK                           (0x04)
>> >>> +
>> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>> >>> +
>> >>> +#define S3C_RSTCON                           (0x08)
>> >>> +
>> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
>> >>> +
>> >>> +#ifndef MHZ
>> >>> +#define MHZ (1000*1000)
>> >>> +#endif
>> >>> +
>> >>> +#endif /* __SEC_USBPHY_H */
>> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>> >>> --- a/include/linux/platform_data/s3c-hsotg.h
>> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
>> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>> >>>
>> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
>> >>>
>> >>>  };
>> >>>
>> >>> +struct s3c_usbphy_plat {
>> >>> +     void (*pmu_isolation)(int on);
>> >>> +};
>> >>> +
>> >>>
>> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>> >>>
>> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>> >>>
>> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>> >>
>> >> --
>> >> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
>> >> the body of a message to majordomo@vger.kernel.org
>> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe
>> > linux-samsung-soc" in
>> > the body of a message to majordomo@vger.kernel.org
>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Praveen Paneri]

Hi,

On Mon, Aug 6, 2012 at 3:21 PM, Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> Hi,
>
> On Mon, Aug 6, 2012 at 2:53 PM, Heiko Stübner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> wrote:
>> Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
>>> Hi Praveen,
>>>
>>> On 8/6/12, Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>>> > Hi Heiko,
>>> >
>>> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko Stübner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> wrote:
>>> >> Hi Praveen,
>>> >>
>>> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>>> >>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>>> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>>> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>> >>
>>> >> Looks cool.
>>> >
>>> > Thanks
>>> >
>>> >> From what I've seen the phy controllers on newer Samsung SoCs are still
>>> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
>>> >> some
>>> >> point after the driver has settled, I'll find the time to add support
>>> >> for these to the phy driver.
>>> >
>>> > Yes! that's great.
>>> >
>>> >> Out of curiosity, what does the "sec" in sec_usbphy for?
>>> >
>>> > Its Samsung Electronics Co. :)
>>>
>>> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
>>> 'sec' prefix for samsung drivers.
>>
>> I'd second that. All new generic samsung drivers look like this (i.e. gpio-
>> samsung, pwm-samsung).
On the second thought I am thinking 'sec' is shorter and cooler. I
know that it has not
been used anywhere else but there is always a first time :-P The
shorter string helps in
writing the code; especially when we have 80 character restriction. If
you go through
this driver itself you will realize this. Also there was a suggestion
some time back to
use 'sec' instead of 'samsung'.
This is just my view about it. Please comment.

Praveen

>>
>> Just checked the datasheets again. This general phy type is used in some form
>> down to the S3C2443, so I'd prefer something with samsung in the name :-)
> Yes! That makes sense. I will change the name to samsung_usbphy
>
> Praveen
>>
>>
>> Heiko
>>
>>>
>>> Thank you,
>>> Kyungmin Park
>>>
>>> > Praveen
>>> >
>>> >>> Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>>> >>
>>> >> Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
>>> >>
>>> >>
>>> >> Heiko
>>> >>
>>> >>> ---
>>> >>>
>>> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>> >>>  drivers/usb/phy/Kconfig                            |    8 +
>>> >>>  drivers/usb/phy/Makefile                           |    1 +
>>> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
>>> >>>
>>> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>>> >>>
>>> >>>  48 +++
>>> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>> >>>  create mode 100644
>>> >>>
>>> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>>> >>> 100644 drivers/usb/phy/sec_usbphy.c
>>> >>>
>>> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>> >>>
>>> >>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
>>> >>> mode 100644
>>> >>> index 0000000..fefd9c8
>>> >>> --- /dev/null
>>> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> >>> @@ -0,0 +1,9 @@
>>> >>> +* Samsung's usb phy transceiver
>>> >>> +
>>> >>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>>> >>> +s3c-hsotg usb device controller.
>>> >>> +
>>> >>> +Required properties:
>>> >>> +- compatible : should be "samsung,exynos4210-usbphy"
>>> >>> +- reg : base physical address of the phy registers and length of
>>> >>> memory mapped +      region.
>>> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>>> >>> index e7cf84f..abbebe2 100644
>>> >>> --- a/drivers/usb/phy/Kconfig
>>> >>> +++ b/drivers/usb/phy/Kconfig
>>> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>> >>>
>>> >>>         To compile this driver as a module, choose M here: the
>>> >>>         module will be called isp1301.
>>> >>>
>>> >>> +
>>> >>> +config SEC_USBPHY
>>> >>> +       bool "Samsung USB PHY controller Driver"
>>> >>> +       depends on USB_S3C_HSOTG
>>> >>> +       select USB_OTG_UTILS
>>> >>> +       help
>>> >>> +         Enable this to support Samsung USB phy controller for samsung
>>> >>> +         SoCs.
>>> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>>> >>> index eca095b..6bb66f0 100644
>>> >>> --- a/drivers/usb/phy/Makefile
>>> >>> +++ b/drivers/usb/phy/Makefile
>>> >>> @@ -5,3 +5,4 @@
>>> >>>
>>> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>> >>>
>>> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>>> >>>
>>> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
>>> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
>>> >>> index 0000000..33119eb
>>> >>> --- /dev/null
>>> >>> +++ b/drivers/usb/phy/sec_usbphy.c
>>> >>> @@ -0,0 +1,354 @@
>>> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
>>> >>> + *
>>> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>>> >>> + *              http://www.samsung.com
>>> >>> + *
>>> >>> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>>> >>> + *
>>> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>>> >>> controller + *
>>> >>> + * This program is free software; you can redistribute it and/or
>>> >>> modify + * it under the terms of the GNU General Public License
>>> >>> version 2 as + * published by the Free Software Foundation.
>>> >>> + *
>>> >>> + * This program is distributed in the hope that it will be useful,
>>> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> >>> + * GNU General Public License for more details.
>>> >>> + *
>>> >>> + * You should have received a copy of the GNU General Public License
>>> >>> + * along with this program; if not, write to the Free Software
>>> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>>> >>> +*/
>>> >>> +
>>> >>> +#include <linux/module.h>
>>> >>> +#include <linux/platform_device.h>
>>> >>> +#include <linux/clk.h>
>>> >>> +#include <linux/delay.h>
>>> >>> +#include <linux/err.h>
>>> >>> +#include <linux/io.h>
>>> >>> +#include <linux/of.h>
>>> >>> +#include <linux/usb/otg.h>
>>> >>> +#include <linux/platform_data/s3c-hsotg.h>
>>> >>> +
>>> >>> +#include "sec_usbphy.h"
>>> >>> +
>>> >>> +enum sec_cpu_type {
>>> >>> +     TYPE_S3C64XX,
>>> >>> +     TYPE_EXYNOS4210,
>>> >>> +};
>>> >>> +
>>> >>> +/*
>>> >>> + * struct sec_usbphy - transceiver driver state
>>> >>> + * @phy: transceiver structure
>>> >>> + * @plat: platform data
>>> >>> + * @dev: The parent device supplied to the probe function
>>> >>> + * @clk: usb phy clock
>>> >>> + * @regs: usb phy register memory base
>>> >>> + * @cpu_type: machine identifier
>>> >>> + */
>>> >>> +struct sec_usbphy {
>>> >>> +     struct usb_phy  phy;
>>> >>> +     struct s3c_usbphy_plat *plat;
>>> >>> +     struct device   *dev;
>>> >>> +     struct clk      *clk;
>>> >>> +     void __iomem    *regs;
>>> >>> +     int             cpu_type;
>>> >>> +};
>>> >>> +
>>> >>> +#define phy_to_sec(x)                container_of((x), struct
>>> >>> sec_usbphy, phy)
>>> >>> +
>>> >>> +/*
>>> >>> + * Enables or disables the phy clock
>>> >>> + * returns 0 on success else the error
>>> >>> + */
>>> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>>> >>> +{
>>> >>> +     if (on) {
>>> >>> +             if (!sec->clk) {
>>> >>> +                     sec->clk = clk_get(sec->dev, "otg");
>>> >>> +                     if (IS_ERR(sec->clk)) {
>>> >>> +                             dev_err(sec->dev, "Failed to get otg
>>> >>> clock\n");
>>> >>> +                             return PTR_ERR(sec->clk);
>>> >>> +                     }
>>> >>> +             }
>>> >>> +             clk_enable(sec->clk);
>>> >>> +     } else {
>>> >>> +             clk_disable(sec->clk);
>>> >>> +             clk_put(sec->clk);
>>> >>> +     }
>>> >>> +
>>> >>> +     return 0;
>>> >>> +}
>>> >>> +
>>> >>> +/*
>>> >>> + * Returns reference clock frequency
>>> >>> + */
>>> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>>> >>> +{
>>> >>> +     struct clk *ref_clk;
>>> >>> +     int refclk_freq = 0;
>>> >>> +
>>> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>>> >>> +     if (IS_ERR(ref_clk)) {
>>> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>>> >>> +             return PTR_ERR(ref_clk);
>>> >>> +     }
>>> >>> +
>>> >>> +     switch (clk_get_rate(ref_clk)) {
>>> >>> +     case 12 * MHZ:
>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>>> >>> +             break;
>>> >>> +     case 24 * MHZ:
>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>>> >>> +             break;
>>> >>> +     default:
>>> >>> +     case 48 * MHZ:
>>> >>> +             /* default reference clock */
>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>>> >>> +             break;
>>> >>> +     }
>>> >>> +     clk_put(ref_clk);
>>> >>> +
>>> >>> +     return refclk_freq;
>>> >>> +}
>>> >>> +
>>> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>>> >>> +{
>>> >>> +     void __iomem *regs = sec->regs;
>>> >>> +     u32 phypwr;
>>> >>> +     u32 phyclk;
>>> >>> +     u32 rstcon;
>>> >>> +
>>> >>> +     /* set clock frequency for PLL */
>>> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> >>> +     rstcon = readl(regs + S3C_RSTCON);
>>> >>> +
>>> >>> +     switch (sec->cpu_type) {
>>> >>> +     case TYPE_S3C64XX:
>>> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>>> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>> >>> +             break;
>>> >>> +     case TYPE_EXYNOS4210:
>>> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>> >>> +     default:
>>> >>> +             break;
>>> >>> +     }
>>> >>> +
>>> >>> +     writel(phyclk, regs + S3C_PHYCLK);
>>> >>> +     /* set to normal of PHY0 */
>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> >>> +     /* reset all ports of PHY and Link */
>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>> >>> +     udelay(10);
>>> >>> +     rstcon &= ~S3C_RSTCON_PHY;
>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>> >>> +}
>>> >>> +
>>> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>>> >>> +{
>>> >>> +     void __iomem *regs = sec->regs;
>>> >>> +     u32 phypwr;
>>> >>> +
>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> >>> +
>>> >>> +     switch (sec->cpu_type) {
>>> >>> +     case TYPE_S3C64XX:
>>> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>>> >>> +             break;
>>> >>> +     case TYPE_EXYNOS4210:
>>> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>>> >>> +     default:
>>> >>> +             break;
>>> >>> +     }
>>> >>> +
>>> >>> +     /* unset to normal of PHY0 */
>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> >>> +}
>>> >>> +
>>> >>> +/*
>>> >>> + * The function passed to the usb driver for phy initialization
>>> >>> + */
>>> >>> +static int sec_usbphy_init(struct usb_phy *phy)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec;
>>> >>> +     int ret = 0;
>>> >>> +
>>> >>> +     sec = phy_to_sec(phy);
>>> >>> +
>>> >>> +     /* Enable the phy clock */
>>> >>> +     ret = sec_usbphy_clk_control(sec, true);
>>> >>> +     if (ret) {
>>> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
>>> >>> +             return ret;
>>> >>> +     }
>>> >>> +
>>> >>> +     /* Disable phy isolation */
>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> >>> +             sec->plat->pmu_isolation(false);
>>> >>> +
>>> >>> +     /* Initialize usb phy registers */
>>> >>> +     sec_usbphy_enable(sec);
>>> >>> +     return ret;
>>> >>> +}
>>> >>> +
>>> >>> +/*
>>> >>> + * The function passed to the usb driver for phy shutdown
>>> >>> + */
>>> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec;
>>> >>> +
>>> >>> +     sec = phy_to_sec(phy);
>>> >>> +
>>> >>> +     /* De-initialize usb phy registers */
>>> >>> +     sec_usbphy_disable(sec);
>>> >>> +
>>> >>> +     /* Enable phy isolation */
>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> >>> +             sec->plat->pmu_isolation(true);
>>> >>> +
>>> >>> +     /* Disable the phy clock */
>>> >>> +     sec_usbphy_clk_control(sec, false);
>>> >>> +}
>>> >>> +
>>> >>> +static const struct of_device_id sec_usbphy_dt_match[];
>>> >>> +
>>> >>> +static inline int sec_usbphy_get_driver_data(struct platform_device
>>> >>> *pdev)
>>> >>> +{
>>> >>> +#ifdef CONFIG_OF
>>> >>> +     int data;
>>> >>> +     if (pdev->dev.of_node) {
>>> >>> +             const struct of_device_id *match;
>>> >>> +             match = of_match_node(sec_usbphy_dt_match,
>>> >>> pdev->dev.of_node);
>>> >>> +             data = (int) match->data;
>>> >>> +             return data;
>>> >>> +     }
>>> >>> +#endif
>>> >>> +     return platform_get_device_id(pdev)->driver_data;
>>> >>> +}
>>> >>> +
>>> >>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec;
>>> >>> +     struct s3c_usbphy_plat *pdata;
>>> >>> +     struct device *dev = &pdev->dev;
>>> >>> +     struct resource *phy_mem;
>>> >>> +     void __iomem    *phy_base;
>>> >>> +     int     ret;
>>> >>> +
>>> >>> +     pdata = pdev->dev.platform_data;
>>> >>> +     if (!pdata) {
>>> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>>> >>> __func__);
>>> >>> +             return -EINVAL;
>>> >>> +     }
>>> >>> +
>>> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> >>> +     if (!phy_mem) {
>>> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>>> >>> +             return -ENODEV;
>>> >>> +     }
>>> >>> +
>>> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>>> >>> +     if (!phy_base) {
>>> >>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>>> >>> +             return -ENXIO;
>>> >>> +     }
>>> >>> +
>>> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>>> >>> +     if (!sec)
>>> >>> +             return -ENOMEM;
>>> >>> +
>>> >>> +     sec->dev                = &pdev->dev;
>>> >>> +     sec->plat               = pdata;
>>> >>> +     sec->regs               = phy_base;
>>> >>> +     sec->phy.dev            = sec->dev;
>>> >>> +     sec->phy.label          = "sec-usbphy";
>>> >>> +     sec->phy.init           = sec_usbphy_init;
>>> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>>> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>>> >>> +
>>> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>>> >>> +     if (ret)
>>> >>> +             goto err;
>>> >>> +
>>> >>> +     platform_set_drvdata(pdev, sec);
>>> >>> +
>>> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>>> >>> +err:
>>> >>> +     return ret;
>>> >>> +}
>>> >>> +
>>> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>>> >>> +
>>> >>> +     usb_remove_phy(&sec->phy);
>>> >>> +
>>> >>> +     if (sec->clk) {
>>> >>> +             clk_put(sec->clk);
>>> >>> +             sec->clk = NULL;
>>> >>> +     }
>>> >>> +
>>> >>> +     return 0;
>>> >>> +}
>>> >>> +
>>> >>> +#ifdef CONFIG_OF
>>> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>>> >>> +     {
>>> >>> +             .compatible = "samsung,s3c64xx-usbphy",
>>> >>> +             .data = (void *)TYPE_S3C64XX,
>>> >>> +     }, {
>>> >>> +             .compatible = "samsung,exynos4210-usbphy",
>>> >>> +             .data = (void *)TYPE_EXYNOS4210,
>>> >>> +     },
>>> >>> +     {},
>>> >>> +};
>>> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>>> >>> +#else
>>> >>> +#define sec_usbphy_dt_match NULL
>>> >>> +#endif
>>> >>> +
>>> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>>> >>> +     {
>>> >>> +             .name           = "s3c64xx-usbphy",
>>> >>> +             .driver_data    = TYPE_S3C64XX,
>>> >>> +     }, {
>>> >>> +             .name           = "exynos4210-usbphy",
>>> >>> +             .driver_data    = TYPE_EXYNOS4210,
>>> >>> +     },
>>> >>> +     {},
>>> >>> +};
>>> >>> +
>>> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>>> >>> +
>>> >>> +static struct platform_driver sec_usbphy_driver = {
>>> >>> +     .probe          = sec_usbphy_probe,
>>> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
>>> >>> +     .id_table       = sec_usbphy_driver_ids,
>>> >>> +     .driver         = {
>>> >>> +             .name   = "sec-usbphy",
>>> >>> +             .owner  = THIS_MODULE,
>>> >>> +             .of_match_table = sec_usbphy_dt_match,
>>> >>> +     },
>>> >>> +};
>>> >>> +
>>> >>> +static int __init sec_usbphy_driver_init(void)
>>> >>> +{
>>> >>> +     return platform_driver_register(&sec_usbphy_driver);
>>> >>> +}
>>> >>> +subsys_initcall(sec_usbphy_driver_init);
>>> >>> +
>>> >>> +static void __exit sec_usbphy_driver_exit(void)
>>> >>> +{
>>> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
>>> >>> +}
>>> >>> +module_exit(sec_usbphy_driver_exit);
>>> >>> +
>>> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>>> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
>>> >>> +MODULE_LICENSE("GPL");
>>> >>> +MODULE_ALIAS("platform:sec-usbphy");
>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
>>> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
>>> >>> index 0000000..06e81d4
>>> >>> --- /dev/null
>>> >>> +++ b/drivers/usb/phy/sec_usbphy.h
>>> >>> @@ -0,0 +1,48 @@
>>> >>> +/*
>>> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>>> >>> + * Author: Yulgon Kim <yulgon.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>>> >>> + * Author: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>>> >>> + * Author: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>>> >>> + *
>>> >>> + * This program is free software; you can redistribute  it and/or
>>> >>> modify
>>> >>> it + * under  the terms of  the GNU General  Public License as
>>> >>> published by the + * Free Software Foundation;  either version 2 of
>>> >>> the  License, or
>>> >>> (at your + * option) any later version.
>>> >>> + */
>>> >>> +
>>> >>> +#ifndef __SEC_USBPHY_H
>>> >>> +#define __SEC_USBPHY_H
>>> >>> +
>>> >>> +#define S3C_PHYPWR                           (0x00)
>>> >>> +
>>> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>>> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>>> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>>> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>>> >>> +/* For Exynos4 */
>>> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>>> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>>> >>> +
>>> >>> +#define S3C_PHYCLK                           (0x04)
>>> >>> +
>>> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>>> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>>> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>>> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>>> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>>> >>> +
>>> >>> +#define S3C_RSTCON                           (0x08)
>>> >>> +
>>> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>>> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>>> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
>>> >>> +
>>> >>> +#ifndef MHZ
>>> >>> +#define MHZ (1000*1000)
>>> >>> +#endif
>>> >>> +
>>> >>> +#endif /* __SEC_USBPHY_H */
>>> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>>> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>>> >>> --- a/include/linux/platform_data/s3c-hsotg.h
>>> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
>>> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>> >>>
>>> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>> >>>
>>> >>>  };
>>> >>>
>>> >>> +struct s3c_usbphy_plat {
>>> >>> +     void (*pmu_isolation)(int on);
>>> >>> +};
>>> >>> +
>>> >>>
>>> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>>> >>>
>>> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>> >>>
>>> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>>> >>
>>> >> --
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Re: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg

[Kyungmin Park]

On 8/7/12, Praveen Paneri <p.paneri@samsung.com> wrote:
> Hi,
>
> On Mon, Aug 6, 2012 at 3:21 PM, Praveen Paneri <p.paneri@samsung.com>
> wrote:
>> Hi,
>>
>> On Mon, Aug 6, 2012 at 2:53 PM, Heiko Stübner <heiko@sntech.de> wrote:
>>> Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
>>>> Hi Praveen,
>>>>
>>>> On 8/6/12, Praveen Paneri <p.paneri@samsung.com> wrote:
>>>> > Hi Heiko,
>>>> >
>>>> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko Stübner <heiko@sntech.de>
>>>> > wrote:
>>>> >> Hi Praveen,
>>>> >>
>>>> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>>>> >>> This driver uses usb_phy interface to interact with s3c-hsotg.
>>>> >>> Supports
>>>> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested
>>>> >>> with
>>>> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>>> >>
>>>> >> Looks cool.
>>>> >
>>>> > Thanks
>>>> >
>>>> >> From what I've seen the phy controllers on newer Samsung SoCs are
>>>> >> still
>>>> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully
>>>> >> at
>>>> >> some
>>>> >> point after the driver has settled, I'll find the time to add
>>>> >> support
>>>> >> for these to the phy driver.
>>>> >
>>>> > Yes! that's great.
>>>> >
>>>> >> Out of curiosity, what does the "sec" in sec_usbphy for?
>>>> >
>>>> > Its Samsung Electronics Co. :)
>>>>
>>>> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
>>>> 'sec' prefix for samsung drivers.
>>>
>>> I'd second that. All new generic samsung drivers look like this (i.e.
>>> gpio-
>>> samsung, pwm-samsung).
> On the second thought I am thinking 'sec' is shorter and cooler. I
> know that it has not
I also think about it. but most of people think 'sec' is "Securities
and Exchange Commission" or security instead of "Samsung Electronics".
Ans TLA is avoid if possible.

Thank you,
Kyungmin Park
> been used anywhere else but there is always a first time :-P The
> shorter string helps in
> writing the code; especially when we have 80 character restriction. If
> you go through
> this driver itself you will realize this. Also there was a suggestion
> some time back to
> use 'sec' instead of 'samsung'.
> This is just my view about it. Please comment.
>
> Praveen
>
>>>
>>> Just checked the datasheets again. This general phy type is used in some
>>> form
>>> down to the S3C2443, so I'd prefer something with samsung in the name
>>> :-)
>> Yes! That makes sense. I will change the name to samsung_usbphy
>>
>> Praveen
>>>
>>>
>>> Heiko
>>>
>>>>
>>>> Thank you,
>>>> Kyungmin Park
>>>>
>>>> > Praveen
>>>> >
>>>> >>> Signed-off-by: Praveen Paneri <p.paneri@samsung.com>
>>>> >>
>>>> >> Acked-by: Heiko Stuebner <heiko@sntech.de>
>>>> >>
>>>> >>
>>>> >> Heiko
>>>> >>
>>>> >>> ---
>>>> >>>
>>>> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>>> >>>  drivers/usb/phy/Kconfig                            |    8 +
>>>> >>>  drivers/usb/phy/Makefile                           |    1 +
>>>> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
>>>> >>>
>>>> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>>>> >>>
>>>> >>>  48 +++
>>>> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>>> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>>> >>>  create mode 100644
>>>> >>>
>>>> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create
>>>> >>> mode
>>>> >>> 100644 drivers/usb/phy/sec_usbphy.c
>>>> >>>
>>>> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>>> >>>
>>>> >>> diff --git
>>>> >>> a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>>> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
>>>> >>> mode 100644
>>>> >>> index 0000000..fefd9c8
>>>> >>> --- /dev/null
>>>> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>>> >>> @@ -0,0 +1,9 @@
>>>> >>> +* Samsung's usb phy transceiver
>>>> >>> +
>>>> >>> +The Samsung's phy transceiver is used for controlling usb otg phy
>>>> >>> for
>>>> >>> +s3c-hsotg usb device controller.
>>>> >>> +
>>>> >>> +Required properties:
>>>> >>> +- compatible : should be "samsung,exynos4210-usbphy"
>>>> >>> +- reg : base physical address of the phy registers and length of
>>>> >>> memory mapped +      region.
>>>> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>>>> >>> index e7cf84f..abbebe2 100644
>>>> >>> --- a/drivers/usb/phy/Kconfig
>>>> >>> +++ b/drivers/usb/phy/Kconfig
>>>> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>>> >>>
>>>> >>>         To compile this driver as a module, choose M here: the
>>>> >>>         module will be called isp1301.
>>>> >>>
>>>> >>> +
>>>> >>> +config SEC_USBPHY
>>>> >>> +       bool "Samsung USB PHY controller Driver"
>>>> >>> +       depends on USB_S3C_HSOTG
>>>> >>> +       select USB_OTG_UTILS
>>>> >>> +       help
>>>> >>> +         Enable this to support Samsung USB phy controller for
>>>> >>> samsung
>>>> >>> +         SoCs.
>>>> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>>>> >>> index eca095b..6bb66f0 100644
>>>> >>> --- a/drivers/usb/phy/Makefile
>>>> >>> +++ b/drivers/usb/phy/Makefile
>>>> >>> @@ -5,3 +5,4 @@
>>>> >>>
>>>> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>>> >>>
>>>> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>>>> >>>
>>>> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
>>>> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
>>>> >>> index 0000000..33119eb
>>>> >>> --- /dev/null
>>>> >>> +++ b/drivers/usb/phy/sec_usbphy.c
>>>> >>> @@ -0,0 +1,354 @@
>>>> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
>>>> >>> + *
>>>> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>>>> >>> + *              http://www.samsung.com
>>>> >>> + *
>>>> >>> + * Author: Praveen Paneri <p.paneri@samsung.com>
>>>> >>> + *
>>>> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>>>> >>> controller + *
>>>> >>> + * This program is free software; you can redistribute it and/or
>>>> >>> modify + * it under the terms of the GNU General Public License
>>>> >>> version 2 as + * published by the Free Software Foundation.
>>>> >>> + *
>>>> >>> + * This program is distributed in the hope that it will be useful,
>>>> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>> >>> + * GNU General Public License for more details.
>>>> >>> + *
>>>> >>> + * You should have received a copy of the GNU General Public
>>>> >>> License
>>>> >>> + * along with this program; if not, write to the Free Software
>>>> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>>>> >>> +*/
>>>> >>> +
>>>> >>> +#include <linux/module.h>
>>>> >>> +#include <linux/platform_device.h>
>>>> >>> +#include <linux/clk.h>
>>>> >>> +#include <linux/delay.h>
>>>> >>> +#include <linux/err.h>
>>>> >>> +#include <linux/io.h>
>>>> >>> +#include <linux/of.h>
>>>> >>> +#include <linux/usb/otg.h>
>>>> >>> +#include <linux/platform_data/s3c-hsotg.h>
>>>> >>> +
>>>> >>> +#include "sec_usbphy.h"
>>>> >>> +
>>>> >>> +enum sec_cpu_type {
>>>> >>> +     TYPE_S3C64XX,
>>>> >>> +     TYPE_EXYNOS4210,
>>>> >>> +};
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * struct sec_usbphy - transceiver driver state
>>>> >>> + * @phy: transceiver structure
>>>> >>> + * @plat: platform data
>>>> >>> + * @dev: The parent device supplied to the probe function
>>>> >>> + * @clk: usb phy clock
>>>> >>> + * @regs: usb phy register memory base
>>>> >>> + * @cpu_type: machine identifier
>>>> >>> + */
>>>> >>> +struct sec_usbphy {
>>>> >>> +     struct usb_phy  phy;
>>>> >>> +     struct s3c_usbphy_plat *plat;
>>>> >>> +     struct device   *dev;
>>>> >>> +     struct clk      *clk;
>>>> >>> +     void __iomem    *regs;
>>>> >>> +     int             cpu_type;
>>>> >>> +};
>>>> >>> +
>>>> >>> +#define phy_to_sec(x)                container_of((x), struct
>>>> >>> sec_usbphy, phy)
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * Enables or disables the phy clock
>>>> >>> + * returns 0 on success else the error
>>>> >>> + */
>>>> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>>>> >>> +{
>>>> >>> +     if (on) {
>>>> >>> +             if (!sec->clk) {
>>>> >>> +                     sec->clk = clk_get(sec->dev, "otg");
>>>> >>> +                     if (IS_ERR(sec->clk)) {
>>>> >>> +                             dev_err(sec->dev, "Failed to get otg
>>>> >>> clock\n");
>>>> >>> +                             return PTR_ERR(sec->clk);
>>>> >>> +                     }
>>>> >>> +             }
>>>> >>> +             clk_enable(sec->clk);
>>>> >>> +     } else {
>>>> >>> +             clk_disable(sec->clk);
>>>> >>> +             clk_put(sec->clk);
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     return 0;
>>>> >>> +}
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * Returns reference clock frequency
>>>> >>> + */
>>>> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>>>> >>> +{
>>>> >>> +     struct clk *ref_clk;
>>>> >>> +     int refclk_freq = 0;
>>>> >>> +
>>>> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>>>> >>> +     if (IS_ERR(ref_clk)) {
>>>> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>>>> >>> +             return PTR_ERR(ref_clk);
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     switch (clk_get_rate(ref_clk)) {
>>>> >>> +     case 12 * MHZ:
>>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>>>> >>> +             break;
>>>> >>> +     case 24 * MHZ:
>>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>>>> >>> +             break;
>>>> >>> +     default:
>>>> >>> +     case 48 * MHZ:
>>>> >>> +             /* default reference clock */
>>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>>>> >>> +             break;
>>>> >>> +     }
>>>> >>> +     clk_put(ref_clk);
>>>> >>> +
>>>> >>> +     return refclk_freq;
>>>> >>> +}
>>>> >>> +
>>>> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>>>> >>> +{
>>>> >>> +     void __iomem *regs = sec->regs;
>>>> >>> +     u32 phypwr;
>>>> >>> +     u32 phyclk;
>>>> >>> +     u32 rstcon;
>>>> >>> +
>>>> >>> +     /* set clock frequency for PLL */
>>>> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>>> >>> +     rstcon = readl(regs + S3C_RSTCON);
>>>> >>> +
>>>> >>> +     switch (sec->cpu_type) {
>>>> >>> +     case TYPE_S3C64XX:
>>>> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>>>> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>>> >>> +             break;
>>>> >>> +     case TYPE_EXYNOS4210:
>>>> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>>> >>> +     default:
>>>> >>> +             break;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     writel(phyclk, regs + S3C_PHYCLK);
>>>> >>> +     /* set to normal of PHY0 */
>>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>>> >>> +     /* reset all ports of PHY and Link */
>>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>>> >>> +     udelay(10);
>>>> >>> +     rstcon &= ~S3C_RSTCON_PHY;
>>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>>> >>> +}
>>>> >>> +
>>>> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>>>> >>> +{
>>>> >>> +     void __iomem *regs = sec->regs;
>>>> >>> +     u32 phypwr;
>>>> >>> +
>>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>>> >>> +
>>>> >>> +     switch (sec->cpu_type) {
>>>> >>> +     case TYPE_S3C64XX:
>>>> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>>>> >>> +             break;
>>>> >>> +     case TYPE_EXYNOS4210:
>>>> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>>>> >>> +     default:
>>>> >>> +             break;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     /* unset to normal of PHY0 */
>>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>>> >>> +}
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * The function passed to the usb driver for phy initialization
>>>> >>> + */
>>>> >>> +static int sec_usbphy_init(struct usb_phy *phy)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec;
>>>> >>> +     int ret = 0;
>>>> >>> +
>>>> >>> +     sec = phy_to_sec(phy);
>>>> >>> +
>>>> >>> +     /* Enable the phy clock */
>>>> >>> +     ret = sec_usbphy_clk_control(sec, true);
>>>> >>> +     if (ret) {
>>>> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
>>>> >>> +             return ret;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     /* Disable phy isolation */
>>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>>> >>> +             sec->plat->pmu_isolation(false);
>>>> >>> +
>>>> >>> +     /* Initialize usb phy registers */
>>>> >>> +     sec_usbphy_enable(sec);
>>>> >>> +     return ret;
>>>> >>> +}
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * The function passed to the usb driver for phy shutdown
>>>> >>> + */
>>>> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec;
>>>> >>> +
>>>> >>> +     sec = phy_to_sec(phy);
>>>> >>> +
>>>> >>> +     /* De-initialize usb phy registers */
>>>> >>> +     sec_usbphy_disable(sec);
>>>> >>> +
>>>> >>> +     /* Enable phy isolation */
>>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>>> >>> +             sec->plat->pmu_isolation(true);
>>>> >>> +
>>>> >>> +     /* Disable the phy clock */
>>>> >>> +     sec_usbphy_clk_control(sec, false);
>>>> >>> +}
>>>> >>> +
>>>> >>> +static const struct of_device_id sec_usbphy_dt_match[];
>>>> >>> +
>>>> >>> +static inline int sec_usbphy_get_driver_data(struct
>>>> >>> platform_device
>>>> >>> *pdev)
>>>> >>> +{
>>>> >>> +#ifdef CONFIG_OF
>>>> >>> +     int data;
>>>> >>> +     if (pdev->dev.of_node) {
>>>> >>> +             const struct of_device_id *match;
>>>> >>> +             match = of_match_node(sec_usbphy_dt_match,
>>>> >>> pdev->dev.of_node);
>>>> >>> +             data = (int) match->data;
>>>> >>> +             return data;
>>>> >>> +     }
>>>> >>> +#endif
>>>> >>> +     return platform_get_device_id(pdev)->driver_data;
>>>> >>> +}
>>>> >>> +
>>>> >>> +static int __devinit sec_usbphy_probe(struct platform_device
>>>> >>> *pdev)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec;
>>>> >>> +     struct s3c_usbphy_plat *pdata;
>>>> >>> +     struct device *dev = &pdev->dev;
>>>> >>> +     struct resource *phy_mem;
>>>> >>> +     void __iomem    *phy_base;
>>>> >>> +     int     ret;
>>>> >>> +
>>>> >>> +     pdata = pdev->dev.platform_data;
>>>> >>> +     if (!pdata) {
>>>> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>>>> >>> __func__);
>>>> >>> +             return -EINVAL;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>> >>> +     if (!phy_mem) {
>>>> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>>>> >>> +             return -ENODEV;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>>>> >>> +     if (!phy_base) {
>>>> >>> +             dev_err(dev, "%s: register mapping failed\n",
>>>> >>> __func__);
>>>> >>> +             return -ENXIO;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>>>> >>> +     if (!sec)
>>>> >>> +             return -ENOMEM;
>>>> >>> +
>>>> >>> +     sec->dev                = &pdev->dev;
>>>> >>> +     sec->plat               = pdata;
>>>> >>> +     sec->regs               = phy_base;
>>>> >>> +     sec->phy.dev            = sec->dev;
>>>> >>> +     sec->phy.label          = "sec-usbphy";
>>>> >>> +     sec->phy.init           = sec_usbphy_init;
>>>> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>>>> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>>>> >>> +
>>>> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>>>> >>> +     if (ret)
>>>> >>> +             goto err;
>>>> >>> +
>>>> >>> +     platform_set_drvdata(pdev, sec);
>>>> >>> +
>>>> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY
>>>> >>> module\n");
>>>> >>> +err:
>>>> >>> +     return ret;
>>>> >>> +}
>>>> >>> +
>>>> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>>>> >>> +
>>>> >>> +     usb_remove_phy(&sec->phy);
>>>> >>> +
>>>> >>> +     if (sec->clk) {
>>>> >>> +             clk_put(sec->clk);
>>>> >>> +             sec->clk = NULL;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     return 0;
>>>> >>> +}
>>>> >>> +
>>>> >>> +#ifdef CONFIG_OF
>>>> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>>>> >>> +     {
>>>> >>> +             .compatible = "samsung,s3c64xx-usbphy",
>>>> >>> +             .data = (void *)TYPE_S3C64XX,
>>>> >>> +     }, {
>>>> >>> +             .compatible = "samsung,exynos4210-usbphy",
>>>> >>> +             .data = (void *)TYPE_EXYNOS4210,
>>>> >>> +     },
>>>> >>> +     {},
>>>> >>> +};
>>>> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>>>> >>> +#else
>>>> >>> +#define sec_usbphy_dt_match NULL
>>>> >>> +#endif
>>>> >>> +
>>>> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>>>> >>> +     {
>>>> >>> +             .name           = "s3c64xx-usbphy",
>>>> >>> +             .driver_data    = TYPE_S3C64XX,
>>>> >>> +     }, {
>>>> >>> +             .name           = "exynos4210-usbphy",
>>>> >>> +             .driver_data    = TYPE_EXYNOS4210,
>>>> >>> +     },
>>>> >>> +     {},
>>>> >>> +};
>>>> >>> +
>>>> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>>>> >>> +
>>>> >>> +static struct platform_driver sec_usbphy_driver = {
>>>> >>> +     .probe          = sec_usbphy_probe,
>>>> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
>>>> >>> +     .id_table       = sec_usbphy_driver_ids,
>>>> >>> +     .driver         = {
>>>> >>> +             .name   = "sec-usbphy",
>>>> >>> +             .owner  = THIS_MODULE,
>>>> >>> +             .of_match_table = sec_usbphy_dt_match,
>>>> >>> +     },
>>>> >>> +};
>>>> >>> +
>>>> >>> +static int __init sec_usbphy_driver_init(void)
>>>> >>> +{
>>>> >>> +     return platform_driver_register(&sec_usbphy_driver);
>>>> >>> +}
>>>> >>> +subsys_initcall(sec_usbphy_driver_init);
>>>> >>> +
>>>> >>> +static void __exit sec_usbphy_driver_exit(void)
>>>> >>> +{
>>>> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
>>>> >>> +}
>>>> >>> +module_exit(sec_usbphy_driver_exit);
>>>> >>> +
>>>> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>>>> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
>>>> >>> +MODULE_LICENSE("GPL");
>>>> >>> +MODULE_ALIAS("platform:sec-usbphy");
>>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
>>>> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
>>>> >>> index 0000000..06e81d4
>>>> >>> --- /dev/null
>>>> >>> +++ b/drivers/usb/phy/sec_usbphy.h
>>>> >>> @@ -0,0 +1,48 @@
>>>> >>> +/*
>>>> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>>>> >>> + * Author: Yulgon Kim <yulgon.kim@samsung.com>
>>>> >>> + * Author: Joonyoung Shim <jy0922.shim@samsung.com>
>>>> >>> + * Author: Praveen Paneri <p.paneri@samsung.com>
>>>> >>> + *
>>>> >>> + * This program is free software; you can redistribute  it and/or
>>>> >>> modify
>>>> >>> it + * under  the terms of  the GNU General  Public License as
>>>> >>> published by the + * Free Software Foundation;  either version 2 of
>>>> >>> the  License, or
>>>> >>> (at your + * option) any later version.
>>>> >>> + */
>>>> >>> +
>>>> >>> +#ifndef __SEC_USBPHY_H
>>>> >>> +#define __SEC_USBPHY_H
>>>> >>> +
>>>> >>> +#define S3C_PHYPWR                           (0x00)
>>>> >>> +
>>>> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>>>> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>>>> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>>>> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>>>> >>> +/* For Exynos4 */
>>>> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>>>> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>>>> >>> +
>>>> >>> +#define S3C_PHYCLK                           (0x04)
>>>> >>> +
>>>> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>>>> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>>>> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>>>> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>>>> >>> +
>>>> >>> +#define S3C_RSTCON                           (0x08)
>>>> >>> +
>>>> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>>>> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>>>> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
>>>> >>> +
>>>> >>> +#ifndef MHZ
>>>> >>> +#define MHZ (1000*1000)
>>>> >>> +#endif
>>>> >>> +
>>>> >>> +#endif /* __SEC_USBPHY_H */
>>>> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>>>> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e
>>>> >>> 100644
>>>> >>> --- a/include/linux/platform_data/s3c-hsotg.h
>>>> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
>>>> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>>> >>>
>>>> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>>> >>>
>>>> >>>  };
>>>> >>>
>>>> >>> +struct s3c_usbphy_plat {
>>>> >>> +     void (*pmu_isolation)(int on);
>>>> >>> +};
>>>> >>> +
>>>> >>>
>>>> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>>>> >>>
>>>> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>>> >>>
>>>> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>>>> >>
>>>> >> --
>>>> >> To unsubscribe from this list: send the line "unsubscribe linux-usb"
>>>> >> in
>>>> >> the body of a message to majordomo@vger.kernel.org
>>>> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>> >
>>>> > --
>>>> > To unsubscribe from this list: send the line "unsubscribe
>>>> > linux-samsung-soc" in
>>>> > the body of a message to majordomo@vger.kernel.org
>>>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe
>>> linux-samsung-soc" in
>>> the body of a message to majordomo@vger.kernel.org
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> --
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>

[PATCH 2/5] usb: s3c-hsotg: Adding phy driver support

[Praveen Paneri]

Adding the transceiver to hsotg driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it

Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/usb/gadget/s3c-hsotg.c |   38 ++++++++++++++++++++++++++++----------
 1 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index b13e0bb..f4ba9a3 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -32,6 +32,7 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
 #include <mach/map.h>
@@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
  * struct s3c_hsotg - driver state.
  * @dev: The parent device supplied to the probe function
  * @driver: USB gadget driver
- * @plat: The platform specific configuration data.
+ * @phy: The otg phy transeiver structure for phy control.
+ * @plat: The platform specific configuration data. This can be removed once
+ * all SoCs support usb transceiver.
  * @regs: The memory area mapped for accessing registers.
  * @irq: The IRQ number we are using
  * @supplies: Definition of USB power supplies
@@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
 struct s3c_hsotg {
 	struct device		 *dev;
 	struct usb_gadget_driver *driver;
+	struct usb_phy		*phy;
 	struct s3c_hsotg_plat	 *plat;
 
 	spinlock_t              lock;
@@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
 	dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
-	if (hsotg->plat->phy_init)
+
+	if (hsotg->phy)
+		usb_phy_init(hsotg->phy);
+	else if (hsotg->plat->phy_init)
 		hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 }
 
@@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
 {
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
-	if (hsotg->plat->phy_exit)
+	if (hsotg->phy)
+		usb_phy_shutdown(hsotg->phy);
+	else if (hsotg->plat->phy_exit)
 		hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 }
 
@@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 {
 	struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+	struct usb_phy *phy;
 	struct device *dev = &pdev->dev;
 	struct s3c_hsotg_ep *eps;
 	struct s3c_hsotg *hsotg;
@@ -3501,20 +3511,25 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 	int ret;
 	int i;
 
-	plat = pdev->dev.platform_data;
-	if (!plat) {
-		dev_err(&pdev->dev, "no platform data defined\n");
-		return -EINVAL;
-	}
-
 	hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
 	if (!hsotg) {
 		dev_err(dev, "cannot get memory\n");
 		return -ENOMEM;
 	}
 
+	phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+	if (!phy) {
+		/* Fallback for platform data */
+		plat = pdev->dev.platform_data;
+		if (!plat) {
+			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
+			return -ENODEV;
+		} else
+			hsotg->plat = plat;
+	} else
+		hsotg->phy = phy;
+
 	hsotg->dev = dev;
-	hsotg->plat = plat;
 
 	hsotg->clk = clk_get(&pdev->dev, "otg");
 	if (IS_ERR(hsotg->clk)) {
@@ -3689,6 +3704,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
 	s3c_hsotg_phy_disable(hsotg);
 	regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
 
+	if (hsotg->phy)
+		devm_usb_put_phy(&pdev->dev, hsotg->phy);
+
 	clk_disable_unprepare(hsotg->clk);
 	clk_put(hsotg->clk);
 
-- 
1.7.1

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[PATCH 3/5] ARM: S3C64XX: Removing old phy setup code

[Praveen Paneri]

This patch removes old phy code from platform side. 'setup-usb-phy.c'
will be used for providing transceiver platform data in next
patch. Not all of the platform data code is removed as there are others
making use of platform_data defined for hsotg. That can be removed once
all the SoCs start using the new transceiver for usb phy setup.

Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/mach-s3c64xx/mach-crag6410.c |    2 -
 arch/arm/mach-s3c64xx/mach-smartq.c   |    2 -
 arch/arm/mach-s3c64xx/mach-smdk6410.c |    2 -
 arch/arm/mach-s3c64xx/setup-usb-phy.c |   79 ---------------------------------
 4 files changed, 0 insertions(+), 85 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d0c352d..984146e 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -767,7 +767,6 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
-static struct s3c_hsotg_plat crag6410_hsotg_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -793,7 +792,6 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ceeb1de..3647202 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -187,7 +187,6 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
 	},
 };
 
-static struct s3c_hsotg_plat smartq_hsotg_pdata;
 
 static int __init smartq_lcd_setup_gpio(void)
 {
@@ -385,7 +384,6 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
-	s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index df3103d..ceec1a9 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -628,7 +628,6 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
-static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -658,7 +657,6 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e0..7a09553 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,82 +9,3 @@
  *
  */
 
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/map.h>
-#include <mach/regs-sys.h>
-#include <plat/cpu.h>
-#include <plat/regs-usb-hsotg-phy.h>
-#include <plat/usb-phy.h>
-
-static int s3c_usb_otgphy_init(struct platform_device *pdev)
-{
-	struct clk *xusbxti;
-	u32 phyclk;
-
-	writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	/* set clock frequency for PLL */
-	phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
-
-	xusbxti = clk_get(&pdev->dev, "xusbxti");
-	if (xusbxti && !IS_ERR(xusbxti)) {
-		switch (clk_get_rate(xusbxti)) {
-		case 12 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_12M;
-			break;
-		case 24 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_24M;
-			break;
-		default:
-		case 48 * MHZ:
-			/* default reference clock */
-			break;
-		}
-		clk_put(xusbxti);
-	}
-
-	/* TODO: select external clock/oscillator */
-	writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
-
-	/* set to normal OTG PHY */
-	writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
-	mdelay(1);
-
-	/* reset OTG PHY and Link */
-	writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
-			S3C_RSTCON);
-	udelay(20);	/* at-least 10uS */
-	writel(0, S3C_RSTCON);
-
-	return 0;
-}
-
-static int s3c_usb_otgphy_exit(struct platform_device *pdev)
-{
-	writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
-				S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
-
-	writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_init(pdev);
-
-	return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_exit(pdev);

[PATCH 4/5] ARM: S3C64XX: Enabling sec_usbphy driver

[Praveen Paneri]

Adding platform device for sec_usbphy driver. Enabling it for s3c64xx
based machines using s3c-hsotg.

Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/mach-s3c64xx/include/mach/map.h     |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c        |    3 ++
 arch/arm/mach-s3c64xx/mach-smartq.c          |    4 +++
 arch/arm/mach-s3c64xx/mach-smdk6410.c        |    3 ++
 arch/arm/mach-s3c64xx/setup-usb-phy.c        |   14 +++++++++++
 arch/arm/plat-samsung/devs.c                 |   32 ++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h    |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h |    1 +
 8 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097b..dc482bb 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -65,6 +65,7 @@
 
 #define S3C64XX_PA_NAND		(0x70200000)
 #define S3C64XX_PA_FB		(0x77100000)
+#define S3C64XX_PA_USB_HSPHY	(0x7C100000)
 #define S3C64XX_PA_USB_HSOTG	(0x7C000000)
 #define S3C64XX_PA_WATCHDOG	(0x7E004000)
 #define S3C64XX_PA_RTC		(0x7E005000)
@@ -113,6 +114,7 @@
 #define S3C_PA_FB		S3C64XX_PA_FB
 #define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG	S3C64XX_PA_USB_HSOTG
+#define S3C_PA_USB_PHY		S3C64XX_PA_USB_HSPHY
 #define S3C_PA_RTC		S3C64XX_PA_RTC
 #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
 #define S3C_PA_SPI0		S3C64XX_PA_SPI0
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 984146e..88c4671 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -337,6 +337,7 @@ static struct platform_device wallvdd_device = {
 };
 
 static struct platform_device *crag6410_devices[] __initdata = {
+	&s3c_device_usbphy,
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc2,
 	&s3c_device_i2c0,
@@ -767,6 +768,7 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
+static struct s3c_usbphy_plat crag6410_usbphy_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -792,6 +794,7 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
+	s3c_usbphy_set_platdata(&crag6410_usbphy_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 3647202..97751d5 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -235,6 +235,7 @@ static struct i2c_board_info smartq_i2c_devs[] __initdata = {
 };
 
 static struct platform_device *smartq_devices[] __initdata = {
+	&s3c_device_usbphy,
 	&s3c_device_hsmmc1,	/* Init iNAND first, ... */
 	&s3c_device_hsmmc0,	/* ... then the external SD card */
 	&s3c_device_hsmmc2,
@@ -381,9 +382,12 @@ void __init smartq_map_io(void)
 	smartq_lcd_mode_set();
 }
 
+static struct s3c_usbphy_plat smartq_usbphy_pdata;
+
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
+	s3c_usbphy_set_platdata(&smartq_usbphy_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ceec1a9..c5ea838 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -264,6 +264,7 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
+	&s3c_device_usbphy,
 #ifdef CONFIG_SMDK6410_SD_CH0
 	&s3c_device_hsmmc0,
 #endif
@@ -628,6 +629,7 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
+static struct s3c_usbphy_plat smdk6410_usbphy_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -657,6 +659,7 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+	s3c_usbphy_set_platdata(&smdk6410_usbphy_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index 7a09553..3aee778 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,3 +9,17 @@
  *
  */
 
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	} else {
+		writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	}
+}
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 6303974..77a35f1 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1343,6 +1343,35 @@ struct platform_device s5p_device_mixer = {
 
 /* USB */
 
+#ifdef CONFIG_S3C_DEV_USB_HSOTG
+/* USB PHY*/
+static struct resource s3c_usbphy_resource[] = {
+	[0] = {
+		.start = S3C_PA_USB_PHY,
+		.end   = S3C_PA_USB_PHY + SZ_16 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device s3c_device_usbphy = {
+	.name		= "s3c64xx-usbphy",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(s3c_usbphy_resource),
+	.resource	= s3c_usbphy_resource,
+};
+
+void __init s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd)
+{
+	struct s3c_usbphy_plat *npd;
+
+	npd = s3c_set_platdata(pd, sizeof(struct s3c_usbphy_plat),
+			&s3c_device_usbphy);
+
+	if (!npd->pmu_isolation)
+		npd->pmu_isolation = s5p_usb_phy_pmu_isolation;
+}
+#endif
+
 #ifdef CONFIG_S3C_DEV_USB_HOST
 static struct resource s3c_usb_resource[] = {
 	[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
@@ -1449,6 +1478,8 @@ struct platform_device s3c_device_usb_hsotg = {
 	},
 };
 
+#ifndef CONFIG_ARCH_S3C64XX
+/* TODO: To be removed later. Currently only S3C64XX is platform data free */
 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 {
 	struct s3c_hsotg_plat *npd;
@@ -1461,6 +1492,7 @@ void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 	if (!npd->phy_exit)
 		npd->phy_exit = s5p_usb_phy_exit;
 }
+#endif
 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
 
 /* USB High Spped 2.0 Device (Gadget) */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 61ca2f3..cbb079a 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -71,6 +71,7 @@ extern struct platform_device s3c_device_spi1;
 extern struct platform_device s3c_device_ts;
 extern struct platform_device s3c_device_timer[];
 extern struct platform_device s3c_device_usbgadget;
+extern struct platform_device s3c_device_usbphy;
 extern struct platform_device s3c_device_usb_hsotg;
 extern struct platform_device s3c_device_usb_hsudc;
 extern struct platform_device s3c_device_wdt;
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb..165ffe7 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -18,5 +18,6 @@ enum s5p_usb_phy_type {
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+extern void s5p_usb_phy_pmu_isolation(int on);
 
 #endif /* __PLAT_SAMSUNG_USB_PHY_H */
-- 
1.7.1

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[PATCH 5/5] ARM: Exynos4210: Enabling sec_usbphy driver

[Praveen Paneri]

Adding usbphy node for Exynos4210 along with the platform data.

Signed-off-by: Praveen Paneri <p.paneri-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/exynos4210.dtsi       |    5 +++++
 arch/arm/mach-exynos/include/mach/map.h |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c  |    8 ++++++++
 arch/arm/mach-exynos/setup-usb-phy.c    |   13 +++++++++++++
 4 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index a1dd2ee..fc9e00f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -45,6 +45,11 @@
 		interrupts = <0 44 0>, <0 45 0>;
 	};
 
+	usbphy@125B0000 {
+		compatible = "samsung,exynos4210-usbphy";
+		reg = <0x125B0000 0x100>;
+	};
+
 	keypad@100A0000 {
 		compatible = "samsung,s5pv210-keypad";
 		reg = <0x100A0000 0x100>;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index ca4aa89..a265634 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -231,6 +231,7 @@
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
 #define S3C_PA_USB_HSOTG		EXYNOS4_PA_HSOTG
+#define S3C_PA_USB_PHY			EXYNOS4_PA_HSPHY
 
 #define S5P_PA_EHCI			EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0			EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e7e9743..9126637 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -20,9 +21,14 @@
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
 
 #include "common.h"
 
+static struct s3c_usbphy_plat exynos4_usbphy_pdata = {
+	.pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable
@@ -57,6 +63,8 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
 				"s3c2440-i2c.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-usbphy", EXYNOS4_PA_HSPHY,
+			"s3c-usbphy", &exynos4_usbphy_pdata),
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 1af0a7f..3fca203 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -193,3 +193,16 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 
 	return -EINVAL;
 }
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			& ~S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	} else {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			| S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	}
+}
-- 
1.7.1

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Re: [PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for samsung SoCs

[Arnd Bergmann]

On Wednesday 01 August 2012, Praveen Paneri wrote:
> This patch set introduces a phy driver for samsung SoCs. It uses the existing
> transceiver infrastructure to provide phy control functions. Use of this driver
> can be extended for usb host phy as well. Over the period of time all the phy
> related code for most of the samsung SoCs can be integrated here.
> Removing the existing phy code from mach-s3c64xx but not from other machine 
> code.This driver is tested with smdk6410 and Exynos4210(with DT).

This looks very nice overall, great work!

We will still have to take care of the pmu isolation callback in the
long run, when we get to the point of removing all auxdata. Do you
have a plan on how to do that? If yes, it would be good to mention
that in the changelog.

My guess is that the PMU code should be moved into a higher-level
abstraction. I don't know if you would use one of those we already
have or whether you'd introduce a new subsystem for those. Apparently
other platforms have similar issues, so I'd suggest you leave the
callback for now, but we should at some point discuss what to to
about it.

	Arnd

Re: [PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for samsung SoCs

[Praveen Paneri]

Hi Arnd,

On Wed, Aug 1, 2012 at 8:50 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Wednesday 01 August 2012, Praveen Paneri wrote:
>> This patch set introduces a phy driver for samsung SoCs. It uses the existing
>> transceiver infrastructure to provide phy control functions. Use of this driver
>> can be extended for usb host phy as well. Over the period of time all the phy
>> related code for most of the samsung SoCs can be integrated here.
>> Removing the existing phy code from mach-s3c64xx but not from other machine
>> code.This driver is tested with smdk6410 and Exynos4210(with DT).
>
> This looks very nice overall, great work!
Thank you!
>
> We will still have to take care of the pmu isolation callback in the
> long run, when we get to the point of removing all auxdata. Do you
> have a plan on how to do that? If yes, it would be good to mention
> that in the changelog.
Yes! I understand this problem and this is the reason these patches
were sitting in my system for couple of weeks. In a  discussion with
Thomas an idea of using the existing regulator framework to
enable/disable numerous PHYs came up. For example the PMU unit
of Exynos4210 has a register set dedicated just to control USBD_PHY,
HDMI_PHY, MIPI_PHY, DAC_PHY and more. If a regulator with
each phy control register as LDO is written, the phy driver becomes a
static consumer and will modify as below.

diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
index 33119eb..4f69675 100644
--- a/drivers/usb/phy/sec_usbphy.c
+++ b/drivers/usb/phy/sec_usbphy.c
@@ -28,8 +28,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/regulator/consumer.h>
 #include <linux/usb/otg.h>
-#include <linux/platform_data/s3c-hsotg.h>

 #include "sec_usbphy.h"

@@ -41,7 +41,7 @@ enum sec_cpu_type {
 /*
  * struct sec_usbphy - transceiver driver state
  * @phy: transceiver structure
- * @plat: platform data
+ * @vusbphy: PMU regulator for usb phy
  * @dev: The parent device supplied to the probe function
  * @clk: usb phy clock
  * @regs: usb phy register memory base
@@ -49,7 +49,7 @@ enum sec_cpu_type {
  */
 struct sec_usbphy {
 	struct usb_phy	phy;
-	struct s3c_usbphy_plat *plat;
+	struct regulator *vusbphy;
 	struct device	*dev;
 	struct clk	*clk;
 	void __iomem	*regs;
@@ -187,8 +187,11 @@ static int sec_usbphy_init(struct usb_phy *phy)
 	}

 	/* Disable phy isolation */
-	if (sec->plat && sec->plat->pmu_isolation)
-		sec->plat->pmu_isolation(false);
+	ret = regulator_enable(sec->vusbphy);
+	if (ret) {
+		dev_err(sec->dev, "Failed to enable regulator for USBPHY\n");
+		return ret;
+	}

 	/* Initialize usb phy registers */
 	sec_usbphy_enable(sec);
@@ -208,8 +211,8 @@ static void sec_usbphy_shutdown(struct usb_phy *phy)
 	sec_usbphy_disable(sec);

 	/* Enable phy isolation */
-	if (sec->plat && sec->plat->pmu_isolation)
-		sec->plat->pmu_isolation(true);
+	if (regulator_disable(sec->vusbphy))
+		dev_err(sec->dev, "Failed to disable regulator for USBPHY\n");

 	/* Disable the phy clock */
 	sec_usbphy_clk_control(sec, false);
@@ -263,7 +266,6 @@ static int __devinit sec_usbphy_probe(struct
platform_device *pdev)
 		return -ENOMEM;

 	sec->dev		= &pdev->dev;
-	sec->plat		= pdata;
 	sec->regs		= phy_base;
 	sec->phy.dev		= sec->dev;
 	sec->phy.label		= "sec-usbphy";
@@ -271,6 +273,14 @@ static int __devinit sec_usbphy_probe(struct
platform_device *pdev)
 	sec->phy.shutdown	= sec_usbphy_shutdown;
 	sec->cpu_type		= sec_usbphy_get_driver_data(pdev);

+	/* acquire regulator */
+	sec->vusbphy = regulator_get(sec->dev, "usbdphy");
+	if (IS_ERR_OR_NULL(sec->vusbphy)) {
+		dev_err(dev, "failed to get regulator 'usbdphy'\n");
+		ret = -ENXIO;
+		goto err;
+	}
+
 	ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
 	if (ret)
 		goto err;
@@ -292,6 +302,7 @@ static int __exit sec_usbphy_remove(struct
platform_device *pdev)
 		clk_put(sec->clk);
 		sec->clk = NULL;
 	}
+	regulator_put(sec->vusbphy);

 	return 0;
 }

This kind of regulator, if generalised can be useful.
Please comment.
>
> My guess is that the PMU code should be moved into a higher-level
> abstraction. I don't know if you would use one of those we already
Could you please point out the location of the code.
> have or whether you'd introduce a new subsystem for those. Apparently.
Havent thought about it. Trying to work it out with the existing infra of the
kernel.
> other platforms have similar issues, so I'd suggest you leave the
> callback for now, but we should at some point discuss what to to
> about it.
>
>         Arnd
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Praveen

Re: [PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for samsung SoCs

[Arnd Bergmann]

On Thursday 02 August 2012, Praveen Paneri wrote:
> Yes! I understand this problem and this is the reason these patches
> were sitting in my system for couple of weeks. In a  discussion with
> Thomas an idea of using the existing regulator framework to
> enable/disable numerous PHYs came up. For example the PMU unit
> of Exynos4210 has a register set dedicated just to control USBD_PHY,
> HDMI_PHY, MIPI_PHY, DAC_PHY and more. If a regulator with
> each phy control register as LDO is written, the phy driver becomes a
> static consumer and will modify as below.

This is roughly what I had in mind, yes. The part I'm not sure about
is the subsystem to use. One could obviously express the same logic
using the clock or gpio framework, which would work but be conceptually
wrong.

Some other parts of the PMU functionality are provided through
pm-domains rather than regulators and I guess in theory it could
all be controlled through pm-domains. Maybe someone else has a better
understanding than me what the tradeoffs are here and which subsystem
should be used for the PMU.

	Arnd