[PATCH V2 0/3] Add clock framework for armada 370/XP

[PATCH V2 0/3] Add clock framework for armada 370/XP

[Gregory CLEMENT]

Hello Mike,

My first version didn't get many attention, so I guess it's too late
for 3.7! ;) I should have ping you earlier about this series. This
time was not lost, by using the cpu clock with SMP I found a bug and
fixed it. And I also improved the spelling and removed unnecessary
small piece of code thanks to the feed back of Andrew Lunn.

The purpose of this patch set is to add support for clock framework
for Armada 370 and Armada XP SoCs. All the support is done under the
directory drivers/clk/mvebu/ as the support for other mvebu SoCs was
in mind during the writing of the code.

Two kinds of clocks are added:

- The CPU clocks are only for Armada XP (which si multi-core)

- The core clocks are clocks which have their rate fixed during
  reset.

This patch set is based on the clk-3.7 branch of Mike Turquette as it
use the patch "clk: add of_clk_src_onecell_get() support" from Shawn
Guo.

Many thanks to Thomas Petazzoni and Sebastian Hesselbarth for their
review and feedback. The device tree bindings were really improved
with the advices of Sebastian.

Changelog:
V1 -> V2:

- Improved the spelling and the wording of the documentation and the
  1st commit log
- Removed the "end_of_list" name which are unused here.
- Fix the cpu clock by using of_clk_src_onecell_get in the same way it
  was used for the core clocks

Regards,

Gregory CLEMENT (3):
  clk: mvebu: add armada-370-xp specific clocks
  clk: armada-370-xp: add support for clock framework
  clocksource: time-armada-370-xp converted to clk framework

 .../devicetree/bindings/clock/mvebu-core-clock.txt |   40 +++
 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   21 ++
 arch/arm/boot/dts/armada-370-db.dts                |    4 -
 arch/arm/boot/dts/armada-370-xp.dtsi               |    1 +
 arch/arm/boot/dts/armada-370.dtsi                  |   12 +
 arch/arm/boot/dts/armada-xp.dtsi                   |   48 +++
 arch/arm/mach-mvebu/Kconfig                        |    5 +
 arch/arm/mach-mvebu/armada-370-xp.c                |    8 +-
 arch/arm/mach-mvebu/common.h                       |    1 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/mvebu/Makefile                         |    2 +
 drivers/clk/mvebu/clk-core.c                       |  312 ++++++++++++++++++++
 drivers/clk/mvebu/clk-core.h                       |   19 ++
 drivers/clk/mvebu/clk-cpu.c                        |  155 ++++++++++
 drivers/clk/mvebu/clk-cpu.h                        |   19 ++
 drivers/clk/mvebu/clk.c                            |   36 +++
 drivers/clocksource/time-armada-370-xp.c           |   11 +-
 17 files changed, 685 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
 create mode 100644 drivers/clk/mvebu/Makefile
 create mode 100644 drivers/clk/mvebu/clk-core.c
 create mode 100644 drivers/clk/mvebu/clk-core.h
 create mode 100644 drivers/clk/mvebu/clk-cpu.c
 create mode 100644 drivers/clk/mvebu/clk-cpu.h
 create mode 100644 drivers/clk/mvebu/clk.c

-- 
1.7.9.5

[PATCH V2 1/3] clk: mvebu: add armada-370-xp specific clocks

[Gregory CLEMENT]

Add Armada 370/XP specific clocks: core clocks and CPU clocks.

The CPU clocks are only for Armada XP for the SMP mode.

The core clocks are clocks which have their rate set during reset. The
code was written with the other SoCs of the mvebu family in
mind. Adding them should be pretty straight forward. For a new
SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children
  clocks

Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   40 +++
 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   21 ++
 drivers/clk/Makefile                               |    1 +
 drivers/clk/mvebu/Makefile                         |    2 +
 drivers/clk/mvebu/clk-core.c                       |  312 ++++++++++++++++++++
 drivers/clk/mvebu/clk-core.h                       |   19 ++
 drivers/clk/mvebu/clk-cpu.c                        |  155 ++++++++++
 drivers/clk/mvebu/clk-cpu.h                        |   19 ++
 drivers/clk/mvebu/clk.c                            |   36 +++
 9 files changed, 605 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
 create mode 100644 drivers/clk/mvebu/Makefile
 create mode 100644 drivers/clk/mvebu/clk-core.c
 create mode 100644 drivers/clk/mvebu/clk-core.h
 create mode 100644 drivers/clk/mvebu/clk-cpu.c
 create mode 100644 drivers/clk/mvebu/clk-cpu.h
 create mode 100644 drivers/clk/mvebu/clk.c

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
new file mode 100644
index 0000000..d2e0965
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -0,0 +1,40 @@
+Device Tree Clock bindings for core clock of Marvell EBU platforms
+
+This is the binding for the "core" clock of the mvebu SoCs, the rate
+of this clocks are fixed during reset. Their value or ratio are taken
+from the Sample at Reset(SAR) register.
+
+Required properties:
+- compatible : shall be one of the following:
+	"marvell,armada-370-core-clockctrl" - core clock for Armada 370
+	"marvell,armada-xp-core-clockctrl" - core clock for Armada XP
+- reg : Address and length of the SAR register set
+- #clock-cells : should be set to 1.
+- clock-output-names: A list of clock output names that mvebu core
+  clocks provides.  The full list of all valid clock names, IDs and
+  description are below.
+	Name	    ID	    Description
+	tclk	    0	    Peripheral clock
+	pclk	    1	    CPU clock
+	nbclk	    2	    L2 clock
+	hclk	    3	    DRAM control clock
+	dramclk	    4	    DDR clock
+
+coreclk: mvebu-sar@d0018230 {
+	#clock-cells = <1>;
+	reg = <0xd0018230 0x08>;
+	compatible = "marvell,armada-370-core-clockctrl";
+	clock-output-names =
+		"tclk",	    /* 0 */
+		"pclk",	    /* 1 */
+		"nbclk",    /* 2 */
+		"hclk",	    /* 3 */
+		"dramclk",  /* 4 */
+};
+
+timer@d0020300 {
+	       compatible = "marvell,armada-370-xp-timer";
+	       reg = <0xd0020300 0x30>;
+	       interrupts = <37>, <38>, <39>, <40>;
+		   clocks = <&coreclk 0>;
+};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
new file mode 100644
index 0000000..c524618
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -0,0 +1,21 @@
+Device Tree Clock bindings for cpu clock of Marvell EBU platforms
+
+Required properties:
+- compatible : shall be one of the following:
+	"marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP
+- reg : Address and length of the clock complex register set
+- #clock-cells : should be set to 1.
+- clocks : shall be the input parent clock phandle for the clock.
+
+cpuclk: clock-complex@d0018700 {
+	#clock-cells = <1>;
+	compatible = "marvell,armada-xp-cpu-clockctrl";
+	reg = <0xd0018700 0xA0>;
+	clocks = <&coreclk 1>;
+}
+
+cpu@0 {
+   	compatible = "marvell,sheeva-v7";
+	reg = <0>;
+	clocks = <&cpuclk 0>;
+};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 6327536..435e4c0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
 obj-$(CONFIG_ARCH_PRIMA2)	+= clk-prima2.o
+obj-$(CONFIG_ARCH_MVEBU)	+= mvebu/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)		+= mmp/
 endif
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
new file mode 100644
index 0000000..de94a87
--- /dev/null
+++ b/drivers/clk/mvebu/Makefile
@@ -0,0 +1,2 @@
+obj-y += clk.o clk-core.o
+obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
new file mode 100644
index 0000000..5792cb5
--- /dev/null
+++ b/drivers/clk/mvebu/clk-core.c
@@ -0,0 +1,312 @@
+/*
+ * Marvell EBU clock core handling defined at reset
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+/* Sample At Reset is a 64 bit bitfiled split in two register of 32
+ * bits*/
+
+#define SARL				    0	/* Low part [0:31] */
+#define	    SARL_AXP_PCLK_FREQ_OPT	    21
+#define	    SARL_AXP_PCLK_FREQ_OPT_MASK	    0x7
+#define	    SARL_A370_PCLK_FREQ_OPT	    11
+#define	    SARL_A370_PCLK_FREQ_OPT_MASK    0xF
+#define	    SARL_AXP_FAB_FREQ_OPT	    24
+#define	    SARL_AXP_FAB_FREQ_OPT_MASK	    0xF
+#define	    SARL_A370_FAB_FREQ_OPT	    15
+#define	    SARL_A370_FAB_FREQ_OPT_MASK	    0x1F
+#define	    SARL_A370_TCLK_FREQ_OPT	    20
+#define	    SARL_A370_TCLK_FREQ_OPT_MASK    0x1
+#define SARH				    4	/* High part [32:63] */
+#define	    SARH_AXP_PCLK_FREQ_OPT	    (52-32)
+#define	    SARH_AXP_PCLK_FREQ_OPT_MASK	    0x1
+#define	    SARH_AXP_PCLK_FREQ_OPT_SHIFT    3
+#define	    SARH_AXP_FAB_FREQ_OPT	    (51-32)
+#define	    SARH_AXP_FAB_FREQ_OPT_MASK	    0x1
+#define	    SARH_AXP_FAB_FREQ_OPT_SHIFT	    4
+
+u32 *sar_reg;
+int sar_reg_size;
+
+enum core_clk {
+	tclk, pclk, nbclk, hclk, dramclk, clk_max
+};
+
+struct core_clk_fn {
+	u32(*get_tclk_freq) (void);
+	u32(*get_pck_freq) (void);
+	const int *(*get_fab_freq_opt) (void);
+};
+
+/* Ratio between VCO and each of the member in the following order:
+   CPU clock, L2 clock, DRAM controler clock, DDR clcok */
+static const int reset_core_ratio[32][4] = {
+	[0x01] = {1, 2, 2, 2},
+	[0x02] = {2, 2, 6, 3},
+	[0x03] = {2, 2, 3, 3},
+	[0x04] = {1, 2, 3, 3},
+	[0x05] = {1, 2, 4, 2},
+	[0x06] = {1, 1, 2, 2},
+	[0x07] = {2, 3, 6, 6},
+	[0x09] = {1, 2, 6, 3},
+	[0x0A] = {2, 4, 10, 5},
+	[0x0C] = {1, 2, 4, 4},
+	[0x0F] = {2, 2, 5, 5},
+	[0x13] = {1, 1, 2, 1},
+	[0x14] = {2, 3, 6, 3},
+	[0x1B] = {1, 1, 1, 1},
+};
+
+static struct clk *clks[clk_max];
+
+static struct clk_onecell_data clk_data;
+
+/* Frequency in MHz*/
+static u32 armada_370_pclk[] = { 400, 533, 667, 800, 1000, 1067, 1200 };
+
+static u32 armada_xp_pclk[] = { 1000, 1066, 1200, 1333, 1500, 1666,
+	1800, 2000, 667, 0, 800, 1600
+};
+
+static u32 armada_370_tclk[] = { 166, 200 };
+
+static const int *__init armada_370_get_fab_freq_opt(void)
+{
+	u8 fab_freq_opt = 0;
+
+	fab_freq_opt = ((sar_reg[0] >> SARL_A370_FAB_FREQ_OPT) &
+			SARL_A370_FAB_FREQ_OPT_MASK);
+
+	if (reset_core_ratio[fab_freq_opt][0] == 0)
+		return NULL;
+	else
+		return reset_core_ratio[fab_freq_opt];
+}
+
+static u32 __init armada_370_get_pck_freq(void)
+{
+	u32 cpu_freq;
+	u8 cpu_freq_select = 0;
+
+	cpu_freq_select = ((sar_reg[0] >> SARL_A370_PCLK_FREQ_OPT) &
+			   SARL_A370_PCLK_FREQ_OPT_MASK);
+	if (cpu_freq_select > ARRAY_SIZE(armada_370_pclk)) {
+		pr_err("CPU freq select unsuported %d\n", cpu_freq_select);
+		cpu_freq = 0;
+	} else
+		cpu_freq = armada_370_pclk[cpu_freq_select];
+
+	return cpu_freq * 1000 * 1000;
+}
+
+static u32 __init armada_370_get_tclk_freq(void)
+{
+	u32 tclk_freq;
+	u8 tclk_freq_select = 0;
+
+	tclk_freq_select = ((sar_reg[0] >> SARL_A370_TCLK_FREQ_OPT) &
+			    SARL_A370_TCLK_FREQ_OPT_MASK);
+	if (tclk_freq_select > ARRAY_SIZE(armada_370_tclk)) {
+		pr_err("TCLK freq select unsuported %d\n", tclk_freq_select);
+		tclk_freq = 0;
+	} else
+		tclk_freq = armada_370_tclk[tclk_freq_select];
+
+	return tclk_freq * 1000 * 1000;
+}
+
+static const int *__init armada_xp_get_fab_freq_opt(void)
+{
+	u8 fab_freq_opt = 0;
+
+	fab_freq_opt = ((sar_reg[0] >> SARL_AXP_FAB_FREQ_OPT) &
+			SARL_AXP_FAB_FREQ_OPT_MASK);
+	/* The upper bit is not contiguous to the other ones
+	 * and located in the high part of the SAR
+	 * registers */
+	fab_freq_opt |= (((sar_reg[1] >> SARH_AXP_FAB_FREQ_OPT) &
+			  SARH_AXP_FAB_FREQ_OPT_MASK)
+			 << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+	if (reset_core_ratio[fab_freq_opt][0] == 0)
+		return NULL;
+	else
+		return reset_core_ratio[fab_freq_opt];
+}
+
+static u32 __init armada_xp_get_pck_freq(void)
+{
+	u32 cpu_freq;
+	u8 cpu_freq_select = 0;
+
+	cpu_freq_select = ((sar_reg[0] >> SARL_AXP_PCLK_FREQ_OPT) &
+			   SARL_AXP_PCLK_FREQ_OPT_MASK);
+	/* The upper bit is not contiguous to the other ones
+	 * and located in the high part of the SAR
+	 * registers */
+	cpu_freq_select |= (((sar_reg[1] >> SARH_AXP_PCLK_FREQ_OPT) &
+			     SARH_AXP_PCLK_FREQ_OPT_MASK)
+			    << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+	if (cpu_freq_select > ARRAY_SIZE(armada_xp_pclk)) {
+		pr_err("CPU freq select unsuported: %d\n", cpu_freq_select);
+		cpu_freq = 0;
+	} else
+		cpu_freq = armada_xp_pclk[cpu_freq_select];
+
+	return cpu_freq * 1000 * 1000;
+}
+
+/* For Armada XP TCLK frequency is fix: 250MHz */
+static u32 __init armada_xp_get_tclk_freq(void)
+{
+	return 250 * 1000 * 1000;
+}
+
+void __init of_core_clk_setup(struct device_node *node,
+			      struct core_clk_fn clk_fn)
+{
+	struct clk *clk;
+	unsigned long rate;
+	const char *clk_name;
+	int i;
+
+	/* clock 0 is tclk */
+	of_property_read_string_index(node, "clock-output-names", tclk,
+				&clk_name);
+	rate = clk_fn.get_tclk_freq();
+	if (rate != 0)
+		clk = clk_register_fixed_rate(NULL, clk_name, NULL,
+					      CLK_IS_ROOT, rate);
+	else {
+		pr_err("Invalid freq for %s\n", clk_name);
+		return;
+	}
+
+	if (WARN_ON(IS_ERR(clk)))
+		return;
+	clks[tclk] = clk;
+
+	/* clock 1 is pclk */
+	of_property_read_string_index(node, "clock-output-names", pclk,
+				&clk_name);
+	rate = clk_fn.get_pck_freq();
+	if (rate != 0)
+		clk = clk_register_fixed_rate(NULL, clk_name, NULL,
+					      CLK_IS_ROOT, rate);
+	else {
+		pr_err("Invalid freq for %s\n", clk_name);
+		return;
+	}
+	if (WARN_ON(IS_ERR(clk)))
+		return;
+	clks[pclk] = clk;
+
+	/* the clocks 2 to 4 are nbclk, hclk and dramclk and are all
+	 * derivated from the clock 1: pclk */
+
+	for (i = nbclk; i <= dramclk; i++) {
+		const int *ratio = clk_fn.get_fab_freq_opt();
+		const char *parent_clk_name;
+
+		of_property_read_string_index(node, "clock-output-names",
+					 i, &clk_name);
+		of_property_read_string_index(node, "clock-output-names",
+					 pclk, &parent_clk_name);
+
+		if (ratio != NULL)
+			clk = clk_register_fixed_factor(NULL, clk_name,
+							parent_clk_name, 0,
+							ratio[0],
+							ratio[i - nbclk + 1]);
+		else {
+			pr_err("Invalid clk ratio for %s\n", clk_name);
+			return;
+		}
+
+		if (WARN_ON(IS_ERR(clk)))
+			return;
+		clks[i] = clk;
+	}
+	clk_data.clk_num = ARRAY_SIZE(clks);
+	clk_data.clks = clks;
+	of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
+}
+
+static struct core_clk_fn armada_370_clk_fn = {
+	.get_tclk_freq = armada_370_get_tclk_freq,
+	.get_pck_freq = armada_370_get_pck_freq,
+	.get_fab_freq_opt = armada_370_get_fab_freq_opt,
+};
+
+static struct core_clk_fn armada_xp_clk_fn = {
+	.get_tclk_freq = armada_xp_get_tclk_freq,
+	.get_pck_freq = armada_xp_get_pck_freq,
+	.get_fab_freq_opt = armada_xp_get_fab_freq_opt,
+};
+
+static const __initconst struct of_device_id clk_match[] = {
+	{
+	 .compatible = "marvell,armada-370-core-clockctrl",
+	 .data = &armada_370_clk_fn,
+	 },
+
+	{
+	 .compatible = "marvell,armada-xp-core-clockctrl",
+	 .data = &armada_xp_clk_fn,
+	 },
+	{
+	 /* sentinel */
+	 }
+};
+
+void __init mvebu_core_clocks_init(void)
+{
+	struct device_node *np;
+	struct resource res;
+	void __iomem *sar_base;
+	int i;
+
+	np = of_find_node_by_name(NULL, "mvebu-sar");
+
+	if (!np)
+		goto err;
+
+	if (of_address_to_resource(np, 0, &res))
+		goto err;
+
+	sar_reg_size = resource_size(&res);
+	sar_reg = kmalloc(sar_reg_size, GFP_KERNEL);
+
+	sar_base = ioremap(res.start, sar_reg_size);
+	if (sar_base == NULL)
+		goto err;
+	for (i = 0; i < sar_reg_size; i += sizeof(*sar_reg))
+		sar_reg[i] = readl(sar_base + i);
+
+	iounmap(sar_base);
+
+	for_each_matching_node(np, clk_match) {
+		const struct of_device_id *match = of_match_node(clk_match, np);
+		struct core_clk_fn *clk_fn = match->data;
+		of_core_clk_setup(np, *clk_fn);
+	}
+
+	return;
+err:
+	pr_err("%s:SAR base adresse not set in DT\n", __func__);
+	return;
+}
diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
new file mode 100644
index 0000000..a04f80b
--- /dev/null
+++ b/drivers/clk/mvebu/clk-core.h
@@ -0,0 +1,19 @@
+/*
+ *  * Marvell EBU clock core handling defined at reset
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MVEBU_CLK_CORE_H
+#define __MVEBU_CLK_CORE_H
+
+void __init of_core_clk_setup(struct device_node *node);
+void __init mvebu_core_clocks_init(void);
+
+#endif
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
new file mode 100644
index 0000000..6b5c841
--- /dev/null
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -0,0 +1,155 @@
+/*
+ * Marvell MVEBU CPU clock handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+
+#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET    0x0
+#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET   0xC
+#define SYS_CTRL_CLK_DIVIDER_MASK	    0x3F
+
+#define MAX_CPU	    4
+struct cpu_clk {
+	struct clk_hw hw;
+	int cpu;
+	const char *clk_name;
+	const char *parent_name;
+	void __iomem *reg_base;
+};
+
+static struct clk **clks;
+
+static struct clk_onecell_data clk_data;
+
+#define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
+
+static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
+					 unsigned long parent_rate)
+{
+	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
+	u32 reg, div;
+
+	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
+	div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
+	return parent_rate / div;
+}
+
+static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
+			       unsigned long *parent_rate)
+{
+	/* Valid ratio are 1:1, 1:2 and 1:3 */
+	u32 div;
+
+	div = *parent_rate / rate;
+	if (div == 0)
+		div = 1;
+	else if (div > 3)
+		div = 3;
+
+	return *parent_rate / div;
+}
+
+static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
+	u32 reg, div;
+	u32 reload_mask;
+
+	div = parent_rate / rate;
+	reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
+		& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
+		| (div << (cpuclk->cpu * 8));
+	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
+	/* Set clock divider reload smooth bit mask */
+	reload_mask = 1 << (20 + cpuclk->cpu);
+
+	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
+	    | reload_mask;
+	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
+
+	/* Now trigger the clock update */
+	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
+	    | 1 << 24;
+	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
+
+	/* Wait for clocks to settle down then clear reload request */
+	udelay(1000);
+	reg &= ~(reload_mask | 1 << 24);
+	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
+	udelay(1000);
+
+	return 0;
+}
+
+static const struct clk_ops cpu_ops = {
+	.recalc_rate = clk_cpu_recalc_rate,
+	.round_rate = clk_cpu_round_rate,
+	.set_rate = clk_cpu_set_rate,
+};
+
+void __init of_cpu_clk_setup(struct device_node *node)
+{
+	struct cpu_clk *cpuclk;
+	void __iomem *clock_complex_base = of_iomap(node, 0);
+	int cpu;
+	if (clock_complex_base == NULL) {
+		pr_err("%s: clock-complex base register not set\n",
+			__func__);
+		return;
+	}
+
+	cpuclk = kzalloc(MAX_CPU * sizeof(*cpuclk), GFP_KERNEL);
+	clks = kzalloc(MAX_CPU * sizeof(*clks), GFP_KERNEL);
+
+	if (WARN_ON(!cpuclk))
+		return;
+	for (cpu = 0; cpu < MAX_CPU; cpu++) {
+		struct clk_init_data init;
+		struct clk *clk;
+		struct clk *parent_clk;
+		char *clk_name = kzalloc(5, GFP_KERNEL);
+
+		sprintf(clk_name, "cpu%d", cpu);
+		parent_clk = of_clk_get(node, 0);
+
+		cpuclk[cpu].parent_name = __clk_get_name(parent_clk);
+		cpuclk[cpu].clk_name = clk_name;
+		cpuclk[cpu].cpu = cpu;
+		cpuclk[cpu].reg_base = clock_complex_base;
+		cpuclk[cpu].hw.init = &init;
+
+		init.name = cpuclk[cpu].clk_name;
+		init.ops = &cpu_ops;
+		init.flags = 0;
+		init.parent_names = &cpuclk[cpu].parent_name;
+		init.num_parents = 1;
+
+		clk = clk_register(NULL, &cpuclk[cpu].hw);
+		if (WARN_ON(IS_ERR(clk)))
+			goto bail_out;
+		clks[cpu] = clk;
+	}
+	clk_data.clk_num = MAX_CPU;
+	clk_data.clks = clks;
+	of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
+
+	return;
+bail_out:
+	kfree(clks);
+	kfree(cpuclk);
+}
diff --git a/drivers/clk/mvebu/clk-cpu.h b/drivers/clk/mvebu/clk-cpu.h
new file mode 100644
index 0000000..5d28356
--- /dev/null
+++ b/drivers/clk/mvebu/clk-cpu.h
@@ -0,0 +1,19 @@
+/*
+ * Marvell MVEBU CPU clock handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MVEBU_CLK_CPU_H
+#define __MVEBU_CLK_CPU_H
+
+void __init of_cpu_clk_setup(struct device_node *node);
+void __init mvebu_cpu_clocks_init(void);
+
+#endif
diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c
new file mode 100644
index 0000000..0864df7
--- /dev/null
+++ b/drivers/clk/mvebu/clk.c
@@ -0,0 +1,36 @@
+/*
+ * Marvell EBU SoC clock handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
+#include "clk-cpu.h"
+#include "clk-core.h"
+
+static const __initconst struct of_device_id clk_match[] = {
+#ifdef CONFIG_MVEBU_CLK_CPU
+	{
+		.compatible = "marvell,armada-xp-cpu-clockctrl",
+		.data = of_cpu_clk_setup,
+	},
+#endif
+	{
+		/* sentinel */
+	}
+};
+
+void __init mvebu_clocks_init(void)
+{
+	mvebu_core_clocks_init();
+	of_clk_init(clk_match);
+}
-- 
1.7.9.5

Re: [PATCH V2 1/3] clk: mvebu: add armada-370-xp specific clocks

[Mike Turquette]

Quoting Gregory CLEMENT (2012-10-01 14:12:04)
> Add Armada 370/XP specific clocks: core clocks and CPU clocks.
> 
> The CPU clocks are only for Armada XP for the SMP mode.
> 
> The core clocks are clocks which have their rate set during reset. The
> code was written with the other SoCs of the mvebu family in
> mind. Adding them should be pretty straight forward. For a new
> SoC, only 3 binding have to be added:
> - one to provide the tclk frequency
> - one to provde the pclk frequency
> - and one to provide the ratio between the pclk and the children
>   clocks
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Thanks for sending v2 Gregory.  Functionally this series looks good but
unfortunately there are a few style and white space nitpicks below.

> diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
> new file mode 100644
> index 0000000..c524618
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
> @@ -0,0 +1,21 @@
> +Device Tree Clock bindings for cpu clock of Marvell EBU platforms
> +
> +Required properties:
> +- compatible : shall be one of the following:
> +       "marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP
> +- reg : Address and length of the clock complex register set
> +- #clock-cells : should be set to 1.
> +- clocks : shall be the input parent clock phandle for the clock.
> +
> +cpuclk: clock-complex@d0018700 {
> +       #clock-cells = <1>;
> +       compatible = "marvell,armada-xp-cpu-clockctrl";
> +       reg = <0xd0018700 0xA0>;
> +       clocks = <&coreclk 1>;
> +}
> +
> +cpu@0 {
> +       compatible = "marvell,sheeva-v7";

Unnecessary white space before the tab in the line above.

> diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
> new file mode 100644
> index 0000000..5792cb5
> --- /dev/null
> +++ b/drivers/clk/mvebu/clk-core.c
> @@ -0,0 +1,312 @@
> +/*
> + * Marvell EBU clock core handling defined at reset
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/kernel.h>
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +
> +/* Sample At Reset is a 64 bit bitfiled split in two register of 32
> + * bits*/

Can you make this proper comment block style per CodingStyle convention?

> +
> +#define SARL                               0   /* Low part [0:31] */
> +#define            SARL_AXP_PCLK_FREQ_OPT          21
> +#define            SARL_AXP_PCLK_FREQ_OPT_MASK     0x7
> +#define            SARL_A370_PCLK_FREQ_OPT         11
> +#define            SARL_A370_PCLK_FREQ_OPT_MASK    0xF
> +#define            SARL_AXP_FAB_FREQ_OPT           24
> +#define            SARL_AXP_FAB_FREQ_OPT_MASK      0xF
> +#define            SARL_A370_FAB_FREQ_OPT          15
> +#define            SARL_A370_FAB_FREQ_OPT_MASK     0x1F
> +#define            SARL_A370_TCLK_FREQ_OPT         20
> +#define            SARL_A370_TCLK_FREQ_OPT_MASK    0x1
> +#define SARH                               4   /* High part [32:63] */
> +#define            SARH_AXP_PCLK_FREQ_OPT          (52-32)
> +#define            SARH_AXP_PCLK_FREQ_OPT_MASK     0x1
> +#define            SARH_AXP_PCLK_FREQ_OPT_SHIFT    3
> +#define            SARH_AXP_FAB_FREQ_OPT           (51-32)
> +#define            SARH_AXP_FAB_FREQ_OPT_MASK      0x1
> +#define            SARH_AXP_FAB_FREQ_OPT_SHIFT     4
> +
> +u32 *sar_reg;
> +int sar_reg_size;
> +
> +enum core_clk {
> +       tclk, pclk, nbclk, hclk, dramclk, clk_max
> +};
> +
> +struct core_clk_fn {
> +       u32(*get_tclk_freq) (void);
> +       u32(*get_pck_freq) (void);
> +       const int *(*get_fab_freq_opt) (void);
> +};
> +
> +/* Ratio between VCO and each of the member in the following order:
> +   CPU clock, L2 clock, DRAM controler clock, DDR clcok */

ditto

> +static const int reset_core_ratio[32][4] = {
> +       [0x01] = {1, 2, 2, 2},
> +       [0x02] = {2, 2, 6, 3},
> +       [0x03] = {2, 2, 3, 3},
> +       [0x04] = {1, 2, 3, 3},
> +       [0x05] = {1, 2, 4, 2},
> +       [0x06] = {1, 1, 2, 2},
> +       [0x07] = {2, 3, 6, 6},
> +       [0x09] = {1, 2, 6, 3},
> +       [0x0A] = {2, 4, 10, 5},
> +       [0x0C] = {1, 2, 4, 4},
> +       [0x0F] = {2, 2, 5, 5},
> +       [0x13] = {1, 1, 2, 1},
> +       [0x14] = {2, 3, 6, 3},
> +       [0x1B] = {1, 1, 1, 1},
> +};
> +
> +static struct clk *clks[clk_max];
> +
> +static struct clk_onecell_data clk_data;
> +
> +/* Frequency in MHz*/
> +static u32 armada_370_pclk[] = { 400, 533, 667, 800, 1000, 1067, 1200 };
> +
> +static u32 armada_xp_pclk[] = { 1000, 1066, 1200, 1333, 1500, 1666,
> +       1800, 2000, 667, 0, 800, 1600
> +};
> +
> +static u32 armada_370_tclk[] = { 166, 200 };
> +
> +static const int *__init armada_370_get_fab_freq_opt(void)
> +{
> +       u8 fab_freq_opt = 0;
> +
> +       fab_freq_opt = ((sar_reg[0] >> SARL_A370_FAB_FREQ_OPT) &
> +                       SARL_A370_FAB_FREQ_OPT_MASK);
> +
> +       if (reset_core_ratio[fab_freq_opt][0] == 0)
> +               return NULL;
> +       else
> +               return reset_core_ratio[fab_freq_opt];
> +}
> +
> +static u32 __init armada_370_get_pck_freq(void)
> +{
> +       u32 cpu_freq;
> +       u8 cpu_freq_select = 0;
> +
> +       cpu_freq_select = ((sar_reg[0] >> SARL_A370_PCLK_FREQ_OPT) &
> +                          SARL_A370_PCLK_FREQ_OPT_MASK);
> +       if (cpu_freq_select > ARRAY_SIZE(armada_370_pclk)) {
> +               pr_err("CPU freq select unsuported %d\n", cpu_freq_select);
> +               cpu_freq = 0;
> +       } else
> +               cpu_freq = armada_370_pclk[cpu_freq_select];
> +
> +       return cpu_freq * 1000 * 1000;
> +}
> +
> +static u32 __init armada_370_get_tclk_freq(void)
> +{
> +       u32 tclk_freq;
> +       u8 tclk_freq_select = 0;
> +
> +       tclk_freq_select = ((sar_reg[0] >> SARL_A370_TCLK_FREQ_OPT) &
> +                           SARL_A370_TCLK_FREQ_OPT_MASK);
> +       if (tclk_freq_select > ARRAY_SIZE(armada_370_tclk)) {
> +               pr_err("TCLK freq select unsuported %d\n", tclk_freq_select);
> +               tclk_freq = 0;
> +       } else
> +               tclk_freq = armada_370_tclk[tclk_freq_select];
> +
> +       return tclk_freq * 1000 * 1000;
> +}
> +
> +static const int *__init armada_xp_get_fab_freq_opt(void)
> +{
> +       u8 fab_freq_opt = 0;
> +
> +       fab_freq_opt = ((sar_reg[0] >> SARL_AXP_FAB_FREQ_OPT) &
> +                       SARL_AXP_FAB_FREQ_OPT_MASK);
> +       /* The upper bit is not contiguous to the other ones
> +        * and located in the high part of the SAR
> +        * registers */

ditto

> +       fab_freq_opt |= (((sar_reg[1] >> SARH_AXP_FAB_FREQ_OPT) &
> +                         SARH_AXP_FAB_FREQ_OPT_MASK)
> +                        << SARH_AXP_FAB_FREQ_OPT_SHIFT);
> +
> +       if (reset_core_ratio[fab_freq_opt][0] == 0)
> +               return NULL;
> +       else
> +               return reset_core_ratio[fab_freq_opt];
> +}
> +
> +static u32 __init armada_xp_get_pck_freq(void)
> +{
> +       u32 cpu_freq;
> +       u8 cpu_freq_select = 0;
> +
> +       cpu_freq_select = ((sar_reg[0] >> SARL_AXP_PCLK_FREQ_OPT) &
> +                          SARL_AXP_PCLK_FREQ_OPT_MASK);
> +       /* The upper bit is not contiguous to the other ones
> +        * and located in the high part of the SAR
> +        * registers */

ditto

> +       cpu_freq_select |= (((sar_reg[1] >> SARH_AXP_PCLK_FREQ_OPT) &
> +                            SARH_AXP_PCLK_FREQ_OPT_MASK)
> +                           << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
> +       if (cpu_freq_select > ARRAY_SIZE(armada_xp_pclk)) {
> +               pr_err("CPU freq select unsuported: %d\n", cpu_freq_select);
> +               cpu_freq = 0;
> +       } else
> +               cpu_freq = armada_xp_pclk[cpu_freq_select];
> +
> +       return cpu_freq * 1000 * 1000;
> +}
> +
> +/* For Armada XP TCLK frequency is fix: 250MHz */
> +static u32 __init armada_xp_get_tclk_freq(void)
> +{
> +       return 250 * 1000 * 1000;
> +}
> +
> +void __init of_core_clk_setup(struct device_node *node,
> +                             struct core_clk_fn clk_fn)
> +{
> +       struct clk *clk;
> +       unsigned long rate;
> +       const char *clk_name;
> +       int i;
> +
> +       /* clock 0 is tclk */
> +       of_property_read_string_index(node, "clock-output-names", tclk,
> +                               &clk_name);
> +       rate = clk_fn.get_tclk_freq();
> +       if (rate != 0)
> +               clk = clk_register_fixed_rate(NULL, clk_name, NULL,
> +                                             CLK_IS_ROOT, rate);
> +       else {
> +               pr_err("Invalid freq for %s\n", clk_name);
> +               return;
> +       }
> +
> +       if (WARN_ON(IS_ERR(clk)))
> +               return;
> +       clks[tclk] = clk;
> +
> +       /* clock 1 is pclk */
> +       of_property_read_string_index(node, "clock-output-names", pclk,
> +                               &clk_name);
> +       rate = clk_fn.get_pck_freq();
> +       if (rate != 0)
> +               clk = clk_register_fixed_rate(NULL, clk_name, NULL,
> +                                             CLK_IS_ROOT, rate);
> +       else {
> +               pr_err("Invalid freq for %s\n", clk_name);
> +               return;
> +       }
> +       if (WARN_ON(IS_ERR(clk)))
> +               return;
> +       clks[pclk] = clk;
> +
> +       /* the clocks 2 to 4 are nbclk, hclk and dramclk and are all
> +        * derivated from the clock 1: pclk */

ditto

> +
> +       for (i = nbclk; i <= dramclk; i++) {
> +               const int *ratio = clk_fn.get_fab_freq_opt();
> +               const char *parent_clk_name;
> +
> +               of_property_read_string_index(node, "clock-output-names",
> +                                        i, &clk_name);
> +               of_property_read_string_index(node, "clock-output-names",
> +                                        pclk, &parent_clk_name);
> +
> +               if (ratio != NULL)
> +                       clk = clk_register_fixed_factor(NULL, clk_name,
> +                                                       parent_clk_name, 0,
> +                                                       ratio[0],
> +                                                       ratio[i - nbclk + 1]);
> +               else {
> +                       pr_err("Invalid clk ratio for %s\n", clk_name);
> +                       return;
> +               }
> +
> +               if (WARN_ON(IS_ERR(clk)))
> +                       return;
> +               clks[i] = clk;
> +       }
> +       clk_data.clk_num = ARRAY_SIZE(clks);
> +       clk_data.clks = clks;
> +       of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
> +}
> +
> +static struct core_clk_fn armada_370_clk_fn = {
> +       .get_tclk_freq = armada_370_get_tclk_freq,
> +       .get_pck_freq = armada_370_get_pck_freq,
> +       .get_fab_freq_opt = armada_370_get_fab_freq_opt,
> +};
> +
> +static struct core_clk_fn armada_xp_clk_fn = {
> +       .get_tclk_freq = armada_xp_get_tclk_freq,
> +       .get_pck_freq = armada_xp_get_pck_freq,
> +       .get_fab_freq_opt = armada_xp_get_fab_freq_opt,
> +};
> +
> +static const __initconst struct of_device_id clk_match[] = {
> +       {
> +        .compatible = "marvell,armada-370-core-clockctrl",
> +        .data = &armada_370_clk_fn,
> +        },

Indention is a bit weird here.  The members are just indented with one
space and there is an extra white space in front of the closing bracket.
Can you re-align?

> +
> +       {
> +        .compatible = "marvell,armada-xp-core-clockctrl",
> +        .data = &armada_xp_clk_fn,
> +        },

ditto

> +       {
> +        /* sentinel */
> +        }

ditto

> +};
> +
> +void __init mvebu_core_clocks_init(void)
> +{
> +       struct device_node *np;
> +       struct resource res;
> +       void __iomem *sar_base;
> +       int i;
> +
> +       np = of_find_node_by_name(NULL, "mvebu-sar");
> +
> +       if (!np)
> +               goto err;
> +
> +       if (of_address_to_resource(np, 0, &res))
> +               goto err;
> +
> +       sar_reg_size = resource_size(&res);
> +       sar_reg = kmalloc(sar_reg_size, GFP_KERNEL);
> +
> +       sar_base = ioremap(res.start, sar_reg_size);
> +       if (sar_base == NULL)
> +               goto err;
> +       for (i = 0; i < sar_reg_size; i += sizeof(*sar_reg))
> +               sar_reg[i] = readl(sar_base + i);
> +
> +       iounmap(sar_base);
> +
> +       for_each_matching_node(np, clk_match) {
> +               const struct of_device_id *match = of_match_node(clk_match, np);
> +               struct core_clk_fn *clk_fn = match->data;
> +               of_core_clk_setup(np, *clk_fn);
> +       }
> +
> +       return;
> +err:
> +       pr_err("%s:SAR base adresse not set in DT\n", __func__);
> +       return;
> +}
> diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
> new file mode 100644
> index 0000000..a04f80b
> --- /dev/null
> +++ b/drivers/clk/mvebu/clk-core.h
> @@ -0,0 +1,19 @@
> +/*
> + *  * Marvell EBU clock core handling defined at reset
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __MVEBU_CLK_CORE_H
> +#define __MVEBU_CLK_CORE_H
> +
> +void __init of_core_clk_setup(struct device_node *node);
> +void __init mvebu_core_clocks_init(void);
> +
> +#endif
> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
> new file mode 100644
> index 0000000..6b5c841
> --- /dev/null
> +++ b/drivers/clk/mvebu/clk-cpu.c
> @@ -0,0 +1,155 @@
> +/*
> + * Marvell MVEBU CPU clock handling.
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/kernel.h>
> +#include <linux/clk.h>

clk-provider.h includes clk.h, so this is redundant.

Regards,
Mike

Re: [PATCH V2 1/3] clk: mvebu: add armada-370-xp specific clocks

[Gregory CLEMENT]

On 10/30/2012 12:20 PM, Mike Turquette wrote:
> Quoting Gregory CLEMENT (2012-10-01 14:12:04)
>> Add Armada 370/XP specific clocks: core clocks and CPU clocks.
>>
>> The CPU clocks are only for Armada XP for the SMP mode.
>>
>> The core clocks are clocks which have their rate set during reset. The
>> code was written with the other SoCs of the mvebu family in
>> mind. Adding them should be pretty straight forward. For a new
>> SoC, only 3 binding have to be added:
>> - one to provide the tclk frequency
>> - one to provde the pclk frequency
>> - and one to provide the ratio between the pclk and the children
>>   clocks
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> 
> Thanks for sending v2 Gregory.  Functionally this series looks good but
> unfortunately there are a few style and white space nitpicks below.

Hi Mike,

You don't review the last version: I have sent a third version tow weeks
ago (October th 15th). But all your comment should applied for this last
version.

The changelog was
V2 -> V3:
- Rebased on top of v3.7-rc1
- Fixed a typo in device trees
- Fixed warning from checkpatch

Thanks for your review, I will send a new version in few hours.

> 
>> diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
>> new file mode 100644
>> index 0000000..c524618
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
>> @@ -0,0 +1,21 @@
>> +Device Tree Clock bindings for cpu clock of Marvell EBU platforms
>> +
>> +Required properties:
>> +- compatible : shall be one of the following:
>> +       "marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP
>> +- reg : Address and length of the clock complex register set
>> +- #clock-cells : should be set to 1.
>> +- clocks : shall be the input parent clock phandle for the clock.
>> +
>> +cpuclk: clock-complex@d0018700 {
>> +       #clock-cells = <1>;
>> +       compatible = "marvell,armada-xp-cpu-clockctrl";
>> +       reg = <0xd0018700 0xA0>;
>> +       clocks = <&coreclk 1>;
>> +}
>> +
>> +cpu@0 {
>> +       compatible = "marvell,sheeva-v7";
> 
> Unnecessary white space before the tab in the line above.
> 
>> diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
>> new file mode 100644
>> index 0000000..5792cb5
>> --- /dev/null
>> +++ b/drivers/clk/mvebu/clk-core.c
>> @@ -0,0 +1,312 @@
>> +/*
>> + * Marvell EBU clock core handling defined at reset
>> + *
>> + * Copyright (C) 2012 Marvell
>> + *
>> + * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/kernel.h>
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_address.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +
>> +/* Sample At Reset is a 64 bit bitfiled split in two register of 32
>> + * bits*/
> 
> Can you make this proper comment block style per CodingStyle convention?
> 
>> +
>> +#define SARL                               0   /* Low part [0:31] */
>> +#define            SARL_AXP_PCLK_FREQ_OPT          21
>> +#define            SARL_AXP_PCLK_FREQ_OPT_MASK     0x7
>> +#define            SARL_A370_PCLK_FREQ_OPT         11
>> +#define            SARL_A370_PCLK_FREQ_OPT_MASK    0xF
>> +#define            SARL_AXP_FAB_FREQ_OPT           24
>> +#define            SARL_AXP_FAB_FREQ_OPT_MASK      0xF
>> +#define            SARL_A370_FAB_FREQ_OPT          15
>> +#define            SARL_A370_FAB_FREQ_OPT_MASK     0x1F
>> +#define            SARL_A370_TCLK_FREQ_OPT         20
>> +#define            SARL_A370_TCLK_FREQ_OPT_MASK    0x1
>> +#define SARH                               4   /* High part [32:63] */
>> +#define            SARH_AXP_PCLK_FREQ_OPT          (52-32)
>> +#define            SARH_AXP_PCLK_FREQ_OPT_MASK     0x1
>> +#define            SARH_AXP_PCLK_FREQ_OPT_SHIFT    3
>> +#define            SARH_AXP_FAB_FREQ_OPT           (51-32)
>> +#define            SARH_AXP_FAB_FREQ_OPT_MASK      0x1
>> +#define            SARH_AXP_FAB_FREQ_OPT_SHIFT     4
>> +
>> +u32 *sar_reg;
>> +int sar_reg_size;
>> +
>> +enum core_clk {
>> +       tclk, pclk, nbclk, hclk, dramclk, clk_max
>> +};
>> +
>> +struct core_clk_fn {
>> +       u32(*get_tclk_freq) (void);
>> +       u32(*get_pck_freq) (void);
>> +       const int *(*get_fab_freq_opt) (void);
>> +};
>> +
>> +/* Ratio between VCO and each of the member in the following order:
>> +   CPU clock, L2 clock, DRAM controler clock, DDR clcok */
> 
> ditto
> 
>> +static const int reset_core_ratio[32][4] = {
>> +       [0x01] = {1, 2, 2, 2},
>> +       [0x02] = {2, 2, 6, 3},
>> +       [0x03] = {2, 2, 3, 3},
>> +       [0x04] = {1, 2, 3, 3},
>> +       [0x05] = {1, 2, 4, 2},
>> +       [0x06] = {1, 1, 2, 2},
>> +       [0x07] = {2, 3, 6, 6},
>> +       [0x09] = {1, 2, 6, 3},
>> +       [0x0A] = {2, 4, 10, 5},
>> +       [0x0C] = {1, 2, 4, 4},
>> +       [0x0F] = {2, 2, 5, 5},
>> +       [0x13] = {1, 1, 2, 1},
>> +       [0x14] = {2, 3, 6, 3},
>> +       [0x1B] = {1, 1, 1, 1},
>> +};
>> +
>> +static struct clk *clks[clk_max];
>> +
>> +static struct clk_onecell_data clk_data;
>> +
>> +/* Frequency in MHz*/
>> +static u32 armada_370_pclk[] = { 400, 533, 667, 800, 1000, 1067, 1200 };
>> +
>> +static u32 armada_xp_pclk[] = { 1000, 1066, 1200, 1333, 1500, 1666,
>> +       1800, 2000, 667, 0, 800, 1600
>> +};
>> +
>> +static u32 armada_370_tclk[] = { 166, 200 };
>> +
>> +static const int *__init armada_370_get_fab_freq_opt(void)
>> +{
>> +       u8 fab_freq_opt = 0;
>> +
>> +       fab_freq_opt = ((sar_reg[0] >> SARL_A370_FAB_FREQ_OPT) &
>> +                       SARL_A370_FAB_FREQ_OPT_MASK);
>> +
>> +       if (reset_core_ratio[fab_freq_opt][0] == 0)
>> +               return NULL;
>> +       else
>> +               return reset_core_ratio[fab_freq_opt];
>> +}
>> +
>> +static u32 __init armada_370_get_pck_freq(void)
>> +{
>> +       u32 cpu_freq;
>> +       u8 cpu_freq_select = 0;
>> +
>> +       cpu_freq_select = ((sar_reg[0] >> SARL_A370_PCLK_FREQ_OPT) &
>> +                          SARL_A370_PCLK_FREQ_OPT_MASK);
>> +       if (cpu_freq_select > ARRAY_SIZE(armada_370_pclk)) {
>> +               pr_err("CPU freq select unsuported %d\n", cpu_freq_select);
>> +               cpu_freq = 0;
>> +       } else
>> +               cpu_freq = armada_370_pclk[cpu_freq_select];
>> +
>> +       return cpu_freq * 1000 * 1000;
>> +}
>> +
>> +static u32 __init armada_370_get_tclk_freq(void)
>> +{
>> +       u32 tclk_freq;
>> +       u8 tclk_freq_select = 0;
>> +
>> +       tclk_freq_select = ((sar_reg[0] >> SARL_A370_TCLK_FREQ_OPT) &
>> +                           SARL_A370_TCLK_FREQ_OPT_MASK);
>> +       if (tclk_freq_select > ARRAY_SIZE(armada_370_tclk)) {
>> +               pr_err("TCLK freq select unsuported %d\n", tclk_freq_select);
>> +               tclk_freq = 0;
>> +       } else
>> +               tclk_freq = armada_370_tclk[tclk_freq_select];
>> +
>> +       return tclk_freq * 1000 * 1000;
>> +}
>> +
>> +static const int *__init armada_xp_get_fab_freq_opt(void)
>> +{
>> +       u8 fab_freq_opt = 0;
>> +
>> +       fab_freq_opt = ((sar_reg[0] >> SARL_AXP_FAB_FREQ_OPT) &
>> +                       SARL_AXP_FAB_FREQ_OPT_MASK);
>> +       /* The upper bit is not contiguous to the other ones
>> +        * and located in the high part of the SAR
>> +        * registers */
> 
> ditto
> 
>> +       fab_freq_opt |= (((sar_reg[1] >> SARH_AXP_FAB_FREQ_OPT) &
>> +                         SARH_AXP_FAB_FREQ_OPT_MASK)
>> +                        << SARH_AXP_FAB_FREQ_OPT_SHIFT);
>> +
>> +       if (reset_core_ratio[fab_freq_opt][0] == 0)
>> +               return NULL;
>> +       else
>> +               return reset_core_ratio[fab_freq_opt];
>> +}
>> +
>> +static u32 __init armada_xp_get_pck_freq(void)
>> +{
>> +       u32 cpu_freq;
>> +       u8 cpu_freq_select = 0;
>> +
>> +       cpu_freq_select = ((sar_reg[0] >> SARL_AXP_PCLK_FREQ_OPT) &
>> +                          SARL_AXP_PCLK_FREQ_OPT_MASK);
>> +       /* The upper bit is not contiguous to the other ones
>> +        * and located in the high part of the SAR
>> +        * registers */
> 
> ditto
> 
>> +       cpu_freq_select |= (((sar_reg[1] >> SARH_AXP_PCLK_FREQ_OPT) &
>> +                            SARH_AXP_PCLK_FREQ_OPT_MASK)
>> +                           << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
>> +       if (cpu_freq_select > ARRAY_SIZE(armada_xp_pclk)) {
>> +               pr_err("CPU freq select unsuported: %d\n", cpu_freq_select);
>> +               cpu_freq = 0;
>> +       } else
>> +               cpu_freq = armada_xp_pclk[cpu_freq_select];
>> +
>> +       return cpu_freq * 1000 * 1000;
>> +}
>> +
>> +/* For Armada XP TCLK frequency is fix: 250MHz */
>> +static u32 __init armada_xp_get_tclk_freq(void)
>> +{
>> +       return 250 * 1000 * 1000;
>> +}
>> +
>> +void __init of_core_clk_setup(struct device_node *node,
>> +                             struct core_clk_fn clk_fn)
>> +{
>> +       struct clk *clk;
>> +       unsigned long rate;
>> +       const char *clk_name;
>> +       int i;
>> +
>> +       /* clock 0 is tclk */
>> +       of_property_read_string_index(node, "clock-output-names", tclk,
>> +                               &clk_name);
>> +       rate = clk_fn.get_tclk_freq();
>> +       if (rate != 0)
>> +               clk = clk_register_fixed_rate(NULL, clk_name, NULL,
>> +                                             CLK_IS_ROOT, rate);
>> +       else {
>> +               pr_err("Invalid freq for %s\n", clk_name);
>> +               return;
>> +       }
>> +
>> +       if (WARN_ON(IS_ERR(clk)))
>> +               return;
>> +       clks[tclk] = clk;
>> +
>> +       /* clock 1 is pclk */
>> +       of_property_read_string_index(node, "clock-output-names", pclk,
>> +                               &clk_name);
>> +       rate = clk_fn.get_pck_freq();
>> +       if (rate != 0)
>> +               clk = clk_register_fixed_rate(NULL, clk_name, NULL,
>> +                                             CLK_IS_ROOT, rate);
>> +       else {
>> +               pr_err("Invalid freq for %s\n", clk_name);
>> +               return;
>> +       }
>> +       if (WARN_ON(IS_ERR(clk)))
>> +               return;
>> +       clks[pclk] = clk;
>> +
>> +       /* the clocks 2 to 4 are nbclk, hclk and dramclk and are all
>> +        * derivated from the clock 1: pclk */
> 
> ditto
> 
>> +
>> +       for (i = nbclk; i <= dramclk; i++) {
>> +               const int *ratio = clk_fn.get_fab_freq_opt();
>> +               const char *parent_clk_name;
>> +
>> +               of_property_read_string_index(node, "clock-output-names",
>> +                                        i, &clk_name);
>> +               of_property_read_string_index(node, "clock-output-names",
>> +                                        pclk, &parent_clk_name);
>> +
>> +               if (ratio != NULL)
>> +                       clk = clk_register_fixed_factor(NULL, clk_name,
>> +                                                       parent_clk_name, 0,
>> +                                                       ratio[0],
>> +                                                       ratio[i - nbclk + 1]);
>> +               else {
>> +                       pr_err("Invalid clk ratio for %s\n", clk_name);
>> +                       return;
>> +               }
>> +
>> +               if (WARN_ON(IS_ERR(clk)))
>> +                       return;
>> +               clks[i] = clk;
>> +       }
>> +       clk_data.clk_num = ARRAY_SIZE(clks);
>> +       clk_data.clks = clks;
>> +       of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
>> +}
>> +
>> +static struct core_clk_fn armada_370_clk_fn = {
>> +       .get_tclk_freq = armada_370_get_tclk_freq,
>> +       .get_pck_freq = armada_370_get_pck_freq,
>> +       .get_fab_freq_opt = armada_370_get_fab_freq_opt,
>> +};
>> +
>> +static struct core_clk_fn armada_xp_clk_fn = {
>> +       .get_tclk_freq = armada_xp_get_tclk_freq,
>> +       .get_pck_freq = armada_xp_get_pck_freq,
>> +       .get_fab_freq_opt = armada_xp_get_fab_freq_opt,
>> +};
>> +
>> +static const __initconst struct of_device_id clk_match[] = {
>> +       {
>> +        .compatible = "marvell,armada-370-core-clockctrl",
>> +        .data = &armada_370_clk_fn,
>> +        },
> 
> Indention is a bit weird here.  The members are just indented with one
> space and there is an extra white space in front of the closing bracket.
> Can you re-align?
> 
>> +
>> +       {
>> +        .compatible = "marvell,armada-xp-core-clockctrl",
>> +        .data = &armada_xp_clk_fn,
>> +        },
> 
> ditto
> 
>> +       {
>> +        /* sentinel */
>> +        }
> 
> ditto
> 
>> +};
>> +
>> +void __init mvebu_core_clocks_init(void)
>> +{
>> +       struct device_node *np;
>> +       struct resource res;
>> +       void __iomem *sar_base;
>> +       int i;
>> +
>> +       np = of_find_node_by_name(NULL, "mvebu-sar");
>> +
>> +       if (!np)
>> +               goto err;
>> +
>> +       if (of_address_to_resource(np, 0, &res))
>> +               goto err;
>> +
>> +       sar_reg_size = resource_size(&res);
>> +       sar_reg = kmalloc(sar_reg_size, GFP_KERNEL);
>> +
>> +       sar_base = ioremap(res.start, sar_reg_size);
>> +       if (sar_base == NULL)
>> +               goto err;
>> +       for (i = 0; i < sar_reg_size; i += sizeof(*sar_reg))
>> +               sar_reg[i] = readl(sar_base + i);
>> +
>> +       iounmap(sar_base);
>> +
>> +       for_each_matching_node(np, clk_match) {
>> +               const struct of_device_id *match = of_match_node(clk_match, np);
>> +               struct core_clk_fn *clk_fn = match->data;
>> +               of_core_clk_setup(np, *clk_fn);
>> +       }
>> +
>> +       return;
>> +err:
>> +       pr_err("%s:SAR base adresse not set in DT\n", __func__);
>> +       return;
>> +}
>> diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
>> new file mode 100644
>> index 0000000..a04f80b
>> --- /dev/null
>> +++ b/drivers/clk/mvebu/clk-core.h
>> @@ -0,0 +1,19 @@
>> +/*
>> + *  * Marvell EBU clock core handling defined at reset
>> + *
>> + * Copyright (C) 2012 Marvell
>> + *
>> + * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#ifndef __MVEBU_CLK_CORE_H
>> +#define __MVEBU_CLK_CORE_H
>> +
>> +void __init of_core_clk_setup(struct device_node *node);
>> +void __init mvebu_core_clocks_init(void);
>> +
>> +#endif
>> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
>> new file mode 100644
>> index 0000000..6b5c841
>> --- /dev/null
>> +++ b/drivers/clk/mvebu/clk-cpu.c
>> @@ -0,0 +1,155 @@
>> +/*
>> + * Marvell MVEBU CPU clock handling.
>> + *
>> + * Copyright (C) 2012 Marvell
>> + *
>> + * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/kernel.h>
>> +#include <linux/clk.h>
> 
> clk-provider.h includes clk.h, so this is redundant.
> 
> Regards,
> Mike
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH V2 2/3] clk: armada-370-xp: add support for clock framework

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 arch/arm/boot/dts/armada-370.dtsi   |   12 +++++++++
 arch/arm/boot/dts/armada-xp.dtsi    |   48 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/Kconfig         |    5 ++++
 arch/arm/mach-mvebu/armada-370-xp.c |    8 +++++-
 arch/arm/mach-mvebu/common.h        |    1 +
 5 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..9bfc904 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -31,5 +31,17 @@
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
+		coreclk: mvebu-sar@d0018230 {
+			#clock-cells = <1>;
+			reg = <0xd0018230 0x08>;
+			compatible = "marvell,armada-370-core-clockctrl";
+			clock-output-names =
+				"tclk",	    /* 0 */
+				"pclk",	    /* 1 */
+				"nbclk",    /* 2 */
+				"hclk",	    /* 3 */
+				"dramclk",  /* 4 */
+		};
+
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d..e75f3a2 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -27,6 +27,35 @@
 		    <0xd0021870 0x58>;
 	};
 
+	cpus {
+	    #address-cells = <1>;
+	    #size-cells = <0>;
+
+	    cpu@0 {
+	       	compatible = "marvell,sheeva-v7";
+		reg = <0>;
+		clocks = <&cpuclk 0>;
+	    };
+
+	    cpu@1 {
+		compatible = "marvell,sheeva-v7";
+		reg = <1>;
+		clocks = <&cpuclk 1>;
+	    };
+
+	    cpu@2 {
+		compatible = "marvell,sheeva-v7";
+		reg = <2>;
+		clocks = <&cpuclk 2>;
+	    };
+
+	    cpu@3 {
+		compatible = "marvell,sheeva-v7";
+		reg = <3>;
+		clocks = <&cpuclk 3>;
+	    };
+	};
+
 	soc {
 		serial@d0012200 {
 				compatible = "ns16550";
@@ -47,6 +76,25 @@
 				marvell,timer-25Mhz;
 		};
 
+		coreclk: mvebu-sar@d0018230 {
+			#clock-cells = <1>;
+			reg = <0xd0018230 0x08>;
+			compatible = "marvell,armada-xp-core-clockctrl";
+			clock-output-names =
+				"tclk",	    /* 0 */
+				"pclk",	    /* 1 */
+				"nbclk",    /* 2 */
+				"hclk",	    /* 3 */
+				"dramclk",  /* 4 */
+		};
+
+		cpuclk: clock-complex@d0018700 {
+			#clock-cells = <1>;
+			compatible = "marvell,armada-xp-cpu-clockctrl";
+			reg = <0xd0018700 0xA0>;
+			clocks = <&coreclk 1>;
+		};
+
 		system-controller@d0018200 {
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x500>;
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e..0370af9 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -2,10 +2,15 @@ if ARCH_MVEBU
 
 menu "Marvell SOC with device tree"
 
+config MVEBU_CLK_CPU
+	   bool
+
 config MACH_ARMADA_370_XP
 	bool "Marvell Armada 370 and Aramada XP boards"
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+	select CLKDEV_LOOKUP
+	select MVEBU_CLK_CPU
 	help
 
 	  Say 'Y' here if you want your kernel to support boards based on
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 4ef923b..612e2c2 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -37,8 +37,14 @@ void __init armada_370_xp_map_io(void)
 	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
 }
 
+void __init armada_370_xp_timer_and_clk_init(void)
+{
+	mvebu_clocks_init();
+	armada_370_xp_timer_init();
+}
+
 struct sys_timer armada_370_xp_timer = {
-	.init		= armada_370_xp_timer_init,
+	.init		= armada_370_xp_timer_and_clk_init,
 };
 
 static void __init armada_370_xp_dt_init(void)
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 02f89ea..281fab3 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -16,6 +16,7 @@
 #define __ARCH_MVEBU_COMMON_H
 
 void mvebu_restart(char mode, const char *cmd);
+void mvebu_clocks_init(void);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
-- 
1.7.9.5

Re: [PATCH V2 2/3] clk: armada-370-xp: add support for clock framework

[Mike Turquette]

Quoting Gregory CLEMENT (2012-10-01 14:12:05)
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This didn't apply cleanly to -rc3.  Can you rebase this along with the
respin of patch #1 in the series?

<snip>

> diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
> index 71d6b5d..e75f3a2 100644
> --- a/arch/arm/boot/dts/armada-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-xp.dtsi
> @@ -27,6 +27,35 @@
>                     <0xd0021870 0x58>;
>         };
>  
> +       cpus {
> +           #address-cells = <1>;
> +           #size-cells = <0>;
> +
> +           cpu@0 {
> +               compatible = "marvell,sheeva-v7";

Extra white space in front of compatible.  Should be tabs.

Regards,
Mike

[PATCH V2 3/3] clocksource: time-armada-370-xp converted to clk framework

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 arch/arm/boot/dts/armada-370-db.dts      |    4 ----
 arch/arm/boot/dts/armada-370-xp.dtsi     |    1 +
 drivers/clocksource/time-armada-370-xp.c |   11 ++++++-----
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index fffd5c2..4a31b03 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -34,9 +34,5 @@
 			clock-frequency = <200000000>;
 			status = "okay";
 		};
-		timer@d0020300 {
-			clock-frequency = <600000000>;
-			status = "okay";
-		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932..e62f478 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -62,6 +62,7 @@
 			       compatible = "marvell,armada-370-xp-timer";
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
+			       clocks = <&coreclk 2>;
 		};
 	};
 };
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index 4674f94..a4605fd 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/timer.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
@@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)
 	u32 u;
 	struct device_node *np;
 	unsigned int timer_clk;
-	int ret;
 	np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
 	timer_base = of_iomap(np, 0);
 	WARN_ON(!timer_base);
@@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void)
 		       timer_base + TIMER_CTRL_OFF);
 		timer_clk = 25000000;
 	} else {
-		u32 clk = 0;
-		ret = of_property_read_u32(np, "clock-frequency", &clk);
-		WARN_ON(!clk || ret < 0);
+		unsigned long rate = 0;
+		struct clk *clk = of_clk_get(np, 0);
+		WARN_ON(IS_ERR(clk));
+		rate =  clk_get_rate(clk);
 		u = readl(timer_base + TIMER_CTRL_OFF);
 		writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
 		       timer_base + TIMER_CTRL_OFF);
-		timer_clk = clk / TIMER_DIVIDER;
+		timer_clk = rate / TIMER_DIVIDER;
 	}
 
 	/* We use timer 0 as clocksource, and timer 1 for
-- 
1.7.9.5

Re: [PATCH V2 3/3] clocksource: time-armada-370-xp converted to clk framework

[Mike Turquette]

Quoting Gregory CLEMENT (2012-10-01 14:12:06)
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

I'm not sure this patch should go through me.  Perhaps John Stultz?

Regards,
Mike

Re: [PATCH V2 3/3] clocksource: time-armada-370-xp converted to clk framework

[John Stultz]

On 10/30/2012 04:52 AM, Mike Turquette wrote:
> Quoting Gregory CLEMENT (2012-10-01 14:12:06)
>> Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> I'm not sure this patch should go through me.  Perhaps John Stultz?

I can apply it to my tree, but really none of it is generic, so in the 
future I'd almost rather someone who could reasonably audit the changes 
for correctness merge it instead (although I always appreciate being 
Cc'ed into the loop).

thanks
-john

Re: [PATCH V2 0/3] Add clock framework for armada 370/XP

[Mike Turquette]

Quoting Gregory CLEMENT (2012-10-01 14:12:03)
> Hello Mike,
> 
> My first version didn't get many attention, so I guess it's too late
> for 3.7! ;) I should have ping you earlier about this series. This
> time was not lost, by using the cpu clock with SMP I found a bug and
> fixed it. And I also improved the spelling and removed unnecessary
> small piece of code thanks to the feed back of Andrew Lunn.
> 

My apologies for letting this one slip through the cracks.  I'm glad you
fixed the bug though!

I'll give this a review once the -rc1 merge window is closed.

Regards,
Mike

> The purpose of this patch set is to add support for clock framework
> for Armada 370 and Armada XP SoCs. All the support is done under the
> directory drivers/clk/mvebu/ as the support for other mvebu SoCs was
> in mind during the writing of the code.
> 
> Two kinds of clocks are added:
> 
> - The CPU clocks are only for Armada XP (which si multi-core)
> 
> - The core clocks are clocks which have their rate fixed during
>   reset.
> 
> This patch set is based on the clk-3.7 branch of Mike Turquette as it
> use the patch "clk: add of_clk_src_onecell_get() support" from Shawn
> Guo.
> 
> Many thanks to Thomas Petazzoni and Sebastian Hesselbarth for their
> review and feedback. The device tree bindings were really improved
> with the advices of Sebastian.
> 
> Changelog:
> V1 -> V2:
> 
> - Improved the spelling and the wording of the documentation and the
>   1st commit log
> - Removed the "end_of_list" name which are unused here.
> - Fix the cpu clock by using of_clk_src_onecell_get in the same way it
>   was used for the core clocks
> 
> Regards,
> 
> Gregory CLEMENT (3):
>   clk: mvebu: add armada-370-xp specific clocks
>   clk: armada-370-xp: add support for clock framework
>   clocksource: time-armada-370-xp converted to clk framework
> 
>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   40 +++
>  .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   21 ++
>  arch/arm/boot/dts/armada-370-db.dts                |    4 -
>  arch/arm/boot/dts/armada-370-xp.dtsi               |    1 +
>  arch/arm/boot/dts/armada-370.dtsi                  |   12 +
>  arch/arm/boot/dts/armada-xp.dtsi                   |   48 +++
>  arch/arm/mach-mvebu/Kconfig                        |    5 +
>  arch/arm/mach-mvebu/armada-370-xp.c                |    8 +-
>  arch/arm/mach-mvebu/common.h                       |    1 +
>  drivers/clk/Makefile                               |    1 +
>  drivers/clk/mvebu/Makefile                         |    2 +
>  drivers/clk/mvebu/clk-core.c                       |  312 ++++++++++++++++++++
>  drivers/clk/mvebu/clk-core.h                       |   19 ++
>  drivers/clk/mvebu/clk-cpu.c                        |  155 ++++++++++
>  drivers/clk/mvebu/clk-cpu.h                        |   19 ++
>  drivers/clk/mvebu/clk.c                            |   36 +++
>  drivers/clocksource/time-armada-370-xp.c           |   11 +-
>  17 files changed, 685 insertions(+), 10 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
>  create mode 100644 drivers/clk/mvebu/Makefile
>  create mode 100644 drivers/clk/mvebu/clk-core.c
>  create mode 100644 drivers/clk/mvebu/clk-core.h
>  create mode 100644 drivers/clk/mvebu/clk-cpu.c
>  create mode 100644 drivers/clk/mvebu/clk-cpu.h
>  create mode 100644 drivers/clk/mvebu/clk.c
> 
> -- 
> 1.7.9.5

Re: [PATCH V2 0/3] Add clock framework for armada 370/XP

[Gregory CLEMENT]

On 10/02/2012 06:17 AM, Mike Turquette wrote:
> Quoting Gregory CLEMENT (2012-10-01 14:12:03)
>> Hello Mike,
>>
>> My first version didn't get many attention, so I guess it's too late
>> for 3.7! ;) I should have ping you earlier about this series. This
>> time was not lost, by using the cpu clock with SMP I found a bug and
>> fixed it. And I also improved the spelling and removed unnecessary
>> small piece of code thanks to the feed back of Andrew Lunn.
>>
> 
> My apologies for letting this one slip through the cracks.  I'm glad you
> fixed the bug though!
> 
> I'll give this a review once the -rc1 merge window is closed.

This time I will remind you as soon as -rc1 will be released ;)

I have an other patch set which will depend on this one. So I hope
this one will be merged early enough in your clk-3.8 branch.

Regards,
Gregory

> 
> Regards,
> Mike
> 
>> The purpose of this patch set is to add support for clock framework
>> for Armada 370 and Armada XP SoCs. All the support is done under the
>> directory drivers/clk/mvebu/ as the support for other mvebu SoCs was
>> in mind during the writing of the code.
>>
>> Two kinds of clocks are added:
>>
>> - The CPU clocks are only for Armada XP (which si multi-core)
>>
>> - The core clocks are clocks which have their rate fixed during
>>   reset.
>>
>> This patch set is based on the clk-3.7 branch of Mike Turquette as it
>> use the patch "clk: add of_clk_src_onecell_get() support" from Shawn
>> Guo.
>>
>> Many thanks to Thomas Petazzoni and Sebastian Hesselbarth for their
>> review and feedback. The device tree bindings were really improved
>> with the advices of Sebastian.
>>
>> Changelog:
>> V1 -> V2:
>>
>> - Improved the spelling and the wording of the documentation and the
>>   1st commit log
>> - Removed the "end_of_list" name which are unused here.
>> - Fix the cpu clock by using of_clk_src_onecell_get in the same way it
>>   was used for the core clocks
>>
>> Regards,
>>
>> Gregory CLEMENT (3):
>>   clk: mvebu: add armada-370-xp specific clocks
>>   clk: armada-370-xp: add support for clock framework
>>   clocksource: time-armada-370-xp converted to clk framework
>>
>>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   40 +++
>>  .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   21 ++
>>  arch/arm/boot/dts/armada-370-db.dts                |    4 -
>>  arch/arm/boot/dts/armada-370-xp.dtsi               |    1 +
>>  arch/arm/boot/dts/armada-370.dtsi                  |   12 +
>>  arch/arm/boot/dts/armada-xp.dtsi                   |   48 +++
>>  arch/arm/mach-mvebu/Kconfig                        |    5 +
>>  arch/arm/mach-mvebu/armada-370-xp.c                |    8 +-
>>  arch/arm/mach-mvebu/common.h                       |    1 +
>>  drivers/clk/Makefile                               |    1 +
>>  drivers/clk/mvebu/Makefile                         |    2 +
>>  drivers/clk/mvebu/clk-core.c                       |  312 ++++++++++++++++++++
>>  drivers/clk/mvebu/clk-core.h                       |   19 ++
>>  drivers/clk/mvebu/clk-cpu.c                        |  155 ++++++++++
>>  drivers/clk/mvebu/clk-cpu.h                        |   19 ++
>>  drivers/clk/mvebu/clk.c                            |   36 +++
>>  drivers/clocksource/time-armada-370-xp.c           |   11 +-
>>  17 files changed, 685 insertions(+), 10 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
>>  create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
>>  create mode 100644 drivers/clk/mvebu/Makefile
>>  create mode 100644 drivers/clk/mvebu/clk-core.c
>>  create mode 100644 drivers/clk/mvebu/clk-core.h
>>  create mode 100644 drivers/clk/mvebu/clk-cpu.c
>>  create mode 100644 drivers/clk/mvebu/clk-cpu.h
>>  create mode 100644 drivers/clk/mvebu/clk.c
>>
>> -- 
>> 1.7.9.5
> 
> _______________________________________________
> linux-arm-kernel mailing list
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> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com