From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH V4 5/5] arm: mvebu: Added SMP support for Armada XP Date: Tue, 20 Nov 2012 16:40:58 +0000 Message-ID: <20121120164058.GB27765@mudshark.cambridge.arm.com> References: <1353357360-7242-1-git-send-email-gregory.clement@free-electrons.com> <1353357360-7242-6-git-send-email-gregory.clement@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1353357360-7242-6-git-send-email-gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: Gregory CLEMENT Cc: Lior Amsalem , Andrew Lunn , Ike Pan , Nadav Haklai , Ian Molton , David Marlin , Yehuda Yitschak , Jani Monoses , Russell King , Tawfik Bayouk , Dan Frazier , Eran Ben-Avi , Leif Lindholm , Sebastian Hesselbarth , Jason Cooper , "jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org" , "devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" , "rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org" , Ben Dooks , Mike Turquette , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: devicetree@vger.kernel.org On Mon, Nov 19, 2012 at 08:35:59PM +0000, Gregory CLEMENT wrote: > +/* > + * Armada XP specific entry point for secondary CPUs. > + * We add the CPU to the coherency fabric and then jump to secondary > + * startup > + */ > +ENTRY(armada_xp_secondary_startup) > + > + /* Read CPU id */ > + mrc p15, 0, r1, c0, c0, 5 > + and r1, r1, #0xF > + > + /* Add CPU to coherency fabric */ > + > + ldr r0, = ARMADA_XP_CFB_BASE > + mov lr, pc > + b ll_set_cpu_coherent > + b secondary_startup adr lr, BSYM(secondary_startup) bl ll_set_cpu_coherent should let you get rid of the mov, b, b, although I think you could do better than that by making this function a prefix of ll_set_cpu_coherent: ENTRY(armada_xp_secondary_startup) ldr r0, =ARMADA_XP_CFB_BASE mrc p15, 0, r1, c0, c0, 5 and r1, r1, #0xF adr lr, BSYM(secondary_startup) /* Fallthrough */ ENTRY(ll_set_cpu_coherent) ... ENDPROC(ll_set_cpu_coherent) ENDPROC(armada_xp_secondary_startup) what do you think? Will