From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: [PATCH v8 5/5] ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND Date: Mon, 14 Jan 2013 10:06:02 -0800 Message-ID: <20130114180602.GV14149@atomide.com> References: <1355481404-27695-1-git-send-email-zonque@gmail.com> <1355481404-27695-6-git-send-email-zonque@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-omap-owner@vger.kernel.org To: Ezequiel Garcia Cc: Daniel Mack , linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, jon-hunter@ti.com, avinashphilip@ti.com, x0148406@ti.com, paul@pwsan.com, nsekhar@ti.com, jacmet@sunsite.dk, grant.likely@secretlab.ca, rob.herring@calxeda.com, devicetree-discuss@lists.ozlabs.org, Javier Martinez Canillas , Enric Balletbo Serra List-Id: devicetree@vger.kernel.org * Ezequiel Garcia [121223 13:49]: > On Fri, Dec 14, 2012 at 7:36 AM, Daniel Mack wrote: > > + > > +Example for an AM33xx board: > > + > > + gpmc: gpmc@50000000 { > > + compatible = "ti,am3352-gpmc"; > > + ti,hwmods = "gpmc"; > > + reg = <0x50000000 0x1000000>; > > + interrupts = <100>; > > + gpmc,num-cs = <8>; > > + gpmc,num-waitpins = <2>; > > + #address-cells = <2>; > > + #size-cells = <1>; > > + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ > > + > > + nand@0,0 { > > + reg = <0 0 0>; /* CS0, offset 0 */ > > I'm a bit confused by this: what are the other two values in "reg"? > I see you've only added a binding for CS. > > I've extended a bit on your work and added a binding to enable OneNAND > device on my IGEP board. > > I might send some patches in case anyone wants to give it a try. Daniel, should this be updated to just pass the CS? Regards, Tony