Re: [PATCH v2 1/4] ARM i.MX6: use reserved bit for mxs phy clock gate

[Peter Chen <peter.chen@freescale.com>]

On Tue, Jan 15, 2013 at 07:33:16PM +0800, Shawn Guo wrote:
> On Tue, Jan 15, 2013 at 02:08:34PM +0800, Peter Chen wrote:
> > For mxs-phy user i.mx6q, the PHY's clock is controlled by
> > hardware automatically, the software only needs to enable it
> > at probe, disable it at remove. During the runtime,
> > we don't need to control it. So for the usbphy clk policy:
> > 
> > - Keep refcount for usbphy as clk framework needs to know if
> > it is off or on.
> 
> Just checked the reference manual, it seems that not only bit 6
> (EN_USB_CLKS) but also bit 12 (POWER) are controlled by USB hardware.
> If this is true, I think that PLL3 and PLL7 are really designed for
> USB PHY use only.  Do you actually see other real users of these two
> PLLs on imx6q besides USB PHY?  If not, we can just provide a dummy
> clock to mxs-phy driver on imx6q, and keep real clocks usbphy1 and
> usbphy2 there for platform init function to enable them if USB support
> is built in.  Then, we can save all these dirty hacks.  Thoughts?
It was my v1 patch did.

I send the v2 patch due to below reasons,
There are other PLL3 users, it is better keep refcount
to all its children, or the user will be confused when the
PLL3 goes to disable, but the usb otg part is still used

For PLL7, we can do it, and let the PLL7 be out of clock framework
management.

But I still think keep usbphy as PLL child is better solution,
in that case, the clock maintainer can know the real clock usage.

> 
> Shawn
> 
> > - Use reserved bit, in that case, clk_enable/disable will
> > only update refcount, but without any hardware effects.
> > 
> > Signed-off-by: Peter Chen <peter.chen@freescale.com>
> > ---
> > Changes for v2:
> > - Use reserved bit for usb phy clk control
> > 
> >  arch/arm/mach-imx/clk-imx6q.c |   10 ++++++++--
> >  1 files changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> > index 7f2c10c..85dcc89 100644
> > --- a/arch/arm/mach-imx/clk-imx6q.c
> > +++ b/arch/arm/mach-imx/clk-imx6q.c
> > @@ -208,8 +208,14 @@ int __init mx6q_clocks_init(void)
> >  	clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x3);
> >  	clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,	"pll8_mlb",	"osc", base + 0xd0, 0x0);
> >  
> > -	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
> > -	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
> > +	/*
> > +	 * Bit 20 is the reserved and read-only bit, we do this only for:
> > +	 * - Do nothing for usbphy clk_enable/disable
> > +	 * - Keep refcount when do usbphy clk_enable/disable, in that case,
> > +	 * the clk framework can know the USB phy clk is on or off
> > +	 */
> > +	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
> > +	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
> >  
> >  	clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
> >  	clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
> > -- 
> > 1.7.0.4
> > 
> > 

-- 

Best Regards,
Peter Chen