From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH V3 2/3] ARM: mmc: bcm281xx SDHCI driver Date: Wed, 29 May 2013 16:25:36 +0200 Message-ID: <201305291625.37068.arnd@arndb.de> References: <1369790016-13270-1-git-send-email-csd@broadcom.com> <1369790016-13270-2-git-send-email-csd@broadcom.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1369790016-13270-2-git-send-email-csd-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: Christian Daudt Cc: linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Jerry Huang , Wei WANG , matt.porter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Kevin Liu , Lars-Peter Clausen , Stephen Warren , Viresh Kumar , Chris Ball , devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, Sascha Hauer , Rob Herring , Bill Pemberton , Russell King , Anton Vorontsov , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Greg Kroah-Hartman , linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Guennadi Liakhovetski List-Id: devicetree@vger.kernel.org On Wednesday 29 May 2013, Christian Daudt wrote: > +static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host) > +{ > + /* > + * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) > + * Back-to-Back writes to same register needs delay when SD bus clock > + * is very low w.r.t AHB clock, mainly during boot-time and during card > + * insert-removal. > + */ > + mdelay(1); > + sdhci_writel(host, val, KONA_SDHOST_CORECTRL); This is now called always without spinlocks held and interrupts enabled, so it should really be msleep() not mdelay(). > +static void sdhci_bcm_kona_sd_init(struct sdhci_host *host) > +{ > + unsigned int val; > + > + /* enable the interrupt from the IP core */ > + val = sdhci_readl(host, KONA_SDHOST_COREIMR); > + val |= KONA_SDHOST_IP; > + sdhci_writel(host, val, KONA_SDHOST_COREIMR); > + > + /* Enable the AHB clock gating module to the host */ > + val = sdhci_readl(host, KONA_SDHOST_CORECTRL); > + val |= KONA_SDHOST_EN; > + > + /* > + * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) > + * Back-to-Back writes to same register needs delay when SD bus clock > + * is very low w.r.t AHB clock, mainly during boot-time and during card > + * insert-removal. > + */ > + mdelay(1); > + sdhci_writel(host, val, KONA_SDHOST_CORECTRL); > +} Same here. Looks good aside from that. Arnd