From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH 7/9] documentation: iommu: add description of ARM System MMU binding Date: Thu, 20 Jun 2013 22:08:45 +0200 Message-ID: <20130620200845.GF11309@8bytes.org> References: <1370889285-22799-1-git-send-email-will.deacon@arm.com> <1370889285-22799-8-git-send-email-will.deacon@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1370889285-22799-8-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Will Deacon Cc: Andreas Herrmann , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Rob Herring , devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Mon, Jun 10, 2013 at 07:34:43PM +0100, Will Deacon wrote: > This patch adds a description of the device tree binding for the ARM > System MMU architecture. Interesting, will this be a common driver to replace existing ARM IOMMU drivers or is it a common driver for ARM IOMMUs found in future chips? > +- smmu-parent : When multiple SMMUs are chained together, this > + property can be used to provide a phandle to the > + parent SMMU (that is the next SMMU on the path going > + from the mmu-masters towards memory) node for this > + SMMU. What happens when SMMUs are chained? Will the second SMMU seeing the DMA just pass it through or is it translated again? Thanks, Joerg