* [PATCH v6 0/3] arm: add basic support for Rockchip Cortex-A9 SoCs
@ 2013-06-20 23:29 Heiko Stübner
[not found] ` <201306210129.54629.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Heiko Stübner @ 2013-06-20 23:29 UTC (permalink / raw)
To: Olof Johansson
Cc: Grant Likely, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Sixth version of basic Rockchip A9 support.
This time again using the regular gate clocks as the driver got accepted into
the clock tree.
Changes since v5:
- reintroduce the use of the gate clocks
Changes since v4:
- remove ifdef around l2x0 init
- only use dummy clocks
Changes since v3:
- split out standalone dw_mmc patches (submitted to linux-mmc)
- Remove divider and mux clocks and use fixed rate clocks instead until
divider and mux clocks have got their generic dt bindings
- Make the gate clock use CLK_OF_DECLARE and document the bindings
Changes since v2:
- use common (pending review) HIWORD_MASK clock flag from Haojian Zhuang and me
- pinctrl driver is already in the pinctrl tree
- add core-periph clock that supplies the twd
- split "mmc: dw_mmc-pltfm: add Rockchip variant" into move and feature parts
as suggested by Andy Shevchenko
Changes since v1:
- addressed Linus Walleij's comments to the pinctrl driver, including the
move to generic pinconfig (hopefully I did catch all)
- renamed the clocks to use the SoC name of the initial user
as suggested by Olof Johansson
- fixed the uart address, found by Arnd Bergmann
- address Arnd's comments on the board file (use of_clk_init and friends,
remove map_io, use real soc names)
- removed Makefile.boot as suggested by Thomas Petazzoni
no dependencies
Heiko Stuebner (3):
arm: Add basic clocks for Rockchip rk3066a SoCs
arm: add debug uarts for rockchip rk29xx and rk3xxx series
arm: add basic support for Rockchip RK3066a boards
arch/arm/Kconfig | 2 +
arch/arm/Kconfig.debug | 34 +++
arch/arm/Makefile | 1 +
arch/arm/boot/dts/rk3066a-clocks.dtsi | 299 +++++++++++++++++++++++++
arch/arm/boot/dts/rk3066a.dtsi | 390 +++++++++++++++++++++++++++++++++
arch/arm/include/debug/rockchip.S | 42 ++++
arch/arm/mach-rockchip/Kconfig | 16 ++
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rockchip.c | 52 +++++
9 files changed, 837 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3066a-clocks.dtsi
create mode 100644 arch/arm/boot/dts/rk3066a.dtsi
create mode 100644 arch/arm/include/debug/rockchip.S
create mode 100644 arch/arm/mach-rockchip/Kconfig
create mode 100644 arch/arm/mach-rockchip/Makefile
create mode 100644 arch/arm/mach-rockchip/rockchip.c
--
1.7.10.4
^ permalink raw reply [flat|nested] 6+ messages in thread[parent not found: <201306210129.54629.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>]
* [PATCH v6 1/3] arm: Add basic clocks for Rockchip rk3066a SoCs [not found] ` <201306210129.54629.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> @ 2013-06-20 23:30 ` Heiko Stübner [not found] ` <201306210130.33033.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> 2013-06-20 23:31 ` [PATCH v6 2/3] arm: add debug uarts for rockchip rk29xx and rk3xxx series Heiko Stübner 2013-06-20 23:31 ` [PATCH v6 3/3] arm: add basic support for Rockchip RK3066a boards Heiko Stübner 2 siblings, 1 reply; 6+ messages in thread From: Heiko Stübner @ 2013-06-20 23:30 UTC (permalink / raw) To: Olof Johansson Cc: Grant Likely, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org This adds a basic clock setup for rk3066a SoCs. Only the gates are set up currently, as the mux and dividers should use the upcoming generic devicetree bindings. Clocks whose rates need to be known are supplied by fixed-rate "dummy"-clocks that provide the correct rate. This is uncritical insofar that the only bootloader currently in existence for Rockchip devices is the propietary Rockchip one that always setups the clocks in the necessary way. Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> --- arch/arm/boot/dts/rk3066a-clocks.dtsi | 299 +++++++++++++++++++++++++++++++++ 1 file changed, 299 insertions(+) create mode 100644 arch/arm/boot/dts/rk3066a-clocks.dtsi diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi new file mode 100644 index 0000000..6e307fc --- /dev/null +++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + dummy48m: dummy48m { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + dummy150m: dummy150m { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gates0: gate-clk@200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk@200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + }; + + clk_gates2: gate-clk@200000d8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d8 0x4>; + clocks = <&clk_gates2 1>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&clk_gates2 3>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_periph_src", "gate_aclk_periph", + "gate_hclk_periph", "gate_pclk_periph", + "gate_smc", "gate_mac", + "gate_hsadc", "gate_hsadc_frac", + "gate_saradc", "gate_spi0", + "gate_spi1", "gate_mmc0", + "gate_mac_lbtest", "gate_mmc1", + "gate_emmc", "gate_tsadc"; + + #clock-cells = <1>; + }; + + clk_gates3: gate-clk@200000dc { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000dc 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", + "gate_dclk_lcdc1", "gate_pclkin_cif0", + "gate_pclkin_cif1", "reserved", + "reserved", "gate_cif0_out", + "gate_cif1_out", "gate_aclk_vepu", + "gate_hclk_vepu", "gate_aclk_vdpu", + "gate_hclk_vdpu", "gate_gpu_src", + "reserved", "gate_xin27m"; + + #clock-cells = <1>; + }; + + clk_gates4: gate-clk@200000e0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e0 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates2 3>, + <&clk_gates2 1>, <&clk_gates2 1>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 3>, <&clk_gates0 3>, + <&clk_gates0 3>, <&clk_gates2 3>, + <&clk_gates0 4>; + + clock-output-names = + "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", + "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", + "gate_aclk_pei_niu", "gate_hclk_usb_peri", + "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", + "gate_hclk_cpubus", "gate_hclk_ahb2apb", + "gate_aclk_strc_sys", "gate_aclk_l2mem_con", + "gate_aclk_intmem", "gate_pclk_tsadc", + "gate_hclk_hdmi"; + + #clock-cells = <1>; + }; + + clk_gates5: gate-clk@200000e4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e4 0x4>; + clocks = <&clk_gates0 3>, <&clk_gates2 1>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 4>, <&clk_gates0 5>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates4 5>, + <&clk_gates4 5>, <&dummy>; + + clock-output-names = + "gate_aclk_dmac1", "gate_aclk_dmac2", + "gate_pclk_efuse", "gate_pclk_tzpc", + "gate_pclk_grf", "gate_pclk_pmu", + "gate_hclk_rom", "gate_pclk_ddrupctl", + "gate_aclk_smc", "gate_hclk_nandc", + "gate_hclk_mmc0", "gate_hclk_mmc1", + "gate_hclk_emmc", "gate_hclk_otg0", + "gate_hclk_otg1", "gate_aclk_gpu"; + + #clock-cells = <1>; + }; + + clk_gates6: gate-clk@200000e8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e8 0x4>; + clocks = <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0", "gate_hclk_lcdc0", + "gate_hclk_lcdc1", "gate_aclk_lcdc1", + "gate_hclk_cif0", "gate_aclk_cif0", + "gate_hclk_cif1", "gate_aclk_cif1", + "gate_aclk_ipp", "gate_hclk_ipp", + "gate_hclk_rga", "gate_aclk_rga", + "gate_hclk_vio_bus", "gate_aclk_vio0", + "gate_aclk_vcodec", "gate_shclk_vio_h2h"; + + #clock-cells = <1>; + }; + + clk_gates7: gate-clk@200000ec { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000ec 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>; + + clock-output-names = + "gate_hclk_emac", "gate_hclk_spdif", + "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", + "gate_hclk_i2s_8ch", "gate_hclk_hsadc", + "gate_hclk_pidf", "gate_pclk_timer0", + "gate_pclk_timer1", "gate_pclk_timer2", + "gate_pclk_pwm01", "gate_pclk_pwm23", + "gate_pclk_spi0", "gate_pclk_spi1", + "gate_pclk_saradc", "gate_pclk_wdt"; + + #clock-cells = <1>; + }; + + clk_gates8: gate-clk@200000f0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f0 0x4>; + clocks = <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&dummy>, <&clk_gates0 5>; + + clock-output-names = + "gate_pclk_uart0", "gate_pclk_uart1", + "gate_pclk_uart2", "gate_pclk_uart3", + "gate_pclk_i2c0", "gate_pclk_i2c1", + "gate_pclk_i2c2", "gate_pclk_i2c3", + "gate_pclk_i2c4", "gate_pclk_gpio0", + "gate_pclk_gpio1", "gate_pclk_gpio2", + "gate_pclk_gpio3", "gate_pclk_gpio4", + "reserved", "gate_pclk_gpio6"; + + #clock-cells = <1>; + }; + + clk_gates9: gate-clk@200000f4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f4 0x4>; + clocks = <&dummy>, <&clk_gates0 5>, + <&dummy>, <&dummy>, + <&dummy>, <&clk_gates1 4>, + <&clk_gates0 5>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>; + + clock-output-names = + "gate_clk_core_dbg", "gate_pclk_dbg", + "gate_clk_trace", "gate_atclk", + "gate_clk_l2c", "gate_aclk_vio1", + "gate_pclk_publ", "gate_aclk_intmem0", + "gate_aclk_intmem1", "gate_aclk_intmem2", + "gate_aclk_intmem3"; + + #clock-cells = <1>; + }; + }; + +}; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
[parent not found: <201306210130.33033.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>]
* Re: [PATCH v6 1/3] arm: Add basic clocks for Rockchip rk3066a SoCs [not found] ` <201306210130.33033.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> @ 2013-06-21 1:22 ` Mike Turquette 0 siblings, 0 replies; 6+ messages in thread From: Mike Turquette @ 2013-06-21 1:22 UTC (permalink / raw) To: Heiko Stübner, Olof Johansson Cc: Grant Likely, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Quoting Heiko Stübner (2013-06-20 16:30:32) > This adds a basic clock setup for rk3066a SoCs. Only the gates are > set up currently, as the mux and dividers should use the upcoming > generic devicetree bindings. > > Clocks whose rates need to be known are supplied by fixed-rate > "dummy"-clocks that provide the correct rate. This is uncritical insofar > that the only bootloader currently in existence for Rockchip devices > is the propietary Rockchip one that always setups the clocks in the > necessary way. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> Looks good to me. As I mentioned previously we might be able to convert the rockchip,rk2928-gate-clk stuff over to the generic gate-clock binding once hiword-mask support and support for clock-cells == 1 is added in. I'm hacking on the former now and the latter may go in for 3.12. Reviewed-by: Mike Turquette <mturquette@linaro.org> > --- > arch/arm/boot/dts/rk3066a-clocks.dtsi | 299 +++++++++++++++++++++++++++++++++ > 1 file changed, 299 insertions(+) > create mode 100644 arch/arm/boot/dts/rk3066a-clocks.dtsi > > diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi > new file mode 100644 > index 0000000..6e307fc > --- /dev/null > +++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi > @@ -0,0 +1,299 @@ > +/* > + * Copyright (c) 2013 MundoReader S.L. > + * Author: Heiko Stuebner <heiko@sntech.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +/ { > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + /* > + * This is a dummy clock, to be used as placeholder on > + * other mux clocks when a specific parent clock is not > + * yet implemented. It should be dropped when the driver > + * is complete. > + */ > + dummy: dummy { > + compatible = "fixed-clock"; > + clock-frequency = <0>; > + #clock-cells = <0>; > + }; > + > + xin24m: xin24m { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + #clock-cells = <0>; > + }; > + > + dummy48m: dummy48m { > + compatible = "fixed-clock"; > + clock-frequency = <48000000>; > + #clock-cells = <0>; > + }; > + > + dummy150m: dummy150m { > + compatible = "fixed-clock"; > + clock-frequency = <150000000>; > + #clock-cells = <0>; > + }; > + > + clk_gates0: gate-clk@200000d0 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000d0 0x4>; > + clocks = <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>; > + > + clock-output-names = > + "gate_core_periph", "gate_cpu_gpll", > + "gate_ddrphy", "gate_aclk_cpu", > + "gate_hclk_cpu", "gate_pclk_cpu", > + "gate_atclk_cpu", "gate_i2s0", > + "gate_i2s0_frac", "gate_i2s1", > + "gate_i2s1_frac", "gate_i2s2", > + "gate_i2s2_frac", "gate_spdif", > + "gate_spdif_frac", "gate_testclk"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates1: gate-clk@200000d4 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000d4 0x4>; > + clocks = <&xin24m>, <&xin24m>, > + <&xin24m>, <&dummy>, > + <&dummy>, <&xin24m>, > + <&xin24m>, <&dummy>, > + <&xin24m>, <&dummy>, > + <&xin24m>, <&dummy>, > + <&xin24m>, <&dummy>, > + <&xin24m>, <&dummy>; > + > + clock-output-names = > + "gate_timer0", "gate_timer1", > + "gate_timer2", "gate_jtag", > + "gate_aclk_lcdc1_src", "gate_otgphy0", > + "gate_otgphy1", "gate_ddr_gpll", > + "gate_uart0", "gate_frac_uart0", > + "gate_uart1", "gate_frac_uart1", > + "gate_uart2", "gate_frac_uart2", > + "gate_uart3", "gate_frac_uart3"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates2: gate-clk@200000d8 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000d8 0x4>; > + clocks = <&clk_gates2 1>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&clk_gates2 3>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy48m>, > + <&dummy>, <&dummy48m>, > + <&dummy>, <&dummy>; > + > + clock-output-names = > + "gate_periph_src", "gate_aclk_periph", > + "gate_hclk_periph", "gate_pclk_periph", > + "gate_smc", "gate_mac", > + "gate_hsadc", "gate_hsadc_frac", > + "gate_saradc", "gate_spi0", > + "gate_spi1", "gate_mmc0", > + "gate_mac_lbtest", "gate_mmc1", > + "gate_emmc", "gate_tsadc"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates3: gate-clk@200000dc { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000dc 0x4>; > + clocks = <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>, <&dummy>; > + > + clock-output-names = > + "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", > + "gate_dclk_lcdc1", "gate_pclkin_cif0", > + "gate_pclkin_cif1", "reserved", > + "reserved", "gate_cif0_out", > + "gate_cif1_out", "gate_aclk_vepu", > + "gate_hclk_vepu", "gate_aclk_vdpu", > + "gate_hclk_vdpu", "gate_gpu_src", > + "reserved", "gate_xin27m"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates4: gate-clk@200000e0 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000e0 0x4>; > + clocks = <&clk_gates2 2>, <&clk_gates2 3>, > + <&clk_gates2 1>, <&clk_gates2 1>, > + <&clk_gates2 1>, <&clk_gates2 2>, > + <&clk_gates2 2>, <&clk_gates2 2>, > + <&clk_gates0 4>, <&clk_gates0 4>, > + <&clk_gates0 3>, <&clk_gates0 3>, > + <&clk_gates0 3>, <&clk_gates2 3>, > + <&clk_gates0 4>; > + > + clock-output-names = > + "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", > + "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", > + "gate_aclk_pei_niu", "gate_hclk_usb_peri", > + "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", > + "gate_hclk_cpubus", "gate_hclk_ahb2apb", > + "gate_aclk_strc_sys", "gate_aclk_l2mem_con", > + "gate_aclk_intmem", "gate_pclk_tsadc", > + "gate_hclk_hdmi"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates5: gate-clk@200000e4 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000e4 0x4>; > + clocks = <&clk_gates0 3>, <&clk_gates2 1>, > + <&clk_gates0 5>, <&clk_gates0 5>, > + <&clk_gates0 5>, <&clk_gates0 5>, > + <&clk_gates0 4>, <&clk_gates0 5>, > + <&clk_gates2 1>, <&clk_gates2 2>, > + <&clk_gates2 2>, <&clk_gates2 2>, > + <&clk_gates2 2>, <&clk_gates4 5>, > + <&clk_gates4 5>, <&dummy>; > + > + clock-output-names = > + "gate_aclk_dmac1", "gate_aclk_dmac2", > + "gate_pclk_efuse", "gate_pclk_tzpc", > + "gate_pclk_grf", "gate_pclk_pmu", > + "gate_hclk_rom", "gate_pclk_ddrupctl", > + "gate_aclk_smc", "gate_hclk_nandc", > + "gate_hclk_mmc0", "gate_hclk_mmc1", > + "gate_hclk_emmc", "gate_hclk_otg0", > + "gate_hclk_otg1", "gate_aclk_gpu"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates6: gate-clk@200000e8 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000e8 0x4>; > + clocks = <&clk_gates3 0>, <&clk_gates0 4>, > + <&clk_gates0 4>, <&clk_gates1 4>, > + <&clk_gates0 4>, <&clk_gates3 0>, > + <&clk_gates0 4>, <&clk_gates1 4>, > + <&clk_gates3 0>, <&clk_gates0 4>, > + <&clk_gates0 4>, <&clk_gates1 4>, > + <&clk_gates0 4>, <&clk_gates3 0>, > + <&dummy>, <&dummy>; > + > + clock-output-names = > + "gate_aclk_lcdc0", "gate_hclk_lcdc0", > + "gate_hclk_lcdc1", "gate_aclk_lcdc1", > + "gate_hclk_cif0", "gate_aclk_cif0", > + "gate_hclk_cif1", "gate_aclk_cif1", > + "gate_aclk_ipp", "gate_hclk_ipp", > + "gate_hclk_rga", "gate_aclk_rga", > + "gate_hclk_vio_bus", "gate_aclk_vio0", > + "gate_aclk_vcodec", "gate_shclk_vio_h2h"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates7: gate-clk@200000ec { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000ec 0x4>; > + clocks = <&clk_gates2 2>, <&clk_gates0 4>, > + <&clk_gates0 4>, <&clk_gates0 4>, > + <&clk_gates0 4>, <&clk_gates2 2>, > + <&clk_gates2 2>, <&clk_gates0 5>, > + <&clk_gates0 5>, <&clk_gates0 5>, > + <&clk_gates0 5>, <&clk_gates2 3>, > + <&clk_gates2 3>, <&clk_gates2 3>, > + <&clk_gates2 3>, <&clk_gates2 3>; > + > + clock-output-names = > + "gate_hclk_emac", "gate_hclk_spdif", > + "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", > + "gate_hclk_i2s_8ch", "gate_hclk_hsadc", > + "gate_hclk_pidf", "gate_pclk_timer0", > + "gate_pclk_timer1", "gate_pclk_timer2", > + "gate_pclk_pwm01", "gate_pclk_pwm23", > + "gate_pclk_spi0", "gate_pclk_spi1", > + "gate_pclk_saradc", "gate_pclk_wdt"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates8: gate-clk@200000f0 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000f0 0x4>; > + clocks = <&clk_gates0 5>, <&clk_gates0 5>, > + <&clk_gates2 3>, <&clk_gates2 3>, > + <&clk_gates0 5>, <&clk_gates0 5>, > + <&clk_gates2 3>, <&clk_gates2 3>, > + <&clk_gates2 3>, <&clk_gates0 5>, > + <&clk_gates0 5>, <&clk_gates0 5>, > + <&clk_gates2 3>, <&clk_gates2 3>, > + <&dummy>, <&clk_gates0 5>; > + > + clock-output-names = > + "gate_pclk_uart0", "gate_pclk_uart1", > + "gate_pclk_uart2", "gate_pclk_uart3", > + "gate_pclk_i2c0", "gate_pclk_i2c1", > + "gate_pclk_i2c2", "gate_pclk_i2c3", > + "gate_pclk_i2c4", "gate_pclk_gpio0", > + "gate_pclk_gpio1", "gate_pclk_gpio2", > + "gate_pclk_gpio3", "gate_pclk_gpio4", > + "reserved", "gate_pclk_gpio6"; > + > + #clock-cells = <1>; > + }; > + > + clk_gates9: gate-clk@200000f4 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000f4 0x4>; > + clocks = <&dummy>, <&clk_gates0 5>, > + <&dummy>, <&dummy>, > + <&dummy>, <&clk_gates1 4>, > + <&clk_gates0 5>, <&dummy>, > + <&dummy>, <&dummy>, > + <&dummy>; > + > + clock-output-names = > + "gate_clk_core_dbg", "gate_pclk_dbg", > + "gate_clk_trace", "gate_atclk", > + "gate_clk_l2c", "gate_aclk_vio1", > + "gate_pclk_publ", "gate_aclk_intmem0", > + "gate_aclk_intmem1", "gate_aclk_intmem2", > + "gate_aclk_intmem3"; > + > + #clock-cells = <1>; > + }; > + }; > + > +}; > -- > 1.7.10.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v6 2/3] arm: add debug uarts for rockchip rk29xx and rk3xxx series [not found] ` <201306210129.54629.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> 2013-06-20 23:30 ` [PATCH v6 1/3] arm: Add basic clocks for Rockchip rk3066a SoCs Heiko Stübner @ 2013-06-20 23:31 ` Heiko Stübner [not found] ` <201306210131.11224.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> 2013-06-20 23:31 ` [PATCH v6 3/3] arm: add basic support for Rockchip RK3066a boards Heiko Stübner 2 siblings, 1 reply; 6+ messages in thread From: Heiko Stübner @ 2013-06-20 23:31 UTC (permalink / raw) To: Olof Johansson Cc: Grant Likely, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types. Only their addresses vary very much. This patch adds the necessary definitions to use any of the uart ports for early debug purposes. Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> --- arch/arm/Kconfig.debug | 34 ++++++++++++++++++++++++++++++ arch/arm/include/debug/rockchip.S | 42 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 arch/arm/include/debug/rockchip.S diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 003f371..0e88bc8 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -399,6 +399,13 @@ choice their output to the standard serial port on the RealView PB1176 platform. + config DEBUG_ROCKCHIP_UART + bool "Kernel low-level debugging messages via Rockchip UART" + depends on ARCH_ROCKCHIP + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS @@ -643,6 +650,32 @@ endchoice choice prompt "Low-level debug console UART" + depends on DEBUG_ROCKCHIP_UART + + config DEBUG_RK29_UART0 + bool "RK29 UART0" + + config DEBUG_RK29_UART1 + bool "RK29 UART1" + + config DEBUG_RK29_UART2 + bool "RK29 UART2" + + config DEBUG_RK3X_UART0 + bool "RK3X UART0" + + config DEBUG_RK3X_UART1 + bool "RK3X UART1" + + config DEBUG_RK3X_UART2 + bool "RK3X UART2" + + config DEBUG_RK3X_UART3 + bool "RK3X UART3" +endchoice + +choice + prompt "Low-level debug console UART" depends on DEBUG_LL && DEBUG_TEGRA_UART config TEGRA_DEBUG_UART_AUTO_ODMDATA @@ -697,6 +730,7 @@ config DEBUG_LL_INCLUDE default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \ DEBUG_MMP_UART3 + default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S new file mode 100644 index 0000000..cfd883e --- /dev/null +++ b/arch/arm/include/debug/rockchip.S @@ -0,0 +1,42 @@ +/* + * Early serial output macro for Rockchip SoCs + * + * Copyright (C) 2012 Maxime Ripard + * + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#if defined(CONFIG_DEBUG_RK29_UART0) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000 +#elif defined(CONFIG_DEBUG_RK29_UART1) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 +#elif defined(CONFIG_DEBUG_RK29_UART2) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 +#elif defined(CONFIG_DEBUG_RK3X_UART0) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000 +#elif defined(CONFIG_DEBUG_RK3X_UART1) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000 +#elif defined(CONFIG_DEBUG_RK3X_UART2) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 +#elif defined(CONFIG_DEBUG_RK3X_UART3) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 +#endif + + .macro addruart, rp, rv, tmp + ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE + ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
[parent not found: <201306210131.11224.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>]
* Re: [PATCH v6 2/3] arm: add debug uarts for rockchip rk29xx and rk3xxx series [not found] ` <201306210131.11224.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> @ 2013-06-21 7:30 ` Olof Johansson 0 siblings, 0 replies; 6+ messages in thread From: Olof Johansson @ 2013-06-21 7:30 UTC (permalink / raw) To: Heiko Stübner Cc: Grant Likely, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Fri, Jun 21, 2013 at 01:31:10AM +0200, Heiko Stübner wrote: > Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types. > Only their addresses vary very much. > > This patch adds the necessary definitions to use any of the uart ports > for early debug purposes. > > Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> Acked-by: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> -Olof ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v6 3/3] arm: add basic support for Rockchip RK3066a boards [not found] ` <201306210129.54629.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> 2013-06-20 23:30 ` [PATCH v6 1/3] arm: Add basic clocks for Rockchip rk3066a SoCs Heiko Stübner 2013-06-20 23:31 ` [PATCH v6 2/3] arm: add debug uarts for rockchip rk29xx and rk3xxx series Heiko Stübner @ 2013-06-20 23:31 ` Heiko Stübner 2 siblings, 0 replies; 6+ messages in thread From: Heiko Stübner @ 2013-06-20 23:31 UTC (permalink / raw) To: Olof Johansson Cc: Grant Likely, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org This adds a generic devicetree board file and a dtsi for boards based on the RK3066a SoCs from Rockchip. Apart from the generic parts (gic, clocks, pinctrl) the only components currently supported are the timers, uarts and mmc ports (all DesignWare- based). Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> Acked-by: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/boot/dts/rk3066a.dtsi | 390 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 16 ++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rockchip.c | 52 +++++ 6 files changed, 462 insertions(+) create mode 100644 arch/arm/boot/dts/rk3066a.dtsi create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/rockchip.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ca30d75..6c696f5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1006,6 +1006,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-realview/Kconfig" +source "arch/arm/mach-rockchip/Kconfig" + source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d7e5e8c..c01e4a7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -172,6 +172,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell machine-$(CONFIG_ARCH_SIRF) += prima2 machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_REALVIEW) += realview +machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi new file mode 100644 index 0000000..56bfac9 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "skeleton.dtsi" +#include "rk3066a-clocks.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&dummy150m>; + }; + + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clock-names = "timer", "pclk"; + }; + + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clock-names = "timer", "pclk"; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + reg = <0x20008000 0x150>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 11>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 13>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 15>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 8>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 10>; + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 12>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 14>; + status = "disabled"; + }; + + dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + + dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig new file mode 100644 index 0000000..25ee12b --- /dev/null +++ b/arch/arm/mach-rockchip/Kconfig @@ -0,0 +1,16 @@ +config ARCH_ROCKCHIP + bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7 + select PINCTRL + select PINCTRL_ROCKCHIP + select ARCH_REQUIRE_GPIOLIB + select ARM_GIC + select CACHE_L2X0 + select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_SMP + select LOCAL_TIMERS if SMP + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select DW_APB_TIMER_OF + help + Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs + containing the RK2928, RK30xx and RK31xx series. diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile new file mode 100644 index 0000000..1547d4f --- /dev/null +++ b/arch/arm/mach-rockchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c new file mode 100644 index 0000000..724d2d8 --- /dev/null +++ b/arch/arm/mach-rockchip/rockchip.c @@ -0,0 +1,52 @@ +/* + * Device Tree support for Rockchip SoCs + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/irqchip.h> +#include <linux/dw_apb_timer.h> +#include <linux/clk-provider.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +static void __init rockchip_timer_init(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + +static void __init rockchip_dt_init(void) +{ + l2x0_of_init(0, ~0UL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const rockchip_board_dt_compat[] = { + "rockchip,rk2928", + "rockchip,rk3066a", + "rockchip,rk3066b", + "rockchip,rk3188", + NULL, +}; + +DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") + .init_machine = rockchip_dt_init, + .init_time = rockchip_timer_init, + .dt_compat = rockchip_board_dt_compat, +MACHINE_END -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-06-21 7:30 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2013-06-20 23:29 [PATCH v6 0/3] arm: add basic support for Rockchip Cortex-A9 SoCs Heiko Stübner
[not found] ` <201306210129.54629.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
2013-06-20 23:30 ` [PATCH v6 1/3] arm: Add basic clocks for Rockchip rk3066a SoCs Heiko Stübner
[not found] ` <201306210130.33033.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
2013-06-21 1:22 ` Mike Turquette
2013-06-20 23:31 ` [PATCH v6 2/3] arm: add debug uarts for rockchip rk29xx and rk3xxx series Heiko Stübner
[not found] ` <201306210131.11224.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
2013-06-21 7:30 ` Olof Johansson
2013-06-20 23:31 ` [PATCH v6 3/3] arm: add basic support for Rockchip RK3066a boards Heiko Stübner
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