* [PATCH V6 1/6] ARM: samsung: use #include for all device trees
2013-06-12 8:07 [PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework Padmavathi Venna
@ 2013-06-12 8:07 ` Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 2/6] clk: samsung: register audio subsystem clocks using common clock framework Padmavathi Venna
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Padmavathi Venna @ 2013-06-12 8:07 UTC (permalink / raw)
To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
alsa-devel, padma.v, padma.kvr
Cc: sbkim73, broonie, kgene.kim, mturquette
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
---
arch/arm/boot/dts/exynos4.dtsi | 2 +-
arch/arm/boot/dts/exynos4210-origen.dts | 2 +-
arch/arm/boot/dts/exynos4210-smdkv310.dts | 2 +-
arch/arm/boot/dts/exynos4210-trats.dts | 2 +-
arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 +-
arch/arm/boot/dts/exynos4210.dtsi | 4 ++--
arch/arm/boot/dts/exynos4212.dtsi | 2 +-
arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +-
arch/arm/boot/dts/exynos4412-origen.dts | 2 +-
arch/arm/boot/dts/exynos4412-smdk4412.dts | 2 +-
arch/arm/boot/dts/exynos4412.dtsi | 2 +-
arch/arm/boot/dts/exynos4x12.dtsi | 4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts | 2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 +-
arch/arm/boot/dts/exynos5250-snow.dts | 4 ++--
arch/arm/boot/dts/exynos5250.dtsi | 4 ++--
arch/arm/boot/dts/exynos5440-sd5v1.dts | 2 +-
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 2 +-
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
arch/arm/boot/dts/s3c2416-smdk2416.dts | 2 +-
arch/arm/boot/dts/s3c2416.dtsi | 4 ++--
arch/arm/boot/dts/s3c24xx.dtsi | 2 +-
22 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
/ {
model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
/ {
model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
/ {
model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
/ {
model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index d4f8067..b7f358a 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
-/include/ "exynos4.dtsi"
-/include/ "exynos4210-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
/ {
compatible = "samsung,exynos4210";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 867d945..46c678e 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
/ {
model = "Hardkernel ODROID-X board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index ca73c42..7993641 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
/ {
model = "Insignal Origen evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index a8ba195..ad316a1 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
/ {
model = "Samsung SMDK evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389..e743e67 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 35cb209..01da194 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
* published by the Free Software Foundation.
*/
-/include/ "exynos4.dtsi"
-/include/ "exynos4x12-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
/ {
aliases {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index c371f7c..5618131 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
*/
/dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index d53ea34..da7adbf 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
*/
/dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
/ {
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb..fd711e2 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
*/
/dts-v1/;
-/include/ "exynos5250.dtsi"
-/include/ "cros5250-common.dtsi"
+#include "exynos5250.dtsi"
+#include "cros5250-common.dtsi"
/ {
model = "Google Snow";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 8b1f9b6..5cfc5b7 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,8 +17,8 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
-/include/ "exynos5250-pinctrl.dtsi"
+#include "skeleton.dtsi"
+#include "exynos5250-pinctrl.dtsi"
/ {
compatible = "samsung,exynos5250";
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b5..5e84c5f 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,7 +10,7 @@
*/
/dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
/ {
model = "SAMSUNG SD5v1 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..2fd6646 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,7 +10,7 @@
*/
/dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
/ {
model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9fd7884..b41ad45 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,7 +9,7 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "samsung,exynos5440";
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index ad1dd09..59594cf 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -9,7 +9,7 @@
*/
/dts-v1/;
-/include/ "s3c2416.dtsi"
+#include "s3c2416.dtsi"
/ {
model = "SMDK2416";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 6809324..e6555bd 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,8 +8,8 @@
* published by the Free Software Foundation.
*/
-/include/ "s3c24xx.dtsi"
-/include/ "s3c2416-pinctrl.dtsi"
+#include "s3c24xx.dtsi"
+#include "s3c2416-pinctrl.dtsi"
/ {
model = "Samsung S3C2416 SoC";
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
index cab46ff..2d1d7dc 100644
--- a/arch/arm/boot/dts/s3c24xx.dtsi
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "samsung,s3c24xx";
--
1.7.4.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH V6 2/6] clk: samsung: register audio subsystem clocks using common clock framework
2013-06-12 8:07 [PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 1/6] ARM: samsung: use #include for all device trees Padmavathi Venna
@ 2013-06-12 8:07 ` Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 3/6] ARM: dts: add Exynos audio subsystem clock controller node Padmavathi Venna
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Padmavathi Venna @ 2013-06-12 8:07 UTC (permalink / raw)
To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
alsa-devel, padma.v, padma.kvr
Cc: sbkim73, broonie, kgene.kim, mturquette
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++++++++++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos-audss.c | 133 ++++++++++++++++++++
include/dt-bindings/clk/exynos-audss-clk.h | 25 ++++
4 files changed, 223 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 0000000..a120180
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+ - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
+ - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock ID SoC (if specific)
+-----------------------------------------------
+
+mout_audss 0
+mout_i2s 1
+dout_srp 2
+dout_aud_bus 3
+dout_i2s 4
+srp_clk 5
+i2s_bus 6
+sclk_i2s 7
+pcm_bus 8
+sclk_pcm 9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller@3810000 {
+ compatible = "samsung,exynos5250-audss-clock";
+ reg = <0x03810000 0x0C>;
+ #clock-cells = <1>;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+i2s0: i2s@03830000 {
+ compatible = "samsung,i2s-v5";
+ reg = <0x03830000 0x100>;
+ dmas = <&pdma0 10
+ &pdma0 9
+ &pdma0 8>;
+ dma-names = "tx", "rx", "tx-sec";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
+ "mout_audss", "mout_i2s";
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..1876810 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 0000000..9b1bbd5
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
+static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_audss_clk_suspend(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+ reg_save[i][1] = readl(reg_base + reg_save[i][0]);
+
+ return 0;
+}
+
+static void exynos_audss_clk_resume(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+ writel(reg_save[i][1], reg_base + reg_save[i][0]);
+}
+
+static struct syscore_ops exynos_audss_clk_syscore_ops = {
+ .suspend = exynos_audss_clk_suspend,
+ .resume = exynos_audss_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* register exynos_audss clocks */
+void __init exynos_audss_clk_init(struct device_node *np)
+{
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: failed to map audss registers\n", __func__);
+ return;
+ }
+
+ clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ GFP_KERNEL);
+ if (!clk_table) {
+ pr_err("%s: could not allocate clk lookup table\n", __func__);
+ return;
+ }
+
+ clk_data.clks = clk_table;
+ clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+ clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+ mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
+ reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+
+ clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+ mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
+ reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
+
+ clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+ "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
+ 0, &lock);
+
+ clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
+ "dout_aud_bus", "dout_srp", 0,
+ reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
+
+ clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+ "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
+ &lock);
+
+ clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+ "dout_srp", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 0, 0, &lock);
+
+ clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+ "dout_aud_bus", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 2, 0, &lock);
+
+ clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+ "dout_i2s", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 3, 0, &lock);
+
+ clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+ "sclk_pcm", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 4, 0, &lock);
+
+ clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+ "div_pcm0", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 5, 0, &lock);
+
+#ifdef CONFIG_PM_SLEEP
+ register_syscore_ops(&exynos_audss_clk_syscore_ops);
+#endif
+
+ pr_info("Exynos: Audss: clock setup completed\n");
+}
+CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
+ exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
+ exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
new file mode 100644
index 0000000..8279f42
--- /dev/null
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS 0
+#define EXYNOS_MOUT_I2S 1
+#define EXYNOS_DOUT_SRP 2
+#define EXYNOS_DOUT_AUD_BUS 3
+#define EXYNOS_DOUT_I2S 4
+#define EXYNOS_SRP_CLK 5
+#define EXYNOS_I2S_BUS 6
+#define EXYNOS_SCLK_I2S 7
+#define EXYNOS_PCM_BUS 8
+#define EXYNOS_SCLK_PCM 9
+
+#define EXYNOS_AUDSS_MAX_CLKS 10
+
+#endif
--
1.7.4.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH V6 3/6] ARM: dts: add Exynos audio subsystem clock controller node
2013-06-12 8:07 [PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 1/6] ARM: samsung: use #include for all device trees Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 2/6] clk: samsung: register audio subsystem clocks using common clock framework Padmavathi Venna
@ 2013-06-12 8:07 ` Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 4/6] ARM: dts: add clock provider information for i2s controllers in Exynos5250 Padmavathi Venna
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Padmavathi Venna @ 2013-06-12 8:07 UTC (permalink / raw)
To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
alsa-devel, padma.v, padma.kvr
Cc: sbkim73, broonie, kgene.kim, mturquette
Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
---
arch/arm/boot/dts/exynos5250.dtsi | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 5cfc5b7..84edf42 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
#clock-cells = <1>;
};
+ clock_audss: audss-clock-controller@3810000 {
+ compatible = "samsung,exynos5250-audss-clock";
+ reg = <0x03810000 0x0C>;
+ #clock-cells = <1>;
+ };
+
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
--
1.7.4.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH V6 4/6] ARM: dts: add clock provider information for i2s controllers in Exynos5250
2013-06-12 8:07 [PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework Padmavathi Venna
` (2 preceding siblings ...)
2013-06-12 8:07 ` [PATCH V6 3/6] ARM: dts: add Exynos audio subsystem clock controller node Padmavathi Venna
@ 2013-06-12 8:07 ` Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 5/6] ARM: dts: Update Samsung I2S documentation Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 Padmavathi Venna
5 siblings, 0 replies; 12+ messages in thread
From: Padmavathi Venna @ 2013-06-12 8:07 UTC (permalink / raw)
To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
alsa-devel, padma.v, padma.kvr
Cc: sbkim73, broonie, kgene.kim, mturquette
Add clock lookup information for i2s controllers on exynos5250 SoC.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 84edf42..0aa9091 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
#include "skeleton.dtsi"
#include "exynos5250-pinctrl.dtsi"
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
/ {
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
@@ -457,6 +459,10 @@
&pdma0 9
&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
@@ -471,6 +477,8 @@
dmas = <&pdma1 12
&pdma1 11>;
dma-names = "tx", "rx";
+ clocks = <&clock 307>, <&clock 157>;
+ clock-names = "iis", "i2s_opclk0";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
};
@@ -481,6 +489,8 @@
dmas = <&pdma0 12
&pdma0 11>;
dma-names = "tx", "rx";
+ clocks = <&clock 308>, <&clock 158>;
+ clock-names = "iis", "i2s_opclk0";
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
};
--
1.7.4.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH V6 5/6] ARM: dts: Update Samsung I2S documentation
2013-06-12 8:07 [PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework Padmavathi Venna
` (3 preceding siblings ...)
2013-06-12 8:07 ` [PATCH V6 4/6] ARM: dts: add clock provider information for i2s controllers in Exynos5250 Padmavathi Venna
@ 2013-06-12 8:07 ` Padmavathi Venna
2013-06-12 8:07 ` [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 Padmavathi Venna
5 siblings, 0 replies; 12+ messages in thread
From: Padmavathi Venna @ 2013-06-12 8:07 UTC (permalink / raw)
To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
alsa-devel, padma.v, padma.kvr
Cc: sbkim73, broonie, kgene.kim, mturquette
This patch updates the samsung i2s documentation for pinmux and
clock entries.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
.../devicetree/bindings/sound/samsung-i2s.txt | 46 ++++++++-----------
1 files changed, 19 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046..025e66b 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,16 @@ Required SoC Specific Properties:
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
- dma-names: identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
+- clocks: Handle to iis clock and RCLK source clk.
+- clock-names:
+ i2s0 uses some base clks from CMU and some are from audio subsystem internal
+ clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
+ "i2s_opclk1" as shown in the example below.
+ i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
+ be "iis" and "i2s_opclk0".
+ "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
+ clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
+ doesn't have any such mux.
Optional SoC Specific Properties:
@@ -20,44 +30,26 @@ Optional SoC Specific Properties:
then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
-
-Required Board Specific Properties:
-
-- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
- interface lines. The format of the gpio specifier depends on the gpio
- controller.
- The syntax of samsung gpio specifier is
- <[phandle of the gpio controller node]
- [pin number within the gpio controller]
- [mux function]
- [flags and pull up/down]
- [drive strength]>
+- pinctrl-0: Should specify pin control groups used for this controller.
+- pinctrl-names: Should contain only one value - "default".
Example:
-- SoC Specific Portion:
-
-i2s@03830000 {
+i2s0: i2s@03830000 {
compatible = "samsung,i2s-v5";
reg = <0x03830000 0x100>;
dmas = <&pdma0 10
&pdma0 9
&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
samsung,idma-addr = <0x03000000>;
-};
-
-- Board Specific Portion:
-
-i2s@03830000 {
- gpios = <&gpz 0 2 0 0>, /* I2S_0_SCLK */
- <&gpz 1 2 0 0>, /* I2S_0_CDCLK */
- <&gpz 2 2 0 0>, /* I2S_0_LRCK */
- <&gpz 3 2 0 0>, /* I2S_0_SDI */
- <&gpz 4 2 0 0>, /* I2S_0_SDO[1] */
- <&gpz 5 2 0 0>, /* I2S_0_SDO[2] */
- <&gpz 6 2 0 0>; /* I2S_0_SDO[3] */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_bus>;
};
--
1.7.4.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
2013-06-12 8:07 [PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework Padmavathi Venna
` (4 preceding siblings ...)
2013-06-12 8:07 ` [PATCH V6 5/6] ARM: dts: Update Samsung I2S documentation Padmavathi Venna
@ 2013-06-12 8:07 ` Padmavathi Venna
2013-06-12 16:45 ` Mike Turquette
5 siblings, 1 reply; 12+ messages in thread
From: Padmavathi Venna @ 2013-06-12 8:07 UTC (permalink / raw)
To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
alsa-devel, padma.v, padma.kvr
Cc: sbkim73, broonie, kgene.kim, mturquette
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
drivers/clk/samsung/clk-exynos5250.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..7c68850 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -87,6 +87,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+ div_i2s1, div_i2s2,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
- DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
- DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
+ DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
+ DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
DIV_F(none, "div_mipi1_pre", "div_mipi1",
--
1.7.4.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
2013-06-12 8:07 ` [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 Padmavathi Venna
@ 2013-06-12 16:45 ` Mike Turquette
2013-06-13 3:02 ` Padma Venkat
0 siblings, 1 reply; 12+ messages in thread
From: Mike Turquette @ 2013-06-12 16:45 UTC (permalink / raw)
To: Padmavathi Venna, linux-samsung-soc, devicetree-discuss,
linux-arm-kernel, alsa-devel
Cc: sbkim73, broonie, kgene.kim
Quoting Padmavathi Venna (2013-06-12 01:07:43)
> This patch adds enum entries for div_i2s1 and div_i2s2 which are
> required for i2s1 and i2s2 controllers.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Looks good. Did you want me to take the clk patches or just gathering
Acks?
Regards,
Mike
> ---
> drivers/clk/samsung/clk-exynos5250.c | 5 +++--
> 1 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 5c97e75..7c68850 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -87,6 +87,7 @@ enum exynos5250_clks {
> sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
> sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
> sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
> + div_i2s1, div_i2s2,
>
> /* gate clocks */
> gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
> @@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
> DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
> DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
> DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
> - DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
> - DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
> + DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
> + DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
> DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
> DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
> DIV_F(none, "div_mipi1_pre", "div_mipi1",
> --
> 1.7.4.4
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
2013-06-12 16:45 ` Mike Turquette
@ 2013-06-13 3:02 ` Padma Venkat
2013-06-17 4:59 ` Padma Venkat
0 siblings, 1 reply; 12+ messages in thread
From: Padma Venkat @ 2013-06-13 3:02 UTC (permalink / raw)
To: Mike Turquette
Cc: Padmavathi Venna, linux-samsung-soc, devicetree-discuss,
linux-arm-kernel, alsa-devel, sbkim73, broonie, kgene.kim
Hi Mike,
On Wed, Jun 12, 2013 at 10:15 PM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Padmavathi Venna (2013-06-12 01:07:43)
>> This patch adds enum entries for div_i2s1 and div_i2s2 which are
>> required for i2s1 and i2s2 controllers.
>>
>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
>
> Looks good. Did you want me to take the clk patches or just gathering
> Acks?
Please take the patches :).
Thanks
Padma
>
> Regards,
> Mike
>
>> ---
>> drivers/clk/samsung/clk-exynos5250.c | 5 +++--
>> 1 files changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>> index 5c97e75..7c68850 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>> @@ -87,6 +87,7 @@ enum exynos5250_clks {
>> sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
>> sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
>> sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
>> + div_i2s1, div_i2s2,
>>
>> /* gate clocks */
>> gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
>> @@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
>> DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
>> DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
>> DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
>> - DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
>> - DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
>> + DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
>> + DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
>> DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
>> DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
>> DIV_F(none, "div_mipi1_pre", "div_mipi1",
>> --
>> 1.7.4.4
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
2013-06-13 3:02 ` Padma Venkat
@ 2013-06-17 4:59 ` Padma Venkat
2013-06-17 10:15 ` Kukjin Kim
0 siblings, 1 reply; 12+ messages in thread
From: Padma Venkat @ 2013-06-17 4:59 UTC (permalink / raw)
To: Mike Turquette
Cc: Padmavathi Venna, linux-samsung-soc, devicetree-discuss,
linux-arm-kernel, alsa-devel, sbkim73, broonie, kgene.kim
Hi Mike,
On Thu, Jun 13, 2013 at 8:32 AM, Padma Venkat <padma.kvr@gmail.com> wrote:
> Hi Mike,
>
> On Wed, Jun 12, 2013 at 10:15 PM, Mike Turquette <mturquette@linaro.org> wrote:
>> Quoting Padmavathi Venna (2013-06-12 01:07:43)
>>> This patch adds enum entries for div_i2s1 and div_i2s2 which are
>>> required for i2s1 and i2s2 controllers.
>>>
>>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
>>
>> Looks good. Did you want me to take the clk patches or just gathering
>> Acks?
>
> Please take the patches :).
>
> Thanks
> Padma
clk related patches in this set has some dependency on arch side
patches because one of the patch replaces all '/include's with
'#include's and adds a header file in
arch/arm/boot/include/dt-bindings/. So all these patches required to
go into one tree.
Hi Kukjin,
Can you please take all these patches into samsung-tree?
Thanks
Padma
>
>>
>> Regards,
>> Mike
>>
>>> ---
>>> drivers/clk/samsung/clk-exynos5250.c | 5 +++--
>>> 1 files changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>>> index 5c97e75..7c68850 100644
>>> --- a/drivers/clk/samsung/clk-exynos5250.c
>>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>>> @@ -87,6 +87,7 @@ enum exynos5250_clks {
>>> sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
>>> sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
>>> sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
>>> + div_i2s1, div_i2s2,
>>>
>>> /* gate clocks */
>>> gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
>>> @@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
>>> DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
>>> DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
>>> DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
>>> - DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
>>> - DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
>>> + DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
>>> + DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
>>> DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
>>> DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
>>> DIV_F(none, "div_mipi1_pre", "div_mipi1",
>>> --
>>> 1.7.4.4
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
2013-06-17 4:59 ` Padma Venkat
@ 2013-06-17 10:15 ` Kukjin Kim
2013-06-21 6:54 ` Mike Turquette
0 siblings, 1 reply; 12+ messages in thread
From: Kukjin Kim @ 2013-06-17 10:15 UTC (permalink / raw)
To: 'Padma Venkat', 'Mike Turquette'
Cc: 'Padmavathi Venna', linux-samsung-soc, devicetree-discuss,
linux-arm-kernel, alsa-devel, sbkim73, broonie
Padma Venkat wrote:
>
> Hi Mike,
>
> On Thu, Jun 13, 2013 at 8:32 AM, Padma Venkat <padma.kvr@gmail.com> wrote:
> > Hi Mike,
> >
> > On Wed, Jun 12, 2013 at 10:15 PM, Mike Turquette <mturquette@linaro.org>
> wrote:
> >> Quoting Padmavathi Venna (2013-06-12 01:07:43)
> >>> This patch adds enum entries for div_i2s1 and div_i2s2 which are
> >>> required for i2s1 and i2s2 controllers.
> >>>
> >>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> >>
> >> Looks good. Did you want me to take the clk patches or just gathering
> >> Acks?
> >
> > Please take the patches :).
> >
> > Thanks
> > Padma
>
> clk related patches in this set has some dependency on arch side
> patches because one of the patch replaces all '/include's with
> '#include's and adds a header file in
> arch/arm/boot/include/dt-bindings/. So all these patches required to
> go into one tree.
>
> Hi Kukjin,
>
> Can you please take all these patches into samsung-tree?
>
Padma, sure, I will.
BTW, Mike, according to your reply, I may get your ack on 2nd and 6th clk
patches...If any problems, please kindly let me know.
Thanks,
- Kukjin
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: RE: [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
2013-06-17 10:15 ` Kukjin Kim
@ 2013-06-21 6:54 ` Mike Turquette
0 siblings, 0 replies; 12+ messages in thread
From: Mike Turquette @ 2013-06-21 6:54 UTC (permalink / raw)
To: Kukjin Kim, 'Padma Venkat'
Cc: 'Padmavathi Venna', linux-samsung-soc, devicetree-discuss,
linux-arm-kernel, alsa-devel, sbkim73, broonie
Quoting Kukjin Kim (2013-06-17 03:15:27)
> Padma Venkat wrote:
> >
> > Hi Mike,
> >
> > On Thu, Jun 13, 2013 at 8:32 AM, Padma Venkat <padma.kvr@gmail.com> wrote:
> > > Hi Mike,
> > >
> > > On Wed, Jun 12, 2013 at 10:15 PM, Mike Turquette <mturquette@linaro.org>
> > wrote:
> > >> Quoting Padmavathi Venna (2013-06-12 01:07:43)
> > >>> This patch adds enum entries for div_i2s1 and div_i2s2 which are
> > >>> required for i2s1 and i2s2 controllers.
> > >>>
> > >>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> > >>
> > >> Looks good. Did you want me to take the clk patches or just gathering
> > >> Acks?
> > >
> > > Please take the patches :).
> > >
> > > Thanks
> > > Padma
> >
> > clk related patches in this set has some dependency on arch side
> > patches because one of the patch replaces all '/include's with
> > '#include's and adds a header file in
> > arch/arm/boot/include/dt-bindings/. So all these patches required to
> > go into one tree.
> >
> > Hi Kukjin,
> >
> > Can you please take all these patches into samsung-tree?
> >
> Padma, sure, I will.
>
> BTW, Mike, according to your reply, I may get your ack on 2nd and 6th clk
> patches...If any problems, please kindly let me know.
Fine by me.
Regards,
Mike
>
> Thanks,
> - Kukjin
^ permalink raw reply [flat|nested] 12+ messages in thread