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From: Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
To: Ezequiel Garcia
	<ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>,
	Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
	devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
	Maen Suleiman <maen-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
	Lior Amsalem <alior-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	Sebastian Hesselbarth
	<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
Date: Fri, 5 Jul 2013 16:08:20 -0600	[thread overview]
Message-ID: <20130705220820.GA11787@obsidianresearch.com> (raw)
In-Reply-To: <1373060372-32357-1-git-send-email-ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

On Fri, Jul 05, 2013 at 06:39:11PM -0300, Ezequiel Garcia wrote:
 
> 			ranges =
> 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
> 				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
> 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
> 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
> 				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
> 				0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
> 				0x81000800 0 0          MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;

This is a good try, but this coding doesn't work...

Recall the long discussion that came up during the original
development of this binding. The OF spec says this:

 In particular, the phys.hi fields of the child address spaces in the
 "ranges" property for PCI does not contain
 the same information as "reg" property entries within PCI nodes. The
 only information that is present in
 "ranges" phys.hi entries are the non-relocatable, prefetchable and
 the PCI address space bits for which the en-
 try applies. I.e., only the n, p and ss bits are present; the
 bbbbbbbb, ddddd, fff and rrrrrrrr fields are 0.

 When an address is to be mapped through a PCI bus bridge node, the
 phys.hi value of the address to be mapped
 and the child field of a "ranges" entry should be masked so that only
 the ss bits are compared. I.e., the only
 portion of phys.hi that should participate in the range determination
 is the address space indicator (the ss bits).

Which forbids (0x82000800 .. ..) from being in a ranges

I don't have an idea how to encode MBUS_ID in the PCI-E ranges :(

Arnd? Didn't you have some idea?

FWIW, I like removing the string tables from the driver, you could
keep the fake MBUS-ID and retain that change by adding a
marvell,target-id type property to the bridges...

Jason

  parent reply	other threads:[~2013-07-05 22:08 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-05 21:39 [PATCH v6 00/21] MBus DT binding: PCIe strikes back Ezequiel Garcia
     [not found] ` <1373060372-32357-1-git-send-email-ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2013-07-05 21:39   ` [PATCH v6 01/21] memory: mvebu-devbus: Remove address decoding window workaround Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 02/21] bus: mvebu-mbus: Add new API for window creation Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 03/21] ARM: kirkwood: Move to ID based MBus " Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 04/21] ARM: mv78xx0: Move to ID based " Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 05/21] ARM: orion5x: " Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 06/21] ARM: dove: " Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 07/21] bus: mvebu-mbus: Factor out initialization details Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 08/21] bus: mvebu-mbus: Introduce device tree binding Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 09/21] bus: mvebu-mbus: Add static window allocation to the binding Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 10/21] pci: mvebu: Adapt to the new device tree layout Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 11/21] bus: mvebu-mbus: Remove the no longer used name-based API Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 12/21] bus: mvebu-mbus: Remove name -> target, attribute mapping tables Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 13/21] bus: mvebu-mbus: Update main description Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 14/21] bus: mvebu-mbus: Factorize Armada 370/XP data structures Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 15/21] ARM: mvebu: Remove the harcoded BootROM window allocation Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 16/21] ARM: mvebu: Initialize MBus using the DT binding Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 17/21] ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 18/21] ARM: mvebu: Add MBus to Armada 370/XP device tree Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 19/21] ARM: mvebu: Add BootROM " Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 20/21] ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes Ezequiel Garcia
2013-07-05 21:39   ` [PATCH v6 21/21] ARM: mvebu: Relocate Armada 370/XP PCIe " Ezequiel Garcia
2013-07-05 22:08   ` Jason Gunthorpe [this message]
     [not found]     ` <20130705220820.GA11787-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2013-07-05 22:37       ` [PATCH v6 00/21] MBus DT binding: PCIe strikes back Thomas Petazzoni
2013-07-05 22:54       ` Arnd Bergmann
2013-07-05 23:35   ` Thomas Petazzoni
2013-07-05 23:38     ` Arnd Bergmann
     [not found]       ` <201307060138.36191.arnd-r2nGTMty4D4@public.gmane.org>
2013-07-08 16:42         ` Jason Gunthorpe
     [not found]           ` <20130708164225.GA26618-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2013-07-08 19:52             ` Ezequiel Garcia
2013-07-05 22:40 ` Arnd Bergmann

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