Re: [RFC v1 0/5] ARM: Initial support for Marvell Armada 1500

Re: [RFC v1 0/5] ARM: Initial support for Marvell Armada 1500

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Fri, 16 Aug 2013 21:41:33 +0200, Sebastian Hesselbarth wrote:
> This is a RFC adding initial support for the Marvell Armada 1500
> (88DE3100) found on various consumer devices (Chromecast, GoogleTV).
> 
> Actually, it is a two-fold RFC also raising discussions on mach-mvebu
> cleanup roadmap to allow other SoCs to hop into it. While mach-mvebu
> originally was created to add support for Armada 370/XP and merge
> existing Marvell Orion familiy into it, I am not so sure about
> Armada 1500 fits that well (the mbus has gone!).

After talking a bit with engineers within Marvell that work on this
SoC, I'm inclined to think that using mach-mvebu for this family of SoC
is not a good idea.

The reasons are:

 * This family of SoC is architecturally completely different from the
   family of Orion SoC: they use completely different hardware blocks
   (i.e none of the plat-orion stuff would apply, and none of the
   Orion device drivers would be useful), they don't use the MBus
   mechanism, etc. They are really a different family of SoC, almost as
   if they were coming from a different SoC company.

 * The SMP and power management code, as well as all the "glue"
   platform code that typically sits in mach-<foo> is going to be
   substantially, if not completely different from the one in
   mach-mvebu. I already believe doing all the "glue" platform code in
   mach-mvebu for all of Kirkwood, Dove, 370/XP, Orion5x and MV78xx0 is
   going to be a challenge, so I'd suggest to not add to this challenge
   a completely separate family of SOCs.

The codename used for those Armada 1500 SOCs is "Berlin", so a name
like mach-berlin, or mach-mvberlin (if we want to keep 'mv' to identify
the founder) seems like a good name.

Also, to help us understand the organization of the family of SOCs, I
asked a few informations to Marvell, and here is what I could collect:

"""
BGxname		CPU core	codename	L2 cache controller	internal name
BG2		PJ4B		Armada1500	Tauros3			MV88DE3100
BG2-CT		Cortex-A9	N/A		PL310			N/A
BG3		Cortex-A15	N/A		CA15 integrated		N/A
"""

As was told that the Armada X or MV88DEx names are not used during
development, and what Marvell is really using are the BGxx names.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [RFC v1 0/5] ARM: Initial support for Marvell Armada 1500

[Sebastian Hesselbarth]

On 08/27/13 16:19, Thomas Petazzoni wrote:
> On Fri, 16 Aug 2013 21:41:33 +0200, Sebastian Hesselbarth wrote:
>> This is a RFC adding initial support for the Marvell Armada 1500
>> (88DE3100) found on various consumer devices (Chromecast, GoogleTV).
>>
>> Actually, it is a two-fold RFC also raising discussions on mach-mvebu
>> cleanup roadmap to allow other SoCs to hop into it. While mach-mvebu
>> originally was created to add support for Armada 370/XP and merge
>> existing Marvell Orion familiy into it, I am not so sure about
>> Armada 1500 fits that well (the mbus has gone!).
>
> After talking a bit with engineers within Marvell that work on this
> SoC, I'm inclined to think that using mach-mvebu for this family of SoC
> is not a good idea.

Thomas,

thanks for the info below. Reading a little bit through the GPL'ed
source, I also quickly came to the same conclusion. It is more likely
we can reuse some stuff from other SoCs than Orion or Armada 370/XP.

> The reasons are:
>
>   * This family of SoC is architecturally completely different from the
>     family of Orion SoC: they use completely different hardware blocks
>     (i.e none of the plat-orion stuff would apply, and none of the
>     Orion device drivers would be useful), they don't use the MBus
>     mechanism, etc. They are really a different family of SoC, almost as
>     if they were coming from a different SoC company.
>
>   * The SMP and power management code, as well as all the "glue"
>     platform code that typically sits in mach-<foo> is going to be
>     substantially, if not completely different from the one in
>     mach-mvebu. I already believe doing all the "glue" platform code in
>     mach-mvebu for all of Kirkwood, Dove, 370/XP, Orion5x and MV78xx0 is
>     going to be a challenge, so I'd suggest to not add to this challenge
>     a completely separate family of SOCs.
>
> The codename used for those Armada 1500 SOCs is "Berlin", so a name
> like mach-berlin, or mach-mvberlin (if we want to keep 'mv' to identify
> the founder) seems like a good name.

I have already moved it under mach-mv88de3xxx as for now, all SoCs
Marvell is providing as DE (Digital Entertainment) fit in that. I like
mach-codename style more than plain numbers, maybe I rename the folder
to mach-berlin before posting.

Speaking of "berlin", they found a 2WW bomb in my home town center today
and are evacuating apartments. Mine too, so it looks like I'll have
some time to prepare v2 tonight..

> Also, to help us understand the organization of the family of SOCs, I
> asked a few informations to Marvell, and here is what I could collect:
>
> """
> BGxname		CPU core	codename	L2 cache controller	internal name
> BG2		PJ4B		Armada1500	Tauros3			MV88DE3100
> BG2-CT		Cortex-A9	N/A		PL310			N/A
> BG3		Cortex-A15	N/A		CA15 integrated		N/A
> """
>
> As was told that the Armada X or MV88DEx names are not used during
> development, and what Marvell is really using are the BGxx names.

Ok, I'll add that info to Marvell SoC documentation also.

Sebastian

Re: [RFC v1 0/5] ARM: Initial support for Marvell Armada 1500

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Tue, 27 Aug 2013 18:45:45 +0200, Sebastian Hesselbarth wrote:

> > After talking a bit with engineers within Marvell that work on this
> > SoC, I'm inclined to think that using mach-mvebu for this family of SoC
> > is not a good idea.
> 
> Thomas,
> 
> thanks for the info below. Reading a little bit through the GPL'ed
> source, I also quickly came to the same conclusion. It is more likely
> we can reuse some stuff from other SoCs than Orion or Armada 370/XP.

Yes, many of the IP blocks are for example DesignWare IPs, or ARM IPs
in the case of the Cortex-A based variants.

> > The codename used for those Armada 1500 SOCs is "Berlin", so a name
> > like mach-berlin, or mach-mvberlin (if we want to keep 'mv' to identify
> > the founder) seems like a good name.
> 
> I have already moved it under mach-mv88de3xxx as for now, all SoCs
> Marvell is providing as DE (Digital Entertainment) fit in that. I like
> mach-codename style more than plain numbers, maybe I rename the folder
> to mach-berlin before posting.

I also like mach-berlin a bit more than mach-mve88de3xxx, for a very
silly reason: when during a discussion you have to say mach-mv88de3xxx,
it's pretty annoying. We already have the horrible mach-mv78xx0, let's
not add more of this :)

> Speaking of "berlin", they found a 2WW bomb in my home town center today
> and are evacuating apartments. Mine too, so it looks like I'll have
> some time to prepare v2 tonight..

Doh!

> > Also, to help us understand the organization of the family of SOCs, I
> > asked a few informations to Marvell, and here is what I could collect:
> >
> > """
> > BGxname		CPU core	codename	L2 cache controller	internal name
> > BG2		PJ4B		Armada1500	Tauros3			MV88DE3100
> > BG2-CT		Cortex-A9	N/A		PL310			N/A
> > BG3		Cortex-A15	N/A		CA15 integrated		N/A
> > """
> >
> > As was told that the Armada X or MV88DEx names are not used during
> > development, and what Marvell is really using are the BGxx names.
> 
> Ok, I'll add that info to Marvell SoC documentation also.

That'd be nice indeed.

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [RFC v1 0/5] ARM: Initial support for Marvell Armada 1500

[Arnd Bergmann]

On Tuesday 27 August 2013 16:19:58 Thomas Petazzoni wrote:
> 
> Also, to help us understand the organization of the family of SOCs, I
> asked a few informations to Marvell, and here is what I could collect:
> 
> """
> BGxname         CPU core        codename        L2 cache controller     internal name
> BG2             PJ4B            Armada1500      Tauros3                 MV88DE3100
> BG2-CT          Cortex-A9       N/A             PL310                   N/A
> BG3             Cortex-A15      N/A             CA15 integrated         N/A
> """

My guess is that BG2-CT is Armada1500-mini aka MV88DE3005, i.e. the chip
used in the chromecast.
At least that is what gets used in the chromecast kernel sources, but it's
also possible that there are UP and SMP versions of BG2-CT and that
DE3005 is only the former.

	Arnd

[PATCH RFC v2 1/6] irqchip: add DesignWare APB ICTL interrupt controller

[Sebastian Hesselbarth]

This adds an irqchip driver and corresponding devicetree binding for the
secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- added copyright reference

Note:
The driver has been sent as a separate patch before, I decided to take it
back into the RFC. There is no other platform using it yet and this way I
can track all changes. Sorry for the noise caused by the individual patch.

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../interrupt-controller/snps,dw-apb-ictl.txt      |   29 ++++
 drivers/irqchip/Kconfig                            |    4 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-dw-apb-ictl.c                  |  142 ++++++++++++++++++++
 4 files changed, 176 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
 create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
new file mode 100644
index 0000000..7ccd1ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -0,0 +1,29 @@
+Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
+
+Synopsys DesignWare provides interrupt controller IP for APB known as
+dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
+APB bus, e.g. Marvell Armada 1500.
+
+Required properties:
+- compatible: shall be "snps,dw-apb-ictl"
+- reg: base address of interrupt registers starting with ENABLE_LOW register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
+- interrupts: interrupt reference to primary interrupt controller
+- interrupt-parent: (optional) reference specific primary interrupt controller
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of low interrupts,
+- 1 maps to bit 1 of low interrupts,
+- 32 maps to bit 0 of high interrupts, and so on.
+
+Example:
+	aic: interrupt-controller@3000 {
+		compatible = "snps,dw-apb-ictl";
+		reg = <0x3000 0xc00>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+	};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..940638d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,10 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config DW_APB_ICTL
+	bool
+	select IRQ_DOMAIN
+
 config IMGPDC_IRQ
 	bool
 	select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 81e8cd4..e5bfb19 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
 obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o
 obj-$(CONFIG_ARM_VIC)			+= irq-vic.o
+obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
 obj-$(CONFIG_IMGPDC_IRQ)		+= irq-imgpdc.o
 obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
new file mode 100644
index 0000000..bbcacee
--- /dev/null
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -0,0 +1,142 @@
+/*
+ * Synopsys DW APB ICTL irqchip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irqchip.h"
+
+#define APB_INT_ENABLE_L	0x00
+#define APB_INT_ENABLE_H	0x04
+#define APB_INT_MASK_L		0x08
+#define APB_INT_MASK_H		0x0c
+#define APB_INT_FINALSTATUS_L	0x30
+#define APB_INT_FINALSTATUS_H	0x34
+
+static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct irq_chip_generic *gc = irq_get_handler_data(irq);
+	struct irq_domain *d = gc->private;
+	u32 stat;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	for (n = 0; n < gc->num_ct; n++) {
+		stat = readl_relaxed(gc->reg_base +
+				     APB_INT_FINALSTATUS_L + 4 * n);
+		while (stat) {
+			u32 hwirq = ffs(stat) - 1;
+			generic_handle_irq(irq_find_mapping(d,
+					    gc->irq_base + hwirq + 32 * n));
+			stat &= ~(1 << hwirq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int __init dw_apb_ictl_init(struct device_node *np,
+				   struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct resource r;
+	struct irq_domain *domain;
+	struct irq_chip_generic *gc;
+	void __iomem *iobase;
+	int ret, nrirqs, irq;
+	u32 reg;
+
+	/* Map the parent interrupt for the chained handler */
+	irq = irq_of_parse_and_map(np, 0);
+	if (irq <= 0) {
+		pr_err("%s: unable to parse irq\n", np->name);
+		return -EINVAL;
+	}
+
+	ret = of_address_to_resource(np, 0, &r);
+	if (ret) {
+		pr_err("%s: unable to get resource\n", np->name);
+		return ret;
+	}
+
+	if (!request_mem_region(r.start, resource_size(&r), np->name)) {
+		pr_err("%s: unable to request mem region\n", np->name);
+		return -ENOMEM;
+	}
+
+	iobase = ioremap(r.start, resource_size(&r));
+	if (!iobase) {
+		pr_err("%s: unable to map resource\n", np->name);
+		return -ENOMEM;
+	}
+
+	/*
+	 * DW IP can be configured to allow 2-64 irqs. We can determine
+	 * the number of irqs supported by writing into enable register
+	 * and look for bits not set, as corresponding flip-flops will
+	 * have been removed by sythesis tool.
+	 */
+
+	/* mask and enable all interrupts */
+	writel(~0, iobase + APB_INT_MASK_L);
+	writel(~0, iobase + APB_INT_MASK_H);
+	writel(~0, iobase + APB_INT_ENABLE_L);
+	writel(~0, iobase + APB_INT_ENABLE_H);
+
+	reg = readl(iobase + APB_INT_ENABLE_H);
+	if (reg)
+		nrirqs = 32 + fls(reg);
+	else
+		nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
+
+	domain = irq_domain_add_linear(np, nrirqs,
+				       &irq_generic_chip_ops, NULL);
+	if (!domain) {
+		pr_err("%s: unable to add irq domain\n", np->name);
+		return -ENOMEM;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
+					     np->name, handle_level_irq, clr, 0,
+					     IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		pr_err("%s: unable to alloc irq domain gc\n", np->name);
+		return ret;
+	}
+
+	gc = irq_get_domain_generic_chip(domain, 0);
+	gc->private = domain;
+	gc->reg_base = iobase;
+
+	gc->chip_types[0].regs.mask = APB_INT_MASK_L;
+	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+
+	if (nrirqs > 32) {
+		gc->chip_types[1].regs.mask = APB_INT_MASK_H;
+		gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
+		gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
+	}
+
+	irq_set_handler_data(irq, gc);
+	irq_set_chained_handler(irq, dw_apb_ictl_handler);
+
+	return 0;
+}
+IRQCHIP_DECLARE(dw_apb_ictl,
+		"snps,dw-apb-ictl", dw_apb_ictl_init);
-- 
1.7.2.5

[PATCH RFC v2 5/6] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

This adds very basic device tree files for the Marvell Armada 1500 SoC
(88DE3100) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
device comprising the Armada 1500 SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- add binding documentation (Reported by Jason Cooper)
- change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
- add copyright reference
- adapt compatibles to mach-berlin instead of mach-mvebu

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/arm/marvell,berlin.txt     |   23 ++
 arch/arm/boot/dts/Makefile                         |    2 +
 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts      |   29 +++
 arch/arm/boot/dts/mv88de3100.dtsi                  |  222 ++++++++++++++++++++
 4 files changed, 276 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
 create mode 100644 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
 create mode 100644 arch/arm/boot/dts/mv88de3100.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
new file mode 100644
index 0000000..a4c3056
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -0,0 +1,23 @@
+Marvell Berlin (88DE3xxx) family SoCs Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Berlin (88DE3xxx) family, e.g. Armada 1500
+shall have the following properties:
+
+* Required root node properties:
+compatible: must contain "marvell,berlin"
+
+In addition, the above compatible shall be extended with the specific
+SoC used, i.e.
+    "marvell,88de3100"	for Marvell 88DE3100 (Armada 1500),
+    "marvell,88de3010"	for Marvell 88DE3010 (Armada 1000),
+    "marvell,88de3005"	for Marvell 88DE3005 (Armada 1500-mini)
+
+* Example:
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "marvell,88de3100", "marvell,berlin";
+
+	...
+}
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d45058e..2989b51 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -43,6 +43,8 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d35ek.dtb
 
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += \
+	mv88de3100-sony-nsz-gs7.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
new file mode 100644
index 0000000..1081bc1
--- /dev/null
+++ b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Sony NSZ-GS7
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "mv88de3100.dtsi"
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,88de3100", "marvell,berlin";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk verbose debug";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1 GB */
+	};
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/mv88de3100.dtsi b/arch/arm/boot/dts/mv88de3100.dtsi
new file mode 100644
index 0000000..04328a6
--- /dev/null
+++ b/arch/arm/boot/dts/mv88de3100.dtsi
@@ -0,0 +1,222 @@
+/*
+ * Device Tree Include file for Marvell 88DE3100 (Armada 1500) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell 88DE3100 (Armada 1500) SoC";
+	compatible = "marvell,88de3100", "marvell,berlin";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "marvell,sheeva-v7";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "marvell,sheeva-v7";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		/* 25MHz reference crystal */
+		ref25: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		cfgclk: cfg-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+
+		ranges = <0 0xf7000000 0x1000000>;
+
+		l2: l2-cache-controller@ac0000 {
+			compatible = "marvell,tauros3-cache";
+			reg = <0xac0000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		gic: interrupt-controller@ad1000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xad1000 0x1000
+			       0xad0100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		local-timer@ad0600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xad0600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		apb@e80000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe80000 0x10000>;
+			interrupt-parent = <&aic>;
+
+			timer0: timer@2c00 {
+				compatible = "snps,dw-apb-timer-osc";
+				reg = <0x2c00 0x14>;
+				interrupts = <8>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer1: timer@2c14 {
+				compatible = "snps,dw-apb-timer-osc";
+				reg = <0x2c14 0x14>;
+				interrupts = <9>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer2: timer@2c28 {
+				compatible = "snps,dw-apb-timer-sp";
+				reg = <0x2c28 0x14>;
+				interrupts = <10>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer3: timer@2c3c {
+				compatible = "snps,dw-apb-timer-sp";
+				reg = <0x2c3c 0x14>;
+				interrupts = <11>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer4: timer@2c50 {
+				compatible = "snps,dw-apb-timer-sp";
+				reg = <0x2c50 0x14>;
+				interrupts = <12>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer5: timer@2c64 {
+				compatible = "snps,dw-apb-timer-sp";
+				reg = <0x2c64 0x14>;
+				interrupts = <13>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer6: timer@2c78 {
+				compatible = "snps,dw-apb-timer-sp";
+				reg = <0x2c78 0x14>;
+				interrupts = <14>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer7: timer@2c8c {
+				compatible = "snps,dw-apb-timer-sp";
+				reg = <0x2c8c 0x14>;
+				interrupts = <15>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			aic: interrupt-controller@3000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0x3000 0xc00>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		apb@fc0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xfc0000 0x10000>;
+			interrupt-parent = <&sic>;
+
+			uart0: serial@9000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x9000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <8>;
+				clock-frequency = <25000000>;
+				status = "disabled";
+			};
+
+			uart1: serial@a000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xa000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <9>;
+				clock-frequency = <25000000>;
+				status = "disabled";
+			};
+
+			uart2: serial@b000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xb000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <10>;
+				clock-frequency = <25000000>;
+				status = "disabled";
+			};
+
+			sic: interrupt-controller@e000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0xe000 0x400>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
-- 
1.7.2.5

Re: [PATCH RFC v2 5/6] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Jason Cooper]

On Wed, Aug 28, 2013 at 02:14:33AM +0200, Sebastian Hesselbarth wrote:
> This adds very basic device tree files for the Marvell Armada 1500 SoC
> (88DE3100) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
> nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
> uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
> device comprising the Armada 1500 SoC above.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> v1->v2:
> - add binding documentation (Reported by Jason Cooper)
> - change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
> - add copyright reference
> - adapt compatibles to mach-berlin instead of mach-mvebu
> 
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../devicetree/bindings/arm/marvell,berlin.txt     |   23 ++
>  arch/arm/boot/dts/Makefile                         |    2 +
>  arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts      |   29 +++
>  arch/arm/boot/dts/mv88de3100.dtsi                  |  222 ++++++++++++++++++++
>  4 files changed, 276 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>  create mode 100644 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
>  create mode 100644 arch/arm/boot/dts/mv88de3100.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> new file mode 100644
> index 0000000..a4c3056
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> @@ -0,0 +1,23 @@
> +Marvell Berlin (88DE3xxx) family SoCs Device Tree Bindings
> +---------------------------------------------------------------
> +
> +Boards with a SoC of the Marvell Berlin (88DE3xxx) family, e.g. Armada 1500
> +shall have the following properties:
> +
> +* Required root node properties:
> +compatible: must contain "marvell,berlin"
> +
> +In addition, the above compatible shall be extended with the specific
> +SoC used, i.e.
> +    "marvell,88de3100"	for Marvell 88DE3100 (Armada 1500),
> +    "marvell,88de3010"	for Marvell 88DE3010 (Armada 1000),
> +    "marvell,88de3005"	for Marvell 88DE3005 (Armada 1500-mini)
> +
> +* Example:
> +
> +/ {
> +	model = "Sony NSZ-GS7";
> +	compatible = "marvell,88de3100", "marvell,berlin";

I would make this:

	compatible = "sony,nsz-gs7", "marvell,88de3100", "marvell,berlin";

> +
> +	...
> +}
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d45058e..2989b51 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -43,6 +43,8 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d35ek.dtb
>  
>  dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
>  dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
> +dtb-$(CONFIG_ARCH_BERLIN) += \
> +	mv88de3100-sony-nsz-gs7.dtb
>  dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
>  	da850-evm.dtb
>  dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
> new file mode 100644
> index 0000000..1081bc1
> --- /dev/null
> +++ b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
> @@ -0,0 +1,29 @@
> +/*
> + * Device Tree file for Sony NSZ-GS7
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "mv88de3100.dtsi"
> +
> +/ {
> +	model = "Sony NSZ-GS7";
> +	compatible = "sony,nsz-gs7", "marvell,88de3100", "marvell,berlin";
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200 earlyprintk verbose debug";

I would remove 'verbose debug' before official submission, no point to
defaulting to log-spammer.

thx,

Jason.

Re: [PATCH RFC v2 5/6] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

On 08/28/13 14:14, Jason Cooper wrote:
> On Wed, Aug 28, 2013 at 02:14:33AM +0200, Sebastian Hesselbarth wrote:
>> This adds very basic device tree files for the Marvell Armada 1500 SoC
>> (88DE3100) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
>> nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
>> uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
>> device comprising the Armada 1500 SoC above.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> ---
>> Changelog:
>> v1->v2:
>> - add binding documentation (Reported by Jason Cooper)
>> - change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
>> - add copyright reference
>> - adapt compatibles to mach-berlin instead of mach-mvebu
>>
>> Cc: Jason Cooper <jason@lakedaemon.net>
>> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-doc@vger.kernel.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> ---
>>   .../devicetree/bindings/arm/marvell,berlin.txt     |   23 ++
>>   arch/arm/boot/dts/Makefile                         |    2 +
>>   arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts      |   29 +++
>>   arch/arm/boot/dts/mv88de3100.dtsi                  |  222 ++++++++++++++++++++
>>   4 files changed, 276 insertions(+), 0 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>>   create mode 100644 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
>>   create mode 100644 arch/arm/boot/dts/mv88de3100.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> new file mode 100644
>> index 0000000..a4c3056
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> @@ -0,0 +1,23 @@
>> +Marvell Berlin (88DE3xxx) family SoCs Device Tree Bindings
>> +---------------------------------------------------------------
>> +
>> +Boards with a SoC of the Marvell Berlin (88DE3xxx) family, e.g. Armada 1500
>> +shall have the following properties:
>> +
>> +* Required root node properties:
>> +compatible: must contain "marvell,berlin"
>> +
>> +In addition, the above compatible shall be extended with the specific
>> +SoC used, i.e.
>> +    "marvell,88de3100"	for Marvell 88DE3100 (Armada 1500),
>> +    "marvell,88de3010"	for Marvell 88DE3010 (Armada 1000),
>> +    "marvell,88de3005"	for Marvell 88DE3005 (Armada 1500-mini)
>> +
>> +* Example:
>> +
>> +/ {
>> +	model = "Sony NSZ-GS7";
>> +	compatible = "marvell,88de3100", "marvell,berlin";
>
> I would make this:
>
> 	compatible = "sony,nsz-gs7", "marvell,88de3100", "marvell,berlin";

Ok.

>> +
>> +	...
>> +}
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index d45058e..2989b51 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -43,6 +43,8 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d35ek.dtb
>>
>>   dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
>>   dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
>> +dtb-$(CONFIG_ARCH_BERLIN) += \
>> +	mv88de3100-sony-nsz-gs7.dtb
>>   dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
>>   	da850-evm.dtb
>>   dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
>> diff --git a/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
>> new file mode 100644
>> index 0000000..1081bc1
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
>> @@ -0,0 +1,29 @@
>> +/*
>> + * Device Tree file for Sony NSZ-GS7
>> + *
>> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "mv88de3100.dtsi"
>> +
>> +/ {
>> +	model = "Sony NSZ-GS7";
>> +	compatible = "sony,nsz-gs7", "marvell,88de3100", "marvell,berlin";
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200 earlyprintk verbose debug";
>
> I would remove 'verbose debug' before official submission, no point to
> defaulting to log-spammer.

Agree.

Maybe, for the next patches, I'll add some I/O device drivers that
allow you to actually boot into some rootfs. All those fooHCI IP
shouldn't be that hard - hopefully some quirks only.

I also had a look at I2C and SPI, both DW IP with mainline drivers
available. SPI needs a little DT tweaking and I did not carry out any
functional tests, yet.

Thanks for the constant reviews!

Sebastian