Re: [PATCH v2 1/7] pinctrl: imx1 core driver

Re: [PATCH v2 1/7] pinctrl: imx1 core driver

[Markus Pargmann]

Hi,

sorry for the late response, I moved last week.

On Tue, Aug 20, 2013 at 08:56:17PM +0800, Shawn Guo wrote:
> Looks good to me.  A couple of small comments below.
> 
> On Mon, Aug 19, 2013 at 04:07:08PM +0200, Markus Pargmann wrote:
> > +/*
> > + * Write to a register with 2 bits per pin. The function will automatically
> > + * use the next register if the pin is managed in the second register.
> > + */
> > +static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
> > +		u32 value, u32 reg_offset)
> > +{
> > +	void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
> > +	int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
> > +	int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
> > +	u32 old_val;
> > +	u32 new_val;
> > +
> > +	dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
> > +			reg, offset, value);
> > +
> > +	/* Use the next register if the pin's port pin number is >=16 */
> > +	if (pin_id % 32 >= 16)
> > +		reg += 0x04;
> > +
> > +	/* Get current state of pins */
> > +	old_val = readl(reg);
> > +	old_val &= mask;
> > +
> > +	new_val = value & 0x3; /* Make sure value is really 2 bit */
> > +	new_val <<= offset;
> > +	new_val |= old_val;/* Set new state for pin_id */
> > +
> > +	writel(new_val, reg);
> > +}
> > +
> > +static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
> > +		u32 value, u32 reg_offset)
> > +{
> > +	void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
> > +	int offset = pin_id % 32;
> > +	int mask = ~BIT_MASK(offset);
> > +	u32 old_val;
> > +	u32 new_val;
> > +
> > +	/* Get current state of pins */
> > +	old_val = readl(reg);
> > +	old_val &= mask;
> > +
> > +	new_val = value & 0x1; /* Make sure value is really 2 bit */
> 
> Copy&past error in comment.
> 
> > +	new_val <<= offset;
> > +	new_val |= old_val;/* Set new state for pin_id */
> > +
> > +	writel(new_val, reg);
> > +}
> 
> <snip>
> 
> > +static int imx1_pinctrl_parse_groups(struct device_node *np,
> > +				    struct imx1_pin_group *grp,
> > +				    struct imx1_pinctrl_soc_info *info,
> > +				    u32 index)
> > +{
> > +	int size;
> > +	const __be32 *list;
> > +	int i;
> > +
> > +	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
> > +
> > +	/* Initialise group */
> > +	grp->name = np->name;
> > +
> > +	/*
> > +	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
> 
> It does not match the bindings.
> 
> > +	 * do sanity check and calculate pins number
> > +	 */
> > +	list = of_get_property(np, "fsl,pins", &size);
> > +	/* we do not check return since it's safe node passed down */
> > +	if (!size || size % 12) {
> > +		dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
> > +				np->name);
> > +		return -EINVAL;
> > +	}
> > +
> > +	grp->npins = size / 12;
> > +	grp->pins = devm_kzalloc(info->dev,
> > +			grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
> > +	grp->pin_ids = devm_kzalloc(info->dev,
> > +			grp->npins * sizeof(unsigned int), GFP_KERNEL);
> > +
> > +	if (!grp->pins || !grp->pin_ids)
> > +		return -ENOMEM;
> > +
> > +	for (i = 0; i < grp->npins; i++) {
> > +		grp->pins[i].pin_id = be32_to_cpu(*list++);
> > +		grp->pins[i].mux_id = be32_to_cpu(*list++);
> > +		grp->pins[i].config = be32_to_cpu(*list++);
> > +
> > +		grp->pin_ids[i] = grp->pins[i].pin_id;
> > +	}
> > +
> > +	return 0;
> > +}
> 
> <snip>
> 
> > +static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
> > +		struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
> > +{
> > +	struct device_node *np = pdev->dev.of_node;
> > +	struct device_node *child;
> > +	int ret;
> > +	u32 nfuncs = 0;
> > +	u32 ngroups = 0;
> > +	u32 ifunc = 0;
> > +	u32 base_addr;
> > +
> > +	if (!np)
> > +		return -ENODEV;
> > +
> > +	ret = of_property_read_u32(np, "reg", &base_addr);
> 
> It seems base_addr is used nowhere?

It's not used anymore. Some old code I forgot to remove from the gpio
subdevices.

I also fixed the comments you mentioned.

Thanks,

Markus

> 
> Shawn
> 
> > +	if (ret)
> > +		return ret;
> > +
> > +	for_each_child_of_node(np, child) {
> > +		++nfuncs;
> > +		ngroups += of_get_child_count(child);
> > +	}
> > +
> > +	if (!nfuncs) {
> > +		dev_err(&pdev->dev, "No pin functions defined\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	info->nfunctions = nfuncs;
> > +	info->functions = devm_kzalloc(&pdev->dev,
> > +			nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
> > +
> > +	info->ngroups = ngroups;
> > +	info->groups = devm_kzalloc(&pdev->dev,
> > +			ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
> > +
> > +
> > +	if (!info->functions || !info->groups)
> > +		return -ENOMEM;
> > +
> > +	for_each_child_of_node(np, child) {
> > +		ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
> > +		if (ret == -ENOMEM)
> > +			return -ENOMEM;
> > +	}
> > +
> > +	return 0;
> > +}
> 
> 

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Re: [PATCH v2 4/7] ARM: dts: imx27 pinctrl

[Markus Pargmann]

Hi Sascha,

On Tue, Aug 20, 2013 at 09:14:11AM +0200, Sascha Hauer wrote:
> On Mon, Aug 19, 2013 at 04:07:11PM +0200, Markus Pargmann wrote:
> > Pinctrl driver node and pin group definitions for other driver nodes.
> > 
> > Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> > ---
> > +					pinctrl_uart_1: uart-1 {
> > +						fsl,pins = <
> > +							MX27_PAD_UART1_TXD__UART1_TXD 0x0
> > +							MX27_PAD_UART1_RXD__UART1_RXD 0x0
> > +							MX27_PAD_UART1_CTS__UART1_CTS 0x0
> > +							MX27_PAD_UART1_RTS__UART1_RTS 0x0
> > +						>;
> > +					};
> 
> The above either misses a group number or an uart number. We need
> pinctrl_uart<uartno>_<groupno>

Fixed.

> 
> Also this doesn't scale very good. For boards without RTS/CTS we would have
> to add a completely different group. For the FEC I've seen different
> groups with a dozen pins each which differ in only a single pin.
> 
> I therefore suggest (and Shawn acked the general idea already) to
> do this:
> 
> 	pinctrl_uart1_1: uart1-1 {
> 		fsl,pins = <
> 			MX27_PAD_UART1_TXD__UART1_TXD 0x0
> 			MX27_PAD_UART1_RXD__UART1_RXD 0x0
> 		>;
> 	};
> 
> 	pinctrl_uart1_rtscts_1: uart1-rtscts-1 {
> 		fsl,pins = <
> 			MX27_PAD_UART1_CTS__UART1_CTS 0x0
> 			MX27_PAD_UART1_RTS__UART1_RTS 0x0
> 		>;
> 	};

I changed the uart groups accordingly.

Thanks,

Markus

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH v2 4/7] ARM: dts: imx27 pinctrl

[Markus Pargmann]

On Wed, Aug 21, 2013 at 09:30:36AM +0800, Shawn Guo wrote:
> On Mon, Aug 19, 2013 at 04:07:11PM +0200, Markus Pargmann wrote:
> > Pinctrl driver node and pin group definitions for other driver nodes.
> > 
> > Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> > ---
> >  arch/arm/boot/dts/imx27.dtsi | 84 ++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 84 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> > index 76cd89f..b9477d6 100644
> > --- a/arch/arm/boot/dts/imx27.dtsi
> > +++ b/arch/arm/boot/dts/imx27.dtsi
> > @@ -10,6 +10,7 @@
> >   */
> >  
> >  #include "skeleton.dtsi"
> > +#include "imx27-pinfunc.h"
> >  
> >  / {
> >  	aliases {
> > @@ -235,6 +236,89 @@
> >  				status = "disabled";
> >  			};
> >  
> > +			iomuxc: iomuxc@10015000 {
> > +				compatible = "fsl,imx27-iomuxc";
> > +				reg = <0x10015000 0x600>;
> > +
> > +				fec {
> > +					pinctrl_fec_1: fec-1 {
> > +						fsl,pins = <
> > +							MX27_PAD_SD3_CMD__FEC_TXD0 0x0
> > +							MX27_PAD_SD3_CLK__FEC_TXD1 0x0
> > +							MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
> > +							MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
> > +							MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
> > +							MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
> > +							MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
> > +							MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
> > +							MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
> > +							MX27_PAD_ATA_DATA7__FEC_MDC 0x0
> > +							MX27_PAD_ATA_DATA8__FEC_CRS 0x0
> > +							MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
> > +							MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
> > +							MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
> > +							MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
> > +							MX27_PAD_ATA_DATA13__FEC_COL 0x0
> > +							MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
> > +							MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
> > +						>;
> > +					};
> > +				};
> 
> I like the idea [1] from Alexander Shiyan that maintains all these
> pinctrl setting entries outside the main device nodes structure.  Can
> you please do that for imx27.dtsi from the beginning?

Yes, the seperation looks better, I changed it.

Regards,

Markus

> 
> Shawn
> 
> [1] http://article.gmane.org/gmane.linux.ports.arm.kernel/260404
> 
> > +
> > +				i2c {
> > +					pinctrl_i2c_1: i2c-1 {
> > +						fsl,pins = <
> > +							MX27_PAD_I2C_DATA__I2C_DATA 0x0
> > +							MX27_PAD_I2C_CLK__I2C_CLK 0x0
> > +						>;
> > +					};
> > +
> > +					pinctrl_i2c_2: i2c-2 {
> > +						fsl,pins = <
> > +							MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
> > +							MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
> > +						>;
> > +					};
> > +				};
> > +
> > +				owire {
> > +					pinctrl_owire_1: owire-1 {
> > +						fsl,pins = <
> > +							MX27_PAD_RTCK__OWIRE 0x0
> > +						>;
> > +					};
> > +				};
> > +
> > +				uart {
> > +					pinctrl_uart_1: uart-1 {
> > +						fsl,pins = <
> > +							MX27_PAD_UART1_TXD__UART1_TXD 0x0
> > +							MX27_PAD_UART1_RXD__UART1_RXD 0x0
> > +							MX27_PAD_UART1_CTS__UART1_CTS 0x0
> > +							MX27_PAD_UART1_RTS__UART1_RTS 0x0
> > +						>;
> > +					};
> > +
> > +					pinctrl_uart_2: uart-2 {
> > +						fsl,pins = <
> > +							MX27_PAD_UART2_TXD__UART2_TXD 0x0
> > +							MX27_PAD_UART2_RXD__UART2_RXD 0x0
> > +							MX27_PAD_UART2_CTS__UART2_CTS 0x0
> > +							MX27_PAD_UART2_RTS__UART2_RTS 0x0
> > +						>;
> > +					};
> > +
> > +					pinctrl_uart_3: uart-3 {
> > +						fsl,pins = <
> > +							MX27_PAD_UART3_TXD__UART3_TXD 0x0
> > +							MX27_PAD_UART3_RXD__UART3_RXD 0x0
> > +							MX27_PAD_UART3_CTS__UART3_CTS 0x0
> > +							MX27_PAD_UART3_RTS__UART3_RTS 0x0
> > +						>;
> > +					};
> > +				};
> > +			};
> > +
> >  			gpio1: gpio@10015000 {
> >  				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> >  				reg = <0x10015000 0x100>;
> > -- 
> > 1.8.4.rc3
> > 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH v2 2/7] pinctrl: imx27: imx27 pincontrol driver

[Markus Pargmann]

On Wed, Aug 21, 2013 at 09:23:03AM +0800, Shawn Guo wrote:
> On Mon, Aug 19, 2013 at 04:07:09PM +0200, Markus Pargmann wrote:
> > imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> > similar to other imx pincontrol drivers.
> > 
> > Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> > ---
> >  .../bindings/pinctrl/fsl,imx27-pinctrl.txt         |  53 +++
> >  drivers/pinctrl/Kconfig                            |   8 +
> >  drivers/pinctrl/Makefile                           |   1 +
> >  drivers/pinctrl/pinctrl-imx27.c                    | 477 +++++++++++++++++++++
> >  4 files changed, 539 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> >  create mode 100644 drivers/pinctrl/pinctrl-imx27.c
> > 
> > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > new file mode 100644
> > index 0000000..016fc89
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > @@ -0,0 +1,53 @@
> > +* Freescale IMX27 IOMUX Controller
> > +
> > +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
> > +and usage.
> 
> Since imx-pinctrl and imx1-pinctrl are now two completely different
> drivers/bindings, is there actually anything from fsl,imx-pinctrl.txt
> could be referred to here?

No, fixed, thanks.

Regards,

Markus

> 
> Shawn
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |