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From: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
To: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Benjamin Herrenschmidt
	<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>,
	Nicolas Pitre
	<nicolas.pitre-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Dave P Martin <Dave.Martin-5wv7dgnIgG8@public.gmane.org>,
	Vincent Guittot
	<vincent.guittot-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Mark Rutland <Mark.Rutland-5wv7dgnIgG8@public.gmane.org>,
	Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org>,
	Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Pawel Moll <Pawel.Moll-5wv7dgnIgG8@public.gmane.org>,
	Ian Campbell
	<ian.campbell-Sxgqhf6Nn4DQT0dZR+AlfA@public.gmane.org>,
	Hanjun Guo <hanjun.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Subject: Re: [PATCH 2/2] Documentation: DT: arm: define CPU topology bindings
Date: Mon, 16 Sep 2013 10:10:06 +0100	[thread overview]
Message-ID: <20130916091006.GC22390@e102568-lin.cambridge.arm.com> (raw)
In-Reply-To: <52337E7F.9010802-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On Fri, Sep 13, 2013 at 10:07:11PM +0100, Rob Herring wrote:
> On 08/15/2013 04:42 AM, Lorenzo Pieralisi wrote:
> > The advent of multi-cluster ARM systems requires a mechanism to describe
> > how in hierarchical terms CPUs are connected in ARM SoCs so that the kernel
> > can initialize and map resources like IRQs and memory space to specific
> > group(s) of CPUs.
> > 
> > The CPU topology is made up of multiple hierarchy levels whose bottom
> > layers (aka leaf nodes in device tree syntax) contain links to the HW
> > CPUs in the system.
> > 
> > The topology bindings are generic for both 32-bit and 64-bit systems and
> > lay the groundwork on top of which affinity schemes can be built.
> 
> By affinity schemes, you mean further bindings? Do we need this binding
> until that point?

Well, further bindings (for HW like perf counters) will rely on these
topology bindings to build IRQ affinity masks for instance.

I think we should go on and publish these bindings asap so that we can
rely on them to properly describe topologies for ARM from the beginning.

Current reliance on MPIDR is a leap of faith.

> As is, I don't have much comment.

I take this as positive feedback, or put it another way, that you think
bindings are sound.

> 
> [snip]
> 
> > +Example 3 (ARM 32-bit, cortex-a8 single core):
> > +
> > +cpus {
> > +	#size-cells = <0>;
> > +	#address-cells = <1>;
> > +
> > +	cpu-map {
> > +		cluster0 {
> > +			core0 {
> > +				cpu = <&CPU0>;
> > +			};
> > +		};
> > +	};
> 
> This example seems utterly pointless. I think we should be specific that
> single core does not contain a cpu-map. I suppose we could have a
> threaded, single core case, but let's address that if we ever do.

Ok right. We can have a multi cluster system where one cluster is made
up of a single CPU, then a binding like the one above makes sense.
I will rule cpu-map out for uniprocessor systems.

Lorenzo

> 
> Rob
> 
> > +
> > +	CPU0: cpu@0 {
> > +		device_type = "cpu";
> > +		compatible = "arm,cortex-a8";
> > +		reg = <0x0>;
> > +	};
> > +};
> > +
> > +===============================================================================
> > +[1] ARM Linux kernel documentation
> > +    Documentation/devicetree/bindings/arm/cpus.txt
> > 
> 
> 

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      parent reply	other threads:[~2013-09-16  9:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1376559743-31848-1-git-send-email-lorenzo.pieralisi@arm.com>
     [not found] ` <1376559743-31848-2-git-send-email-lorenzo.pieralisi@arm.com>
2013-08-28 19:45   ` [PATCH 1/2] Documentation: devicetree: arm: cpus/cpu nodes bindings updates Grant Likely
     [not found]   ` <520CE665.8060907@gmail.com>
     [not found]     ` <20130815152238.GF17839@e102568-lin.cambridge.arm.com>
     [not found]       ` <20130815152238.GF17839-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2013-09-13 16:57         ` Lorenzo Pieralisi
     [not found]           ` <20130913165708.GC5408-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2013-09-13 20:51             ` Rob Herring
     [not found]               ` <52337AEC.9080302-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-09-14  7:49                 ` Andrew Lunn
2013-09-16  8:55                 ` Lorenzo Pieralisi
2013-09-15  8:36             ` Andrew Lunn
     [not found]               ` <20130915083658.GH23705-g2DYL2Zd6BY@public.gmane.org>
2013-09-16  8:57                 ` Lorenzo Pieralisi
     [not found] ` <1376559743-31848-3-git-send-email-lorenzo.pieralisi@arm.com>
     [not found]   ` <1376559743-31848-3-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2013-09-13 16:39     ` [PATCH 2/2] Documentation: DT: arm: define CPU topology bindings Lorenzo Pieralisi
2013-09-13 21:07     ` Rob Herring
     [not found]       ` <52337E7F.9010802-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-09-16  9:10         ` Lorenzo Pieralisi [this message]

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