* [PATCHv6 01/45] CLK: TI: Add DPLL clock support
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
@ 2013-08-29 13:15 ` Tero Kristo
2013-09-10 22:09 ` Mike Turquette
[not found] ` <1377782197-10611-2-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
2013-08-29 13:15 ` [PATCHv6 02/45] CLK: TI: add DT alias clock registration mechanism Tero Kristo
` (43 subsequent siblings)
44 siblings, 2 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:15 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/dpll.txt | 68 +++
arch/arm/mach-omap2/clock.h | 144 +-----
arch/arm/mach-omap2/clock3xxx.h | 2 -
drivers/clk/Makefile | 1 +
drivers/clk/ti/Makefile | 3 +
drivers/clk/ti/dpll.c | 476 ++++++++++++++++++++
include/linux/clk/ti.h | 164 +++++++
7 files changed, 713 insertions(+), 145 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
create mode 100644 drivers/clk/ti/Makefile
create mode 100644 drivers/clk/ti/dpll.c
create mode 100644 include/linux/clk/ti.h
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 0000000..83c21c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,68 @@
+Binding for Texas Instruments DPLL clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,omap4-dpll-x2-clock",
+ "ti,omap3-dpll-clock",
+ "ti,omap3-dpll-core-clock",
+ "ti,omap3-dpll-per-clock",
+ "ti,omap3-dpll-per-j-type-clock",
+ "ti,omap4-dpll-clock",
+ "ti,omap4-dpll-core-clock",
+ "ti,omap4-dpll-m4xen-clock",
+ "ti,omap4-dpll-j-type-clock",
+ "ti,omap4-dpll-no-gate-clock",
+ "ti,omap4-dpll-no-gate-j-type-clock",
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks, first entry lists reference clock
+ and second entry bypass clock
+- reg : address and length of the register set for controlling the DPLL.
+ It contains the information of registers in the same order as described by
+ reg-names.
+- reg-names : array of the register names for controlling the device, sorted
+ in the same order as the reg property.
+ "control" - contains the control register base address
+ "idlest" - contains the idle status register base address
+ "autoidle" - contains the autoidle register base address
+ "mult-div1" - contains the multiplier / divider register base address
+
+Optional properties:
+- ti,modes : available modes for the DPLL, bitmask of:
+ 0x02 - DPLL supports low power stop mode
+ 0x20 - DPLL can be put to low power bypass mode
+ 0x80 - DPLL can be put to lock mode (running)
+ Other values currently unsupported.
+- ti,clkdm-name : clockdomain name for the DPLL
+
+Examples:
+ dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
+ <0x44e00468 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ };
+
+ dpll2_ck: dpll2_ck@48004004 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ ti,modes = <0xa2>;
+ reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>,
+ <0x48004040 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ ti,clkdm-name = "dpll2_clkdm";
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..079536a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
struct omap_clk {
u16 cpu;
@@ -178,83 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- * omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- * omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
- void __iomem *mult_div1_reg;
- u32 mult_mask;
- u32 div1_mask;
- struct clk *clk_bypass;
- struct clk *clk_ref;
- void __iomem *control_reg;
- u32 enable_mask;
- unsigned long last_rounded_rate;
- u16 last_rounded_m;
- u8 last_rounded_m4xen;
- u8 last_rounded_lpmode;
- u16 max_multiplier;
- u8 last_rounded_n;
- u8 min_divider;
- u16 max_divider;
- u8 modes;
- void __iomem *autoidle_reg;
- void __iomem *idlest_reg;
- u32 autoidle_mask;
- u32 freqsel_mask;
- u32 idlest_mask;
- u32 dco_mask;
- u32 sddiv_mask;
- u32 lpmode_mask;
- u32 m4xen_mask;
- u8 auto_recal_bit;
- u8 recal_en_bit;
- u8 recal_st_bit;
- u8 flags;
-};
-
/*
* struct clk.flags possibilities
*
@@ -274,45 +198,6 @@ struct dpll_data {
#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
#define CLOCK_CLKOUTX2 (1 << 5)
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
- struct clk_hw hw;
- struct list_head node;
- unsigned long fixed_rate;
- u8 fixed_div;
- void __iomem *enable_reg;
- u8 enable_bit;
- u8 flags;
- void __iomem *clksel_reg;
- u32 clksel_mask;
- const struct clksel *clksel;
- struct dpll_data *dpll_data;
- const char *clkdm_name;
- struct clockdomain *clkdm;
- const struct clk_hw_omap_ops *ops;
-};
-
struct clk_hw_omap_ops {
void (*find_idlest)(struct clk_hw_omap *oclk,
void __iomem **idlest_reg,
@@ -348,36 +233,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP 0x1
-#define DPLL_LOW_POWER_BYPASS 0x5
-#define DPLL_LOCKED 0x7
-
-/* DPLL Type and DCO Selection Flags */
-#define DPLL_J_TYPE 0x1
-
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
- unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate);
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
- unsigned long target_rate,
- unsigned long *parent_rate);
-void omap2_init_clk_clkdm(struct clk_hw *clk);
void __init omap2_clk_disable_clkdm_control(void);
/* clkt_clksel.c public functions */
@@ -396,7 +258,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,7 +269,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap2_clk_enable_autoidle_all(void);
int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
@@ -431,10 +291,8 @@ extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a..dab90e2 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,8 +9,6 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
- unsigned long parent_rate);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void omap3_clk_lock_dpll5(void);
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4038c2b..cf55585 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
+obj-$(CONFIG_ARCH_OMAP) += ti/
obj-$(CONFIG_X86) += x86/
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 0000000..93177987
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,3 @@
+ifneq ($(CONFIG_OF),)
+obj-y += dpll.o
+endif
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
new file mode 100644
index 0000000..3f4236d
--- /dev/null
+++ b/drivers/clk/ti/dpll.c
@@ -0,0 +1,476 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static const struct clk_ops dpll_m4xen_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_core_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops dpll_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+ .init = &omap2_init_clk_clkdm,
+};
+
+static const struct clk_ops dpll_no_gate_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+};
+
+static const struct clk_ops omap3_dpll_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .round_rate = &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops omap3_dpll_per_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap3_dpll_recalc,
+ .set_rate = &omap3_dpll4_set_rate,
+ .round_rate = &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops dpll_x2_ck_ops = {
+ .recalc_rate = &omap3_clkoutx2_recalc,
+};
+
+static struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
+ const char **parent_names, int num_parents, unsigned long flags,
+ struct dpll_data *dpll_data, const char *clkdm_name,
+ const struct clk_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { 0 };
+ struct clk_hw_omap *clk_hw;
+
+ /* allocate the divider */
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->dpll_data = dpll_data;
+ clk_hw->ops = &clkhwops_omap3_dpll;
+ clk_hw->clkdm_name = clkdm_name;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.flags = flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ if (IS_ERR(clk))
+ kfree(clk_hw);
+ else
+ omap2_init_clk_hw_omap_clocks(clk);
+
+ return clk;
+}
+
+static struct clk *omap_clk_register_dpll_x2(struct device *dev,
+ const char *name, const char *parent_name, void __iomem *reg,
+ const struct clk_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { 0 };
+ struct clk_hw_omap *clk_hw;
+
+ if (!parent_name) {
+ pr_err("%s: dpll_x2 must have parent\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->ops = &clkhwops_omap4_dpllmx;
+ clk_hw->clksel_reg = reg;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ if (IS_ERR(clk))
+ kfree(clk_hw);
+ else
+ omap2_init_clk_hw_omap_clocks(clk);
+
+ return clk;
+}
+
+/**
+ * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
+ *
+ * @node: device node containing the DPLL info
+ * @ops: ops for the DPLL
+ * @ddt: DPLL data template to use
+ */
+static void __init of_omap_dpll_setup(struct device_node *node,
+ const struct clk_ops *ops,
+ const struct dpll_data *ddt)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ int num_parents;
+ const char **parent_names = NULL;
+ const char *clkdm_name = NULL;
+ u8 dpll_flags = 0;
+ struct dpll_data *dd;
+ int i;
+ u32 val;
+
+ dd = kzalloc(sizeof(*dd), GFP_KERNEL);
+ if (!dd) {
+ pr_err("%s: could not allocate dpll_data\n", __func__);
+ return;
+ }
+
+ memcpy(dd, ddt, sizeof(*dd));
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: omap dpll %s must have parent(s)\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ dd->clk_ref = of_clk_get(node, 0);
+ dd->clk_bypass = of_clk_get(node, 1);
+
+ if (IS_ERR(dd->clk_ref)) {
+ pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (IS_ERR(dd->clk_bypass)) {
+ pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
+
+ i = of_property_match_string(node, "reg-names", "control");
+ if (i >= 0)
+ dd->control_reg = of_iomap(node, i);
+
+ i = of_property_match_string(node, "reg-names", "idlest");
+ if (i >= 0)
+ dd->idlest_reg = of_iomap(node, i);
+
+ i = of_property_match_string(node, "reg-names", "autoidle");
+ if (i >= 0)
+ dd->autoidle_reg = of_iomap(node, i);
+
+ i = of_property_match_string(node, "reg-names", "mult-div1");
+ if (i >= 0)
+ dd->mult_div1_reg = of_iomap(node, i);
+
+ if (!of_property_read_u32(node, "ti,modes", &val))
+ dd->modes = val;
+
+ clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
+ num_parents, dpll_flags, dd,
+ clkdm_name, ops);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+cleanup:
+ kfree(dd);
+ kfree(parent_names);
+ return;
+}
+
+static void __init of_omap_dpll_x2_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+
+ clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
+ reg, &dpll_x2_ck_ops);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(omap_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
+ of_omap_dpll_x2_setup);
+
+static void __init of_omap3_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf0,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
+
+static void __init of_omap3_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 16,
+ .div1_mask = 0x7f << 8,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf0,
+ };
+
+ of_omap_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
+ of_omap3_core_dpll_setup);
+
+static void __init of_omap3_per_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1 << 1,
+ .enable_mask = 0x7 << 16,
+ .autoidle_mask = 0x7 << 3,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .freqsel_mask = 0xf00000,
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
+ of_omap3_per_dpll_setup);
+
+static void __init of_omap3_per_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1 << 1,
+ .enable_mask = 0x7 << 16,
+ .autoidle_mask = 0x7 << 3,
+ .mult_mask = 0xfff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 4095,
+ .max_divider = 128,
+ .min_divider = 1,
+ .sddiv_mask = 0xff << 24,
+ .dco_mask = 0xe << 20,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
+ of_omap3_per_jtype_dpll_setup);
+
+static void __init of_omap4_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &dpll_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
+
+static void __init of_omap4_core_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &dpll_core_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
+ of_omap4_core_dpll_setup);
+
+static void __init of_omap4_m4xen_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .m4xen_mask = 0x800,
+ .lpmode_mask = 1 << 10,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
+ of_omap4_m4xen_dpll_setup);
+
+static void __init of_omap4_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0xfff << 8,
+ .div1_mask = 0xff,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+ .sddiv_mask = 0xff << 24,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
+ of_omap4_jtype_dpll_setup);
+
+static void __init of_omap4_no_gate_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_no_gate_dpll_clock, "ti,omap4-dpll-no-gate-clock",
+ of_omap4_no_gate_dpll_setup);
+
+static void __init of_omap4_no_gate_jtype_dpll_setup(struct device_node *node)
+{
+ const struct dpll_data dd = {
+ .idlest_mask = 0x1,
+ .enable_mask = 0x7,
+ .autoidle_mask = 0x7,
+ .mult_mask = 0x7ff << 8,
+ .div1_mask = 0x7f,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+ .flags = DPLL_J_TYPE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ };
+
+ of_omap_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_no_gate_jtype_dpll_clock,
+ "ti,omap4-dpll-no-gate-j-type-clock",
+ of_omap4_no_gate_jtype_dpll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
new file mode 100644
index 0000000..385384a
--- /dev/null
+++ b/include/linux/clk/ti.h
@@ -0,0 +1,164 @@
+/*
+ * TI clock drivers support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_CLK_TI_H__
+#define __LINUX_CLK_TI_H__
+
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ * omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ * omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+ void __iomem *mult_div1_reg;
+ u32 mult_mask;
+ u32 div1_mask;
+ struct clk *clk_bypass;
+ struct clk *clk_ref;
+ void __iomem *control_reg;
+ u32 enable_mask;
+ unsigned long last_rounded_rate;
+ u16 last_rounded_m;
+ u8 last_rounded_m4xen;
+ u8 last_rounded_lpmode;
+ u16 max_multiplier;
+ u8 last_rounded_n;
+ u8 min_divider;
+ u16 max_divider;
+ u8 modes;
+ void __iomem *autoidle_reg;
+ void __iomem *idlest_reg;
+ u32 autoidle_mask;
+ u32 freqsel_mask;
+ u32 idlest_mask;
+ u32 dco_mask;
+ u32 sddiv_mask;
+ u32 lpmode_mask;
+ u32 m4xen_mask;
+ u8 auto_recal_bit;
+ u8 recal_en_bit;
+ u8 recal_st_bit;
+ u8 flags;
+};
+
+struct clk_hw_omap_ops;
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+struct clk_hw_omap {
+ struct clk_hw hw;
+ struct list_head node;
+ unsigned long fixed_rate;
+ u8 fixed_div;
+ void __iomem *enable_reg;
+ u8 enable_bit;
+ u8 flags;
+ void __iomem *clksel_reg;
+ u32 clksel_mask;
+ const struct clksel *clksel;
+ struct dpll_data *dpll_data;
+ const char *clkdm_name;
+ struct clockdomain *clkdm;
+ const struct clk_hw_omap_ops *ops;
+};
+
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP 0x1
+#define DPLL_LOW_POWER_BYPASS 0x5
+#define DPLL_LOCKED 0x7
+
+/* DPLL Type and DCO Selection Flags */
+#define DPLL_J_TYPE 0x1
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+ unsigned long target_rate,
+ unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+ unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+ unsigned long parent_rate);
+
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCHv6 01/45] CLK: TI: Add DPLL clock support
2013-08-29 13:15 ` [PATCHv6 01/45] CLK: TI: Add DPLL clock support Tero Kristo
@ 2013-09-10 22:09 ` Mike Turquette
[not found] ` <1377782197-10611-2-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
1 sibling, 0 replies; 48+ messages in thread
From: Mike Turquette @ 2013-09-10 22:09 UTC (permalink / raw)
To: Tero Kristo, linux-omap, paul, tony, rnayak, nm
Cc: linux-arm-kernel, devicetree
Quoting Tero Kristo (2013-08-29 06:15:53)
> The OMAP clock driver now supports DPLL clock type. This patch also
> adds support for DT DPLL nodes.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tero,
Overall this patch is really great. Some minor comments below.
> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> new file mode 100644
> index 0000000..83c21c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> @@ -0,0 +1,68 @@
> +Binding for Texas Instruments DPLL clock.
> +
> +This binding uses the common clock binding[1]. It assumes a
> +register-mapped DPLL with usually two selectable input clocks
> +(reference clock and bypass clock), with digital phase locked
> +loop logic for multiplying the input clock to a desired output
> +clock. This clock also typically supports different operation
> +modes (locked, low power stop etc.) This binding has several
> +sub-types, which effectively result in slightly different setup
> +for the actual DPLL clock.
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : shall be one of:
> + "ti,omap4-dpll-x2-clock",
> + "ti,omap3-dpll-clock",
> + "ti,omap3-dpll-core-clock",
> + "ti,omap3-dpll-per-clock",
> + "ti,omap3-dpll-per-j-type-clock",
> + "ti,omap4-dpll-clock",
> + "ti,omap4-dpll-core-clock",
> + "ti,omap4-dpll-m4xen-clock",
> + "ti,omap4-dpll-j-type-clock",
> + "ti,omap4-dpll-no-gate-clock",
> + "ti,omap4-dpll-no-gate-j-type-clock",
> +
> +- #clock-cells : from common clock binding; shall be set to 0.
> +- clocks : link phandles of parent clocks, first entry lists reference clock
> + and second entry bypass clock
> +- reg : address and length of the register set for controlling the DPLL.
> + It contains the information of registers in the same order as described by
> + reg-names.
> +- reg-names : array of the register names for controlling the device, sorted
> + in the same order as the reg property.
> + "control" - contains the control register base address
> + "idlest" - contains the idle status register base address
> + "autoidle" - contains the autoidle register base address
> + "mult-div1" - contains the multiplier / divider register base address
> +
> +Optional properties:
> +- ti,modes : available modes for the DPLL, bitmask of:
> + 0x02 - DPLL supports low power stop mode
> + 0x20 - DPLL can be put to low power bypass mode
> + 0x80 - DPLL can be put to lock mode (running)
Any particular reason to use a bitmask here versus flags/DT properties?
Something like
Optional properties:
low-power-stop : DPLL supports low power stop mode, gating output
low-power-bypass : DPLL output matches rate of parent bypass clock
lock : DPLL locks in programmed rate
Is there ever a time when a DPLL does not support the locked state? We
can probably remove that from binding entirely.
> + Other values currently unsupported.
> +- ti,clkdm-name : clockdomain name for the DPLL
What does this mean? I thought that the clockdomain data would not go
into the clock binding?
> diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
> new file mode 100644
> index 0000000..3f4236d
> --- /dev/null
> +++ b/drivers/clk/ti/dpll.c
> @@ -0,0 +1,476 @@
> +/*
> + * OMAP DPLL clock support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk/ti.h>
> +
> +static const struct clk_ops dpll_m4xen_ck_ops = {
> + .enable = &omap3_noncore_dpll_enable,
> + .disable = &omap3_noncore_dpll_disable,
> + .recalc_rate = &omap4_dpll_regm4xen_recalc,
> + .round_rate = &omap4_dpll_regm4xen_round_rate,
> + .set_rate = &omap3_noncore_dpll_set_rate,
> + .get_parent = &omap2_init_dpll_parent,
> +};
> +
> +static const struct clk_ops dpll_core_ck_ops = {
> + .recalc_rate = &omap3_dpll_recalc,
> + .get_parent = &omap2_init_dpll_parent,
> +};
> +
> +static const struct clk_ops omap3_dpll_core_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .get_parent = &omap2_init_dpll_parent,
> + .recalc_rate = &omap3_dpll_recalc,
> + .round_rate = &omap2_dpll_round_rate,
> +};
> +
> +static const struct clk_ops dpll_ck_ops = {
> + .enable = &omap3_noncore_dpll_enable,
> + .disable = &omap3_noncore_dpll_disable,
> + .recalc_rate = &omap3_dpll_recalc,
> + .round_rate = &omap2_dpll_round_rate,
> + .set_rate = &omap3_noncore_dpll_set_rate,
> + .get_parent = &omap2_init_dpll_parent,
> + .init = &omap2_init_clk_clkdm,
> +};
> +
> +static const struct clk_ops dpll_no_gate_ck_ops = {
> + .recalc_rate = &omap3_dpll_recalc,
> + .get_parent = &omap2_init_dpll_parent,
> + .round_rate = &omap2_dpll_round_rate,
> + .set_rate = &omap3_noncore_dpll_set_rate,
> +};
> +
> +static const struct clk_ops omap3_dpll_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap3_noncore_dpll_enable,
> + .disable = &omap3_noncore_dpll_disable,
> + .get_parent = &omap2_init_dpll_parent,
> + .recalc_rate = &omap3_dpll_recalc,
> + .set_rate = &omap3_noncore_dpll_set_rate,
> + .round_rate = &omap2_dpll_round_rate,
> +};
> +
> +static const struct clk_ops omap3_dpll_per_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap3_noncore_dpll_enable,
> + .disable = &omap3_noncore_dpll_disable,
> + .get_parent = &omap2_init_dpll_parent,
> + .recalc_rate = &omap3_dpll_recalc,
> + .set_rate = &omap3_dpll4_set_rate,
> + .round_rate = &omap2_dpll_round_rate,
> +};
> +
> +static const struct clk_ops dpll_x2_ck_ops = {
> + .recalc_rate = &omap3_clkoutx2_recalc,
> +};
No .set_parent ops for any of the DPLLs? How do you handle bypassing
them? Are you using another mux clock that is the parent of the DPLL, or
just open-coding the bypass stuff?
Regards,
Mike
^ permalink raw reply [flat|nested] 48+ messages in thread[parent not found: <1377782197-10611-2-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>]
* Re: [PATCHv6 01/45] CLK: TI: Add DPLL clock support
[not found] ` <1377782197-10611-2-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
@ 2013-09-17 16:09 ` Tony Lindgren
0 siblings, 0 replies; 48+ messages in thread
From: Tony Lindgren @ 2013-09-17 16:09 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA, paul-DWxLp4Yu+b8AvxtiuMwx3w,
rnayak-l0cyMroinI0, nm-l0cyMroinI0,
mturquette-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
* Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org> [130829 06:24]:
> The OMAP clock driver now supports DPLL clock type. This patch also
> adds support for DT DPLL nodes.
...
> +- reg-names : array of the register names for controlling the device, sorted
> + in the same order as the reg property.
> + "control" - contains the control register base address
> + "idlest" - contains the idle status register base address
> + "autoidle" - contains the autoidle register base address
> + "mult-div1" - contains the multiplier / divider register base address
FYI, looks like there's some tab vs spaces issue with the
formatting above.
> +Examples:
> + dpll_core_ck: dpll_core_ck@44e00490 {
> + #clock-cells = <0>;
> + compatible = "ti,omap4-dpll-core-clock";
> + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
> + reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
> + <0x44e00468 0x4>;
> + reg-names = "control", "idlest", "autoidle", "mult-div1";
> + };
> +
> + dpll2_ck: dpll2_ck@48004004 {
> + #clock-cells = <0>;
> + compatible = "ti,omap3-dpll-clock";
> + clocks = <&sys_ck>, <&dpll2_fck>;
> + ti,modes = <0xa2>;
> + reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>,
> + <0x48004040 0x4>;
> + reg-names = "control", "idlest", "autoidle", "mult-div1";
> + ti,clkdm-name = "dpll2_clkdm";
> + };
Do you need the reg-names at all? You may be able to do that
automatically in the driver based on the compatible flags if
you only have few different types.
Regards,
Tony
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^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCHv6 02/45] CLK: TI: add DT alias clock registration mechanism
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
2013-08-29 13:15 ` [PATCHv6 01/45] CLK: TI: Add DPLL clock support Tero Kristo
@ 2013-08-29 13:15 ` Tero Kristo
2013-08-29 13:15 ` [PATCHv6 03/45] CLK: TI: add autoidle support Tero Kristo
` (42 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:15 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 23 +++++++++++++++++++++
3 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 93177987..05af5d8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += dpll.o
+obj-y += clk.o dpll.o
endif
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 0000000..f09798e
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,52 @@
+/*
+ * TI clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+#include <linux/of.h>
+
+/**
+ * omap_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init omap_dt_clocks_register(struct omap_dt_clk oclks[])
+{
+ struct omap_dt_clk *c;
+ struct device_node *node;
+ struct clk *clk;
+ struct of_phandle_args clkspec;
+
+ for (c = oclks; c->node_name != NULL; c++) {
+ node = of_find_node_by_name(NULL, c->node_name);
+ clkspec.np = node;
+ clk = of_clk_get_from_provider(&clkspec);
+
+ if (!IS_ERR(clk)) {
+ c->lk.clk = clk;
+ clkdev_add(&c->lk);
+ } else {
+ pr_warn("%s: failed to lookup clock node %s\n",
+ __func__, c->node_name);
+ }
+ }
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 385384a..1c4f492 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,8 @@
#ifndef __LINUX_CLK_TI_H__
#define __LINUX_CLK_TI_H__
+#include <linux/clkdev.h>
+
/**
* struct dpll_data - DPLL registers and integration data
* @mult_div1_reg: register containing the DPLL M and N bitfields
@@ -138,6 +140,25 @@ struct clk_hw_omap {
/* DPLL Type and DCO Selection Flags */
#define DPLL_J_TYPE 0x1
+/**
+ * struct omap_dt_clk - OMAP DT clock alias declarations
+ * @lk: clock lookup definition
+ * @node_name: clock DT node to map to
+ */
+struct omap_dt_clk {
+ struct clk_lookup lk;
+ char *node_name;
+};
+
+#define DT_CLK(dev, con, name) \
+ { \
+ .lk = { \
+ .dev_id = dev, \
+ .con_id = con, \
+ }, \
+ .node_name = name, \
+ }
+
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -158,6 +179,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+void omap_dt_clocks_register(struct omap_dt_clk *oclks);
+
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 03/45] CLK: TI: add autoidle support
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
2013-08-29 13:15 ` [PATCHv6 01/45] CLK: TI: Add DPLL clock support Tero Kristo
2013-08-29 13:15 ` [PATCHv6 02/45] CLK: TI: add DT alias clock registration mechanism Tero Kristo
@ 2013-08-29 13:15 ` Tero Kristo
2013-08-29 13:15 ` [PATCHv6 04/45] CLK: TI: add support for OMAP gate clock Tero Kristo
` (41 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:15 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/autoidle.txt | 48 ++++++++
arch/arm/mach-omap2/clock.c | 6 +
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/autoidle.c | 121 ++++++++++++++++++++
include/linux/clk/ti.h | 7 ++
5 files changed, 183 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/autoidle.txt
create mode 100644 drivers/clk/ti/autoidle.c
diff --git a/Documentation/devicetree/bindings/clock/ti/autoidle.txt b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
new file mode 100644
index 0000000..cc09910
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
@@ -0,0 +1,48 @@
+Binding for Texas Instruments autoidling clock.
+
+This binding uses the common clock binding[1]. Autoidle clocks
+are inherited clocks from basic divider-clock [2] or
+fixed-factor-clock [3] and just add autoidle support on top of
+this. Autoidle is an OMAP clock feature, which allows the clock
+to gate autonomously by hardware when they are no longer needed.
+The autoidle feature must be enabled manually for these clocks.
+Otherwise the clocks behave exactly as their base clock type.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/divider-clock.txt
+[3] Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,divider-clock",
+ "ti,fixed-factor-clock"
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock
+- reg : base address for the control register of this clock
+
+Optional properties:
+- ti,autoidle-low : autoidle is enabled by setting the bit to 0
+
+Other properties as per the base clock type.
+
+Examples:
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0051f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+ };
+
+ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,autoidle-shift = <8>;
+ clock-div = <1>;
+ reg = <0x4a0081b4 0x4>;
+ clock-mult = <1>;
+ ti,autoidle-low;
+ };
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..669d4c4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->allow_idle)
c->ops->allow_idle(c);
+
+ of_omap_clk_allow_autoidle_all();
+
return 0;
}
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->deny_idle)
c->ops->deny_idle(c);
+
+ of_omap_clk_deny_autoidle_all();
+
return 0;
}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 05af5d8..533efb4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o
+obj-y += clk.o dpll.o autoidle.o
endif
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
new file mode 100644
index 0000000..a52a42b
--- /dev/null
+++ b/drivers/clk/ti/autoidle.c
@@ -0,0 +1,121 @@
+/*
+ * OMAP clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+struct clk_omap_autoidle {
+ void __iomem *reg;
+ u8 shift;
+ u8 flags;
+ const char *name;
+ struct list_head node;
+};
+
+#define AUTOIDLE_LOW 0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
+{
+ u32 val;
+
+ val = readl(clk->reg);
+
+ if (clk->flags & AUTOIDLE_LOW)
+ val &= ~(1 << clk->shift);
+ else
+ val |= (1 << clk->shift);
+
+ writel(val, clk->reg);
+}
+
+static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
+{
+ u32 val;
+
+ val = readl(clk->reg);
+
+ if (clk->flags & AUTOIDLE_LOW)
+ val |= (1 << clk->shift);
+ else
+ val &= ~(1 << clk->shift);
+
+ writel(val, clk->reg);
+}
+
+void of_omap_clk_allow_autoidle_all(void)
+{
+ struct clk_omap_autoidle *c;
+
+ list_for_each_entry(c, &autoidle_clks, node)
+ omap_allow_autoidle(c);
+}
+
+void of_omap_clk_deny_autoidle_all(void)
+{
+ struct clk_omap_autoidle *c;
+
+ list_for_each_entry(c, &autoidle_clks, node)
+ omap_deny_autoidle(c);
+}
+
+static void __init of_omap_autoidle_setup(struct device_node *node)
+{
+ u32 shift;
+ void __iomem *reg;
+ struct clk_omap_autoidle *clk;
+
+ if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+ return;
+
+ reg = of_iomap(node, 0);
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+
+ if (!clk) {
+ pr_err("%s: kzalloc failed\n", __func__);
+ return;
+ }
+
+ clk->shift = shift;
+ clk->name = node->name;
+ clk->reg = reg;
+
+ if (of_property_read_bool(node, "ti,autoidle-low"))
+ clk->flags |= AUTOIDLE_LOW;
+
+ list_add(&clk->node, &autoidle_clks);
+}
+
+static void __init of_omap_divider_setup(struct device_node *node)
+{
+ of_divider_clk_setup(node);
+ of_omap_autoidle_setup(node);
+}
+CLK_OF_DECLARE(omap_divider_clock, "ti,divider-clock", of_omap_divider_setup);
+
+static void __init of_omap_fixed_factor_setup(struct device_node *node)
+{
+ of_fixed_factor_clk_setup(node);
+ of_omap_autoidle_setup(node);
+}
+CLK_OF_DECLARE(omap_fixed_factor_clock, "ti,fixed-factor-clock",
+ of_omap_fixed_factor_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 1c4f492..e2473b8 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -180,6 +180,13 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void omap_dt_clocks_register(struct omap_dt_clk *oclks);
+#ifdef CONFIG_OF
+void of_omap_clk_allow_autoidle_all(void);
+void of_omap_clk_deny_autoidle_all(void);
+#else
+static inline void of_omap_clk_allow_autoidle_all(void) { }
+static inline void of_omap_clk_deny_autoidle_all(void) { }
+#endif
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 04/45] CLK: TI: add support for OMAP gate clock
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (2 preceding siblings ...)
2013-08-29 13:15 ` [PATCHv6 03/45] CLK: TI: add autoidle support Tero Kristo
@ 2013-08-29 13:15 ` Tero Kristo
2013-08-29 13:15 ` [PATCHv6 05/45] CLK: TI: add support for clockdomain binding Tero Kristo
` (40 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:15 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/gate.txt | 73 ++++++++
arch/arm/mach-omap2/clock.h | 28 ----
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/gate.c | 174 ++++++++++++++++++++
include/linux/clk/ti.h | 35 ++++
5 files changed, 283 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
create mode 100644 drivers/clk/ti/gate.c
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 0000000..338b112
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,73 @@
+Binding for Texas Instruments gate clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,gate-clock" - basic gate clock
+ "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
+ "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
+ "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
+ clock directly from a clockdomain, see [3] how
+ to map clockdomains properly
+ "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
+ required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable gate, not needed for
+ ti,clkdm-gate-clock type
+- ti,enable-bit : bit shift for programming the clock gate, not needed for
+ ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+ gates the clock and clearing the bit ungates the clock.
+
+Examples:
+ mmchs2_fck: mmchs2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <25>;
+ };
+
+ dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,enable-bit = <0>;
+ };
+
+ emac_ick: emac_ick@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,enable-bit = <1>;
+ };
+
+ emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+ };
+
+ dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,enable-bit = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ ti,set-bit-to-disable;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 079536a..f0b7218 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -179,25 +179,6 @@ struct clksel {
const struct clksel_rate *rates;
};
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- * bits share the same register. This flag allows the
- * omap4_dpllmx*() code to determine which GATE_CTRL bit field
- * should be used. This is a temporary solution - a better approach
- * would be to associate clock type-specific data with the clock,
- * similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL (1 << 1)
-#define CLOCK_NO_IDLE_PARENT (1 << 2)
-#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
-#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2 (1 << 5)
-
struct clk_hw_omap_ops {
void (*find_idlest)(struct clk_hw_omap *oclk,
void __iomem **idlest_reg,
@@ -260,9 +241,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
void __iomem **other_reg,
u8 *other_bit);
@@ -292,15 +270,12 @@ extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
@@ -318,8 +293,5 @@ extern const struct clksel_rate div31_1to31_rates[];
extern int am33xx_clk_init(void);
-extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
-
extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
#endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..57bfbaa 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o
+obj-y += clk.o dpll.o autoidle.o gate.o
endif
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
new file mode 100644
index 0000000..c9fcbb2
--- /dev/null
+++ b/drivers/clk/ti/gate.c
@@ -0,0 +1,174 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
+
+static const struct clk_ops omap_gate_clkdm_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_clkops_enable_clkdm,
+ .disable = &omap2_clkops_disable_clkdm,
+};
+
+static const struct clk_ops omap_gate_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+/**
+ * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
+ * from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set. Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
+{
+ struct clk_divider *parent;
+ struct clk_hw *parent_hw;
+ u32 dummy_v, orig_v;
+ int ret;
+
+ /* Clear PWRDN bit of HSDIVIDER */
+ ret = omap2_dflt_clk_enable(clk);
+
+ /* Parent is the x2 node, get parent of parent for the m2 div */
+ parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
+ parent = to_clk_divider(parent_hw);
+
+ /* Restore the dividers */
+ if (!ret) {
+ orig_v = __raw_readl(parent->reg);
+ dummy_v = orig_v;
+
+ /* Write any other value different from the Read value */
+ dummy_v ^= (1 << parent->shift);
+ __raw_writel(dummy_v, parent->reg);
+
+ /* Write the original divider */
+ __raw_writel(orig_v, parent->reg);
+ }
+
+ return ret;
+}
+
+static void __init _of_omap_gate_clk_setup(struct device_node *node,
+ void __iomem *reg,
+ const struct clk_ops *ops,
+ const struct clk_hw_omap_ops *hw_ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { 0 };
+ struct clk_hw_omap *clk_hw;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 val;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return;
+ }
+
+ clk_hw->hw.init = &init;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ init.name = clk_name;
+ init.ops = ops;
+ clk_hw->enable_reg = reg;
+ if (!of_property_read_u32(node, "ti,enable-bit", &val))
+ clk_hw->enable_bit = val;
+ clk_hw->ops = hw_ops;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ if (of_property_read_bool(node, "ti,set-rate-parent"))
+ init.flags |= CLK_SET_RATE_PARENT;
+
+ if (of_property_read_bool(node, "ti,set-bit-to-disable"))
+ clk_hw->flags |= INVERT_ENABLE;
+
+ clk = clk_register(NULL, &clk_hw->hw);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+static void __init of_omap_clkdm_gate_clk_setup(struct device_node *node)
+{
+ _of_omap_gate_clk_setup(node, NULL, &omap_gate_clkdm_clk_ops, NULL);
+}
+CLK_OF_DECLARE(omap_clkdm_gate_clk, "ti,clkdm-gate-clock",
+ of_omap_clkdm_gate_clk_setup);
+
+static void __init of_omap_hsdiv_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_hsdiv_restore_ops,
+ &clkhwops_wait);
+}
+CLK_OF_DECLARE(omap_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
+ of_omap_hsdiv_gate_clk_setup);
+
+static void __init of_omap_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_ops, &clkhwops_wait);
+}
+CLK_OF_DECLARE(omap_gate_clk, "ti,gate-clock", of_omap_gate_clk_setup);
+
+static void __init of_omap_am35xx_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_ops,
+ &clkhwops_am35xx_ipss_module_wait);
+}
+CLK_OF_DECLARE(omap_am35xx_gate_clk, "ti,am35xx-gate-clock",
+ of_omap_am35xx_gate_clk_setup);
+
+static void __init of_omap_dss_gate_clk_setup(struct device_node *node)
+{
+ void __iomem *reg = of_iomap(node, 0);
+ _of_omap_gate_clk_setup(node, reg, &omap_gate_clk_ops,
+ &clkhwops_omap3430es2_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(omap_dss_gate_clk, "ti,dss-gate-clock",
+ of_omap_dss_gate_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index e2473b8..5fe2d43 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -132,6 +132,33 @@ struct clk_hw_omap {
const struct clk_hw_omap_ops *ops;
};
+/*
+ * struct clk_hw_omap.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
+ * with 32bit ops, by default OMAP1 uses 16bit ops.
+ * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
+ * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
+ * clock is put to no-idle mode.
+ * ENABLE_ON_INIT: Clock is enabled on init.
+ * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
+ * disable. This inverts the behavior making '0' enable and '1' disable.
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ * bits share the same register. This flag allows the
+ * omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ * should be used. This is a temporary solution - a better approach
+ * would be to associate clock type-specific data with the clock,
+ * similar to the struct dpll_data approach.
+ */
+#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL (1 << 1)
+#define CLOCK_NO_IDLE_PARENT (1 << 2)
+#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
+#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2 (1 << 5)
+
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP 0x1
#define DPLL_LOW_POWER_BYPASS 0x5
@@ -176,8 +203,13 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
void omap2_init_clk_clkdm(struct clk_hw *clk);
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned long parent_rate);
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+int omap2_dflt_clk_enable(struct clk_hw *hw);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap_dt_clocks_register(struct omap_dt_clk *oclks);
#ifdef CONFIG_OF
@@ -190,5 +222,8 @@ static inline void of_omap_clk_deny_autoidle_all(void) { }
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 05/45] CLK: TI: add support for clockdomain binding
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (3 preceding siblings ...)
2013-08-29 13:15 ` [PATCHv6 04/45] CLK: TI: add support for OMAP gate clock Tero Kristo
@ 2013-08-29 13:15 ` Tero Kristo
2013-08-29 13:15 ` [PATCHv6 06/45] ARM: dts: omap4 clock data Tero Kristo
` (39 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:15 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/clockdomain.txt | 19 ++++++++
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/Makefile | 3 +-
drivers/clk/ti/clockdomain.c | 46 ++++++++++++++++++++
include/linux/clk/ti.h | 2 +
5 files changed, 69 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
create mode 100644 drivers/clk/ti/clockdomain.c
diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 0000000..0dc5cd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,19 @@
+Binding for Texas Instruments clockdomain.
+
+This binding uses the common clock binding[1]. Every clock on
+TI SoC belongs to one clockdomain, but software only needs this
+information for specific clocks which require their parent
+clockdomain to be controlled when the clock is enabled/disabled.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,clockdomain"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index f0b7218..56d4664 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,7 +38,6 @@ struct omap_clk {
}
struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
static struct clk _name = { \
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 57bfbaa..21dff46 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,4 @@
ifneq ($(CONFIG_OF),)
-obj-y += clk.o dpll.o autoidle.o gate.o
+obj-y += clk.o dpll.o autoidle.o gate.o \
+ clockdomain.o
endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 0000000..bc02937
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,46 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+void __init of_omap_clockdomain_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_hw *clk_hw;
+ const char *clkdm_name = node->name;
+ int i;
+ int num_clks;
+
+ num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+
+ for (i = 0; i < num_clks; i++) {
+ clk = of_clk_get(node, i);
+ if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+ pr_warn("%s: can't setup clkdm for basic clk %s\n",
+ __func__, __clk_get_name(clk));
+ continue;
+ }
+ clk_hw = __clk_get_hw(clk);
+ to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
+ omap2_init_clk_clkdm(clk_hw);
+ }
+}
+CLK_OF_DECLARE(omap_clockdomain, "ti,clockdomain", of_omap_clockdomain_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 5fe2d43..ab73f35 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -186,6 +186,8 @@ struct omap_dt_clk {
.node_name = name, \
}
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 06/45] ARM: dts: omap4 clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (4 preceding siblings ...)
2013-08-29 13:15 ` [PATCHv6 05/45] CLK: TI: add support for clockdomain binding Tero Kristo
@ 2013-08-29 13:15 ` Tero Kristo
2013-08-29 13:15 ` [PATCHv6 07/45] CLK: TI: add omap4 clock init file Tero Kristo
` (38 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:15 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap443x-clocks.dtsi | 17 +
arch/arm/boot/dts/omap443x.dtsi | 20 +
arch/arm/boot/dts/omap4460.dtsi | 20 +
arch/arm/boot/dts/omap446x-clocks.dtsi | 27 +
arch/arm/boot/dts/omap44xx-clocks.dtsi | 1639 ++++++++++++++++++++++++++++++++
5 files changed, 1723 insertions(+)
create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..2bd82b2
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+bandgap_fclk: bandgap_fclk@4a307888 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..91eb272 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -30,4 +30,24 @@
0x4a00232C 0x4>;
compatible = "ti,omap4430-bandgap";
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap44xx-clocks.dtsi"
+ /include/ "omap443x-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..5cbdab0 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -38,4 +38,24 @@
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
gpios = <&gpio3 22 0>; /* tshut */
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap44xx-clocks.dtsi"
+ /include/ "omap446x-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3_init_clkdm: l3_init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+
+ emu_sys_clkdm: emu_sys_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&trace_clk_div_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..86d0805
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP446x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+div_ts_ck: div_ts_ck@4a307888 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ bit-shift = <24>;
+ reg = <0x4a307888 0x4>;
+ table = < 8 0 >, < 16 1 >, < 32 2 >;
+ bit-mask = <0x3>;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk@4a307888 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&div_ts_ck>;
+ bit-shift = <8>;
+ reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..190e6b4
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1639 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extalt_clkin_ck: extalt_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck@4a004108 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ bit-shift = <8>;
+ reg = <0x4a004108 0x4>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&slimbus_src_clk>;
+ bit-shift = <10>;
+ reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@4a306110 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4a306110 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a306108 0x4>;
+ bit-mask = <0x1>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ reg = <0x4a30610c 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0041e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x4a0041f0 0x4>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+abe_clk: abe_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a004108 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&abe_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f4 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@4a00412c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+ bit-shift = <23>;
+ reg = <0x4a00412c 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll_core_ck: dpll_core_ck@4a004120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck@4a004140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004140 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004130 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+ddrphy_ck: ddrphy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck@4a00413c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00413c 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+div_core_ck: div_core_ck@4a004100 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a004100 0x4>;
+ bit-mask = <0x1>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk@4a0041dc {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a0041dc 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk@4a00419c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_m5x2_ck>;
+ reg = <0x4a00419c 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck@4a004138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004138 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_ck>;
+ reg = <0x4a0041f0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@4a004134 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x4a004134 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_core_m3x2_div_ck>;
+ bit-shift = <8>;
+ reg = <0x4a004134 0x4>;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck@4a004144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004144 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@4a0041ac {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+ bit-shift = <23>;
+ reg = <0x4a0041ac 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0041a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@4a0041b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041b8 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@4a0041bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041bc 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a004160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004170 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@4a00814c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+ bit-shift = <23>;
+ reg = <0x4a00814c 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x4a008150 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x4a008150 0x4>;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@4a008154 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ reg = <0x4a008154 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m3x2_div_ck>;
+ bit-shift = <8>;
+ reg = <0x4a008154 0x4>;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck@4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck@4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck@4a008160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008160 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck@4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,autoidle-shift = <8>;
+ clock-div = <1>;
+ reg = <0x4a0081b4 0x4>;
+ clock-mult = <1>;
+ ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck@4a008100 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+ reg = <0x4a008100 0x4>;
+ bit-mask = <0x1>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+func_48m_fclk: func_48m_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x4a008108 0x4>;
+ table = < 4 0 >, < 8 1 >;
+ bit-mask = <0x1>;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_64m_fclk: func_64m_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ reg = <0x4a008108 0x4>;
+ table = < 2 0 >, < 4 1 >;
+ bit-mask = <0x1>;
+};
+
+func_96m_fclk: func_96m_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ reg = <0x4a008108 0x4>;
+ table = < 2 0 >, < 4 1 >;
+ bit-mask = <0x1>;
+};
+
+init_60m_fclk: init_60m_fclk@4a008104 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ table = < 1 0 >, < 8 1 >;
+ bit-mask = <0x1>;
+};
+
+l3_div_ck: l3_div_ck@4a004100 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&div_core_ck>;
+ bit-shift = <4>;
+ reg = <0x4a004100 0x4>;
+ bit-mask = <0x1>;
+};
+
+l4_div_ck: l4_div_ck@4a004100 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l3_div_ck>;
+ bit-shift = <8>;
+ reg = <0x4a004100 0x4>;
+ bit-mask = <0x1>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@4a306108 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+ reg = <0x4a306108 0x4>;
+ bit-mask = <0x1>;
+};
+
+mpu_periphclk: mpu_periphclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk@4a004528 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&aess_fclk>;
+ bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ table = < 2 0 >, < 1 1 >;
+ bit-mask = <0x1>;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk@4a008108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4a008108 0x4>;
+ bit-mask = <0x1>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck@4a306100 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x4a306100 0x4>;
+ bit-mask = <0x1>;
+};
+
+aes1_fck: aes1_fck@4a0095a0 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3_div_ck>;
+ bit-shift = <1>;
+ reg = <0x4a0095a0 0x4>;
+};
+
+aes2_fck: aes2_fck@4a0095a8 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3_div_ck>;
+ bit-shift = <1>;
+ reg = <0x4a0095a8 0x4>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ bit-shift = <25>;
+ reg = <0x4a004538 0x4>;
+ bit-mask = <0x1>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk@4a004538 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004538 0x4>;
+ bit-mask = <0x3>;
+};
+
+dss_sys_clk: dss_sys_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&syc_clk_div_ck>;
+ bit-shift = <10>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_tv_clk: dss_tv_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&extalt_clkin_ck>;
+ bit-shift = <11>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m5x2_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_48mc_fclk>;
+ bit-shift = <9>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_fck: dss_fck@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3_div_ck>;
+ bit-shift = <1>;
+ reg = <0x4a009120 0x4>;
+};
+
+fdif_fck: fdif_fck@4a009028 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009028 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk@4a307838 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a307838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009460 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009460 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009468 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009468 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009470 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009470 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009478 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009478 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009480 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009480 0x4>;
+};
+
+sgx_clk_mux: sgx_clk_mux@4a009220 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009220 0x4>;
+ bit-mask = <0x1>;
+};
+
+hsi_fck: hsi_fck@4a009338 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009338 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk@4a009020 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_96m_fclk>;
+ bit-shift = <8>;
+ reg = <0x4a009020 0x4>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ bit-shift = <25>;
+ reg = <0x4a004540 0x4>;
+ bit-mask = <0x1>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@4a004540 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004540 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ bit-shift = <25>;
+ reg = <0x4a004548 0x4>;
+ bit-mask = <0x1>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk@4a004548 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004548 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ bit-shift = <25>;
+ reg = <0x4a004550 0x4>;
+ bit-mask = <0x1>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk@4a004550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004550 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+ bit-shift = <25>;
+ reg = <0x4a004558 0x4>;
+ bit-mask = <0x1>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk@4a004558 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004558 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@4a0094e0 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+ bit-shift = <25>;
+ reg = <0x4a0094e0 0x4>;
+ bit-mask = <0x1>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk@4a0094e0 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+ bit-shift = <24>;
+ reg = <0x4a0094e0 0x4>;
+ bit-mask = <0x1>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk@4a009328 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+ bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+ bit-mask = <0x1>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk@4a009330 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+ bit-shift = <24>;
+ reg = <0x4a009330 0x4>;
+ bit-mask = <0x1>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_48m_fclk>;
+ bit-shift = <8>;
+ reg = <0x4a0093e0 0x4>;
+};
+
+sha2md5_fck: sha2md5_fck@4a0095c8 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3_div_ck>;
+ bit-shift = <1>;
+ reg = <0x4a0095c8 0x4>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1@4a004560 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_24m_clk>;
+ bit-shift = <9>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0@4a004560 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&abe_24m_fclk>;
+ bit-shift = <8>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2@4a004560 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&pad_clks_ck>;
+ bit-shift = <10>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&slimbus_clk>;
+ bit-shift = <11>;
+ reg = <0x4a004560 0x4>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1@4a009538 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_abe_24m_fclk>;
+ bit-shift = <9>;
+ reg = <0x4a009538 0x4>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0@4a009538 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_24mc_fclk>;
+ bit-shift = <8>;
+ reg = <0x4a009538 0x4>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk@4a009538 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&pad_slimbus_core_clks_ck>;
+ bit-shift = <10>;
+ reg = <0x4a009538 0x4>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck@4a008638 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ bit-shift = <1>;
+ reg = <0x4a008638 0x4>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck@4a008630 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ bit-shift = <1>;
+ reg = <0x4a008630 0x4>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck@4a008628 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ bit-shift = <1>;
+ reg = <0x4a008628 0x4>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux@4a307840 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a307840 0x4>;
+ bit-mask = <0x1>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux@4a009428 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009428 0x4>;
+ bit-mask = <0x1>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux@4a009430 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009430 0x4>;
+ bit-mask = <0x1>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux@4a009438 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009438 0x4>;
+ bit-mask = <0x1>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux@4a009440 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009440 0x4>;
+ bit-mask = <0x1>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux@4a009448 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009448 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer5_sync_mux: timer5_sync_mux@4a004568 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004568 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer6_sync_mux: timer6_sync_mux@4a004570 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004570 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer7_sync_mux: timer7_sync_mux@4a004578 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004578 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer8_sync_mux: timer8_sync_mux@4a004580 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004580 0x4>;
+ bit-mask = <0x1>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux@4a009450 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009450 0x4>;
+ bit-mask = <0x1>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck@4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_48mc_fclk>;
+ reg = <0x4a0093d0 0x4>;
+ bit-shift = <1>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009358 0x4>;
+ bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&utmi_p1_gfclk>;
+ bit-shift = <8>;
+ reg = <0x4a009358 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+ bit-shift = <25>;
+ reg = <0x4a009358 0x4>;
+ bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&utmi_p2_gfclk>;
+ bit-shift = <9>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&init_60m_fclk>;
+ bit-shift = <10>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ bit-shift = <13>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&init_60m_fclk>;
+ bit-shift = <11>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&init_60m_fclk>;
+ bit-shift = <12>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ bit-shift = <14>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_48mc_fclk>;
+ bit-shift = <15>;
+ reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck@4a009358 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&init_60m_fclk>;
+ bit-shift = <1>;
+ reg = <0x4a009358 0x4>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk@4a009360 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009360 0x4>;
+ bit-mask = <0x1>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk@4a009360 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&otg_60m_gfclk>;
+ bit-shift = <8>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick@4a009360 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3_div_ck>;
+ bit-shift = <0>;
+ reg = <0x4a009360 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009368 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&init_60m_fclk>;
+ bit-shift = <10>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009368 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&init_60m_fclk>;
+ bit-shift = <8>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009368 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&init_60m_fclk>;
+ bit-shift = <9>;
+ reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick@4a009368 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l4_div_ck>;
+ bit-shift = <0>;
+ reg = <0x4a009368 0x4>;
+};
+
+usim_ck: usim_ck@4a307858 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m4x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a307858 0x4>;
+ table = < 14 0 >, < 18 1 >;
+ bit-mask = <0x1>;
+};
+
+usim_fclk: usim_fclk@4a307858 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&usim_ck>;
+ bit-shift = <8>;
+ reg = <0x4a307858 0x4>;
+};
+
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+ bit-shift = <20>;
+ reg = <0x4a307a20 0x4>;
+ bit-mask = <0x3>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+ bit-shift = <22>;
+ reg = <0x4a307a20 0x4>;
+ bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&pmd_stm_clock_mux_ck>;
+ bit-shift = <27>;
+ reg = <0x4a307a20 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck@4a307a20 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ bit-shift = <24>;
+ reg = <0x4a307a20 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&trace_clk_div_div_ck>;
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck@4a30a310 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4a30a310 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck@4a30a310 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk0_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4a30a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck@4a30a310 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4a30a310 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck@4a30a314 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4a30a314 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck@4a30a314 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk1_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4a30a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck@4a30a314 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4a30a314 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck@4a30a318 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4a30a318 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck@4a30a318 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk2_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4a30a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck@4a30a318 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4a30a318 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck@4a30a31c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4a30a31c 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck@4a30a31c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk3_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4a30a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck@4a30a31c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4a30a31c 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck@4a30a320 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4a30a320 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck@4a30a320 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk4_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4a30a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck@4a30a320 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4a30a320 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk5_src_mux_ck: auxclk5_src_mux_ck@4a30a324 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4a30a324 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck@4a30a324 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk5_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4a30a324 0x4>;
+};
+
+auxclk5_ck: auxclk5_ck@4a30a324 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk5_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4a30a324 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck@4a30a210 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ bit-shift = <2>;
+ reg = <0x4a30a210 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck@4a30a214 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ bit-shift = <2>;
+ reg = <0x4a30a214 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck@4a30a218 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ bit-shift = <2>;
+ reg = <0x4a30a218 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck@4a30a21c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ bit-shift = <2>;
+ reg = <0x4a30a21c 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck@4a30a220 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ bit-shift = <2>;
+ reg = <0x4a30a220 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck@4a30a224 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+ bit-shift = <2>;
+ reg = <0x4a30a224 0x4>;
+ bit-mask = <0x7>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 07/45] CLK: TI: add omap4 clock init file
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (5 preceding siblings ...)
2013-08-29 13:15 ` [PATCHv6 06/45] ARM: dts: omap4 clock data Tero Kristo
@ 2013-08-29 13:15 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 08/45] ARM: OMAP4: remove old clock data and link in new clock init code Tero Kristo
` (37 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:15 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/clk-44xx.c | 303 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
3 files changed, 304 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-44xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 56d4664..106c5c2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
new file mode 100644
index 0000000..d18aa9f
--- /dev/null
+++ b/drivers/clk/ti/clk-44xx.c
@@ -0,0 +1,303 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Mike Turquette (mturquette@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ 98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ 960000000
+
+static struct omap_dt_clk omap44xx_clks[] = {
+ DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
+ DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+ DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+ DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+ DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
+ DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+ DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
+ DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
+ DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
+ DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
+ DT_CLK(NULL, "div_core_ck", "div_core_ck"),
+ DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
+ DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
+ DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
+ DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
+ DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+ DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
+ DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+ DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
+ DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
+ DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+ DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
+ DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
+ DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
+ DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
+ DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
+ DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
+ DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
+ DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
+ DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
+ DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
+ DT_CLK("smp_twd", NULL, "mpu_periphclk"),
+ DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
+ DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
+ DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
+ DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
+ DT_CLK(NULL, "aes1_fck", "aes1_fck"),
+ DT_CLK(NULL, "aes2_fck", "aes2_fck"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+ DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+ DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_fck", "dss_fck"),
+ DT_CLK("omapdss_dss", "ick", "dss_fck"),
+ DT_CLK(NULL, "fdif_fck", "fdif_fck"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
+ DT_CLK(NULL, "hsi_fck", "hsi_fck"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+ DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
+ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
+ DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
+ DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
+ DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
+ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
+ DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
+ DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
+ DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
+ DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+ DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
+ DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
+ DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
+ DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
+ DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
+ DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
+ DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
+ DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
+ DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
+ DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
+ DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
+ DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
+ DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
+ DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
+ DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
+ DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
+ DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
+ DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
+ DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
+ DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
+ DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
+ DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
+ DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
+ DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
+ DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
+ DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+ DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
+ DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
+ DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
+ DT_CLK(NULL, "usim_ck", "usim_ck"),
+ DT_CLK(NULL, "usim_fclk", "usim_fclk"),
+ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
+ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
+ DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+ DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+ DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+ DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+ DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+ DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+ DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+ DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+ DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+ DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+ DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+ DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+ DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+ DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+ DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
+ DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
+ DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
+ DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
+ DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
+ DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
+ DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
+ DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
+ DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
+ { .node_name = NULL },
+};
+
+int __init omap4xxx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
+
+ of_clk_init(NULL);
+
+ omap_dt_clocks_register(omap44xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ /*
+ * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
+ * state when turning the ABE clock domain. Workaround this by
+ * locking the ABE DPLL on boot.
+ * Lock the ABE DPLL in any case to avoid issues with audio.
+ */
+ abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+ sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+ abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ if (!rc)
+ rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ /*
+ * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+ * domain can transition to retention state when not in use.
+ */
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index ab73f35..cd09da9 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -207,6 +207,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned long parent_rate);
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+int omap2_clk_disable_autoidle_all(void);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
int omap2_dflt_clk_enable(struct clk_hw *hw);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 08/45] ARM: OMAP4: remove old clock data and link in new clock init code
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (6 preceding siblings ...)
2013-08-29 13:15 ` [PATCHv6 07/45] CLK: TI: add omap4 clock init file Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 09/45] ARM: dts: omap5 clock data Tero Kristo
` (36 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
OMAP4 clocks have now been moved to DT, thus remove the old data file
and use the new init code under drivers/clk/omap/clk-44xx.c.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/cclock44xx_data.c | 1730 ---------------------------------
drivers/clk/ti/Makefile | 2 +-
3 files changed, 2 insertions(+), 1732 deletions(-)
delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index afb457c..f518360 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -184,7 +184,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index 88e37a4..0000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1730 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- * Mike Turquette (mturquette@ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ 98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ 960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
- "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
- "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
- "virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
- OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
- OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
- NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
- OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
- .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
- .clk_ref = &abe_dpll_refclk_mux_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK,
- .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
- "abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap4_dpll_regm4xen_recalc,
- .round_rate = &omap4_dpll_regm4xen_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
- .hw = {
- .clk = &dpll_abe_ck,
- },
- .dpll_data = &dpll_abe_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
- "dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
- .recalc_rate = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
- .hw = {
- .clk = &dpll_abe_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
- .set_rate = &omap2_clksel_set_rate,
- .recalc_rate = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
- 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
- 0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
- OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
- OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
- OMAP4430_CM1_ABE_AESS_CLKCTRL,
- OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
- OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
- 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
- OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
- 0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
- .clk_bypass = &core_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
- "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
- .hw = {
- .clk = &dpll_core_ck,
- },
- .dpll_data = &dpll_core_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
- "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
- .hw = {
- .clk = &dpll_core_x2_ck,
- },
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_CORE,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
- 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
- OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
- 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
- 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
- 0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
- "dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
- { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
- OMAP4430_CM_DIV_M3_DPLL_CORE,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- OMAP4430_CM_DIV_M3_DPLL_CORE,
- OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
- dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
- &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
- OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
- OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
- .clk_bypass = &iva_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
- "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
- .hw = {
- .clk = &dpll_iva_ck,
- },
- .dpll_data = &dpll_iva_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
- "dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
- .hw = {
- .clk = &dpll_iva_x2_ck,
- },
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
- 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
- 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
- .clk_bypass = &div_mpu_hs_clk,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
- "sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
- .hw = {
- .clk = &dpll_mpu_ck,
- },
- .dpll_data = &dpll_mpu_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_MPU,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
- &dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
- OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
- .clk_bypass = &per_hsd_byp_clk_mux_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
- "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
- .hw = {
- .clk = &dpll_per_ck,
- },
- .dpll_data = &dpll_per_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
- "dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
- .hw = {
- .clk = &dpll_per_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
- OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
- "dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
- { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
- OMAP4430_CM_DIV_M3_DPLL_PER,
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- OMAP4430_CM_DIV_M3_DPLL_PER,
- OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
- dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
- 0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
- OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
- &dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
- .clk_bypass = &usb_hs_clk_div_ck,
- .flags = DPLL_J_TYPE,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
- .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
- .max_multiplier = 4095,
- .max_divider = 256,
- .min_divider = 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
- "sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
- .hw = {
- .clk = &dpll_usb_ck,
- },
- .dpll_data = &dpll_usb_dd,
- .clkdm_name = "l3_init_clkdm",
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
- "dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
- .hw = {
- .clk = &dpll_usb_clkdcoldo_ck,
- },
- .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
- .ops = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
- dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
- OMAP4430_CM_DIV_M2_DPLL_USB,
- OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
- "div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
- 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
- { .div = 4, .val = 0 },
- { .div = 8, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
- NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 4, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
- NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 4, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
- 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
- NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
- { .div = 1, .val = 0 },
- { .div = 8, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
- 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
- OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
- 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
- OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
- OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
- 0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
- "sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
- { .div = 2, .val = 0 },
- { .div = 1, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
- OMAP4430_CM1_ABE_AESS_CLKCTRL,
- OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
- OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
- 0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
- OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
- OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
- "sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
- dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_AES1_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_AES2_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
- { .div = 8, .val = 0 },
- { .div = 16, .val = 1 },
- { .div = 32, .val = 2 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
- NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
- OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
- OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
- 0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
- "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
- 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
- { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
- "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
- OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
- func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL,
- OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL,
- OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
- OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
- OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
- OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
- OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
- 0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
- { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
- "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
- OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
- sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
- OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
- OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCASP_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
- { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
- "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
- OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
- func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
- { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
- "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
- { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
- "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
- { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = &slimbus_clk, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
- "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
- OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
- "func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
- { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
- { .parent = &pad_clks_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
- "mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
- OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
- OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
- func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
- { .parent = &func_64m_fclk, .rates = div_1_0_rates },
- { .parent = &func_96m_fclk, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
- "func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
- OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
- hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
- OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
- hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
- OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
- &pad_slimbus_core_clks_ck, 0x0,
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
- 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &sys_32k_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
- { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
- { .parent = &sys_32k_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
- "syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
- OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
- timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
- OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
- abe_dpll_bypass_clk_mux_ck_parents,
- func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
- "func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
- .hw = {
- .clk = &usb_host_fs_fck,
- },
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
- .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
- .clkdm_name = "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
- usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
- "init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
- "init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
- &dpll_usb_m2_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
- &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
- &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
- &dpll_usb_m2_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
- "utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
- OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
- OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
- OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
- OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
- OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
- OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
- { .div = 14, .val = 0 },
- { .div = 18, .val = 1 },
- { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
- OMAP4430_CM_WKUP_USIM_CLKCTRL,
- OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
- 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
- OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
- 0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
- "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
- OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
- OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
- OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
- &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
- OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
- "pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
- { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
- { .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .set_rate = &omap2_clksel_set_rate,
- .round_rate = &omap2_clksel_round_rate,
- .init = &omap2_init_clk_clkdm,
- .enable = &omap2_clkops_enable_clkdm,
- .disable = &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
- .hw = {
- .clk = &trace_clk_div_ck,
- },
- .clkdm_name = "emu_sys_clkdm",
- .clksel = trace_clk_div_div,
- .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
- .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
- trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
- { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
- "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
- OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
- OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
- auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
- OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
- "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
- "auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
- OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
- 0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
- CLK(NULL, "div_ts_ck", &div_ts_ck),
- CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
- CLK(NULL, "bandgap_fclk", &bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
- CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
- CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
- CLK(NULL, "pad_clks_ck", &pad_clks_ck),
- CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
- CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
- CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
- CLK(NULL, "slimbus_clk", &slimbus_clk),
- CLK(NULL, "sys_32k_ck", &sys_32k_ck),
- CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
- CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
- CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
- CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
- CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
- CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
- CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
- CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
- CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
- CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
- CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
- CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
- CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
- CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
- CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
- CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
- CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
- CLK(NULL, "abe_clk", &abe_clk),
- CLK(NULL, "aess_fclk", &aess_fclk),
- CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
- CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_core_ck", &dpll_core_ck),
- CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
- CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
- CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
- CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
- CLK(NULL, "ddrphy_ck", &ddrphy_ck),
- CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
- CLK(NULL, "div_core_ck", &div_core_ck),
- CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
- CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
- CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
- CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
- CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
- CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
- CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
- CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
- CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
- CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
- CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
- CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
- CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
- CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
- CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
- CLK(NULL, "dpll_per_ck", &dpll_per_ck),
- CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
- CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
- CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
- CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
- CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
- CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
- CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
- CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
- CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
- CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
- CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
- CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
- CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
- CLK(NULL, "func_12m_fclk", &func_12m_fclk),
- CLK(NULL, "func_24m_clk", &func_24m_clk),
- CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
- CLK(NULL, "func_48m_fclk", &func_48m_fclk),
- CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
- CLK(NULL, "func_64m_fclk", &func_64m_fclk),
- CLK(NULL, "func_96m_fclk", &func_96m_fclk),
- CLK(NULL, "init_60m_fclk", &init_60m_fclk),
- CLK(NULL, "l3_div_ck", &l3_div_ck),
- CLK(NULL, "l4_div_ck", &l4_div_ck),
- CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
- CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
- CLK("smp_twd", NULL, &mpu_periphclk),
- CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
- CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
- CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
- CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
- CLK(NULL, "aes1_fck", &aes1_fck),
- CLK(NULL, "aes2_fck", &aes2_fck),
- CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
- CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
- CLK(NULL, "dss_sys_clk", &dss_sys_clk),
- CLK(NULL, "dss_tv_clk", &dss_tv_clk),
- CLK(NULL, "dss_dss_clk", &dss_dss_clk),
- CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
- CLK(NULL, "dss_fck", &dss_fck),
- CLK("omapdss_dss", "ick", &dss_fck),
- CLK(NULL, "fdif_fck", &fdif_fck),
- CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
- CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
- CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
- CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
- CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
- CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
- CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
- CLK(NULL, "hsi_fck", &hsi_fck),
- CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
- CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
- CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
- CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
- CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
- CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
- CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
- CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
- CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
- CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
- CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
- CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
- CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
- CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m),
- CLK(NULL, "sha2md5_fck", &sha2md5_fck),
- CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
- CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
- CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
- CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
- CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
- CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
- CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
- CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
- CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
- CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
- CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
- CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
- CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
- CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
- CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
- CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
- CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
- CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
- CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
- CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
- CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
- CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
- CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
- CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
- CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
- CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
- CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
- CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
- CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
- CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
- CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
- CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
- CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
- CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
- CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
- CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
- CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
- CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
- CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
- CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
- CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
- CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
- CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
- CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
- CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
- CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
- CLK(NULL, "usim_ck", &usim_ck),
- CLK(NULL, "usim_fclk", &usim_fclk),
- CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
- CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
- CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
- CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
- CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
- CLK(NULL, "auxclk0_ck", &auxclk0_ck),
- CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
- CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
- CLK(NULL, "auxclk1_ck", &auxclk1_ck),
- CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
- CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
- CLK(NULL, "auxclk2_ck", &auxclk2_ck),
- CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
- CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
- CLK(NULL, "auxclk3_ck", &auxclk3_ck),
- CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
- CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
- CLK(NULL, "auxclk4_ck", &auxclk4_ck),
- CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
- CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
- CLK(NULL, "auxclk5_ck", &auxclk5_ck),
- CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
- CLK("omap-gpmc", "fck", &dummy_ck),
- CLK("omap_i2c.1", "ick", &dummy_ck),
- CLK("omap_i2c.2", "ick", &dummy_ck),
- CLK("omap_i2c.3", "ick", &dummy_ck),
- CLK("omap_i2c.4", "ick", &dummy_ck),
- CLK(NULL, "mailboxes_ick", &dummy_ck),
- CLK("omap_hsmmc.0", "ick", &dummy_ck),
- CLK("omap_hsmmc.1", "ick", &dummy_ck),
- CLK("omap_hsmmc.2", "ick", &dummy_ck),
- CLK("omap_hsmmc.3", "ick", &dummy_ck),
- CLK("omap_hsmmc.4", "ick", &dummy_ck),
- CLK("omap-mcbsp.1", "ick", &dummy_ck),
- CLK("omap-mcbsp.2", "ick", &dummy_ck),
- CLK("omap-mcbsp.3", "ick", &dummy_ck),
- CLK("omap-mcbsp.4", "ick", &dummy_ck),
- CLK("omap2_mcspi.1", "ick", &dummy_ck),
- CLK("omap2_mcspi.2", "ick", &dummy_ck),
- CLK("omap2_mcspi.3", "ick", &dummy_ck),
- CLK("omap2_mcspi.4", "ick", &dummy_ck),
- CLK(NULL, "uart1_ick", &dummy_ck),
- CLK(NULL, "uart2_ick", &dummy_ck),
- CLK(NULL, "uart3_ick", &dummy_ck),
- CLK(NULL, "uart4_ick", &dummy_ck),
- CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
- CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
- CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
- CLK("omap_wdt", "ick", &dummy_ck),
- CLK(NULL, "timer_32k_ck", &sys_32k_ck),
- /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
- CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
- CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
- CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
- CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
- CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
- int rc;
-
- if (cpu_is_omap443x()) {
- cpu_mask = RATE_IN_4430;
- omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
- } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
- cpu_mask = RATE_IN_4460 | RATE_IN_4430;
- omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
- if (cpu_is_omap447x())
- pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
- } else {
- return 0;
- }
-
- omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
- omap2_clk_disable_autoidle_all();
-
- /*
- * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
- * state when turning the ABE clock domain. Workaround this by
- * locking the ABE DPLL on boot.
- * Lock the ABE DPLL in any case to avoid issues with audio.
- */
- rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
- if (!rc)
- rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
- if (rc)
- pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
- /*
- * Lock USB DPLL on OMAP4 devices so that the L3INIT power
- * domain can transition to retention state when not in use.
- */
- rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
- if (rc)
- pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
- return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 21dff46..b0b0a36 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o gate.o \
- clockdomain.o
+ clockdomain.o clk-44xx.o
endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 09/45] ARM: dts: omap5 clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (7 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 08/45] ARM: OMAP4: remove old clock data and link in new clock init code Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 10/45] CLK: TI: add omap5 clock init file Tero Kristo
` (35 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap5.dtsi | 14 +
arch/arm/boot/dts/omap54xx-clocks.dtsi | 1400 ++++++++++++++++++++++++++++++++
2 files changed, 1414 insertions(+)
create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e643620..59f7246 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -713,4 +713,18 @@
compatible = "ti,omap5430-bandgap";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap54xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 0000000..1ffcf0a
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1400 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+pad_clks_src_ck: pad_clks_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck@4a004108 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&pad_clks_src_ck>;
+ bit-shift = <8>;
+ reg = <0x4a004108 0x4>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&slimbus_src_clk>;
+ bit-shift = <10>;
+ reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin: sys_clkin@4ae06110 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4ae06110 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06108 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x4ae06108 0x4>;
+ bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ reg = <0x4ae0610c 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0041e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+abe_clk: abe_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a004108 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+abe_iclk: abe_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&abe_clk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f4 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck@4a004120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h21x2_ck: dpll_core_h21x2_ck@4a004150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004150 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+c2c_fclk: c2c_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h21x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+c2c_iclk: c2c_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&c2c_fclk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_h11x2_ck: dpll_core_h11x2_ck@4a004138 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004138 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00413c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00413c 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a004140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004140 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a004144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004144 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a004154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004154 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a004158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004158 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00415c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00415c 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004130 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004134 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0041a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+ reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@4a0041b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041b8 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@4a0041bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041bc 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a004160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a004170 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008154 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_unipro1_ck: dpll_unipro1_ck@4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro1_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro1_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_unipro2_ck: dpll_unipro2_ck@4a0081c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&sys_clkin>;
+ reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_unipro2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@4a0081d0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_unipro2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0081d0 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dss_syc_gfclk_div: dss_syc_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpu_l3_iclk: gpu_l3_iclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk@4a008104 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ table = < 1 0 >, < 8 1 >;
+ bit-mask = <0x1>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+ reg = <0x4ae06108 0x4>;
+ bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dss_32khz_clk: dss_32khz_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <11>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_48m_fclk>;
+ bit-shift = <9>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009420 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk@4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dss_syc_gfclk_div>;
+ bit-shift = <10>;
+ reg = <0x4a009420 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@4ae07938 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4ae07938 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009060 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009060 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009068 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009068 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009070 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009070 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009078 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009078 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009080 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009080 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk@4a009110 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009110 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk@4a009118 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009118 0x4>;
+};
+
+iss_ctrlclk: iss_ctrlclk@4a009320 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_96m_fclk>;
+ bit-shift = <8>;
+ reg = <0x4a009320 0x4>;
+};
+
+lli_txphy_clk: lli_txphy_clk@4a008f20 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_unipro1_clkdcoldo>;
+ bit-shift = <8>;
+ reg = <0x4a008f20 0x4>;
+};
+
+lli_txphy_ls_clk: lli_txphy_ls_clk@4a008f20 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_unipro1_m2_ck>;
+ bit-shift = <9>;
+ reg = <0x4a008f20 0x4>;
+};
+
+mmc1_32khz_clk: mmc1_32khz_clk@4a009628 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009628 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk@4a009688 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_clkin>;
+ bit-shift = <8>;
+ reg = <0x4a009688 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&slimbus_clk>;
+ bit-shift = <11>;
+ reg = <0x4a004560 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ bit-shift = <13>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ bit-shift = <14>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ bit-shift = <7>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ bit-shift = <11>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ bit-shift = <12>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ bit-shift = <6>;
+ reg = <0x4a009658 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009658 0x4>;
+ bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&utmi_p1_gfclk>;
+ bit-shift = <8>;
+ reg = <0x4a009658 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+ bit-shift = <25>;
+ reg = <0x4a009658 0x4>;
+ bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&utmi_p2_gfclk>;
+ bit-shift = <9>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ bit-shift = <10>;
+ reg = <0x4a009658 0x4>;
+};
+
+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@4a0096f0 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ bit-shift = <8>;
+ reg = <0x4a0096f0 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009668 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ bit-shift = <8>;
+ reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009668 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ bit-shift = <9>;
+ reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009668 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
+ bit-shift = <10>;
+ reg = <0x4a009668 0x4>;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&abe_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ bit-mask = <0x1>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ bit-shift = <26>;
+ reg = <0x4a004538 0x4>;
+ bit-mask = <0x3>;
+};
+
+dmic_gfclk: dmic_gfclk@4a004538 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004538 0x4>;
+ bit-mask = <0x3>;
+};
+
+fdif_fclk: fdif_fclk@4a009328 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009520 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009520 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009520 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+ bit-shift = <25>;
+ reg = <0x4a009520 0x4>;
+ bit-mask = <0x1>;
+};
+
+hsi_fclk: hsi_fclk@4a009638 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009638 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ bit-shift = <26>;
+ reg = <0x4a004540 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp_gfclk: mcasp_gfclk@4a004540 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004540 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ bit-shift = <26>;
+ reg = <0x4a004548 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp1_gfclk: mcbsp1_gfclk@4a004548 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004548 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ bit-shift = <26>;
+ reg = <0x4a004550 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp2_gfclk: mcbsp2_gfclk@4a004550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004550 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+ bit-shift = <26>;
+ reg = <0x4a004558 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcbsp3_gfclk: mcbsp3_gfclk@4a004558 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004558 0x4>;
+ bit-mask = <0x3>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux@4a009628 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009628 0x4>;
+ bit-mask = <0x1>;
+};
+
+mmc1_fclk: mmc1_fclk@4a009628 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ bit-shift = <25>;
+ reg = <0x4a009628 0x4>;
+ bit-mask = <0x1>;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux@4a009630 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009630 0x4>;
+ bit-mask = <0x1>;
+};
+
+mmc2_fclk: mmc2_fclk@4a009630 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ bit-shift = <25>;
+ reg = <0x4a009630 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux@4a009028 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009028 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux@4a009030 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009030 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux@4ae07940 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4ae07940 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux@4a009038 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009038 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux@4a009040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009040 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux@4a009048 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009048 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux@4a004568 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004568 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux@4a004570 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004570 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux@4a004578 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004578 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux@4a004580 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a004580 0x4>;
+ bit-mask = <0x1>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux@4a009050 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009050 0x4>;
+ bit-mask = <0x1>;
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck@4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4ae0a310 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck@4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk0_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4ae0a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck@4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk0_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4ae0a310 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck@4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4ae0a314 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck@4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk1_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4ae0a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck@4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk1_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4ae0a314 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck@4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4ae0a318 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck@4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk2_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4ae0a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck@4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk2_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4ae0a318 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck@4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4ae0a31c 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck@4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk3_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4ae0a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck@4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk3_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4ae0a31c 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck@4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+ bit-shift = <1>;
+ reg = <0x4ae0a320 0x4>;
+ bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck@4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk4_src_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x4ae0a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck@4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk4_src_ck>;
+ bit-shift = <16>;
+ reg = <0x4ae0a320 0x4>;
+ bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck@4ae0a210 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ bit-shift = <2>;
+ reg = <0x4ae0a210 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck@4ae0a214 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ bit-shift = <2>;
+ reg = <0x4ae0a214 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck@4ae0a218 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ bit-shift = <2>;
+ reg = <0x4ae0a218 0x4>;
+ bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck@4ae0a21c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+ bit-shift = <2>;
+ reg = <0x4ae0a21c 0x4>;
+ bit-mask = <0x7>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 10/45] CLK: TI: add omap5 clock init file
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (8 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 09/45] ARM: dts: omap5 clock data Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 11/45] CLK: TI: omap5: Initialize USB_DPLL at boot Tero Kristo
` (34 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/io.c | 1 +
drivers/clk/ti/Makefile | 3 +-
drivers/clk/ti/clk-54xx.c | 215 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 2 +
4 files changed, 220 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-54xx.c
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ff2113c..205bb1d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -650,6 +650,7 @@ void __init omap5_init_early(void)
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_clk_init = omap5xxx_clk_init;
}
#endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index b0b0a36..36e4afc 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o gate.o \
- clockdomain.o clk-44xx.o
+ clockdomain.o clk-44xx.o \
+ clk-54xx.o
endif
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
new file mode 100644
index 0000000..bf9dc00
--- /dev/null
+++ b/drivers/clk/ti/clk-54xx.c
@@ -0,0 +1,215 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/ti.h>
+
+#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+
+static struct omap_dt_clk omap54xx_clks[] = {
+ DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+ DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+ DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin", "sys_clkin"),
+ DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+ DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "abe_iclk", "abe_iclk"),
+ DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
+ DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
+ DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
+ DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+ DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
+ DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+ DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+ DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+ DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+ DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+ DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+ DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+ DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
+ DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
+ DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+ DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+ DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
+ DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
+ DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
+ DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
+ DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
+ DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
+ DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
+ DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
+ DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+ DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
+ DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+ DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+ DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+ DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+ DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
+ DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
+ DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
+ DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
+ DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
+ DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
+ DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
+ DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
+ DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
+ DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+ DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+ DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
+ DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
+ DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+ DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
+ DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
+ DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
+ DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
+ DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
+ DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
+ DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
+ DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
+ DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
+ DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
+ DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
+ DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
+ DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
+ DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+ { .node_name = NULL },
+};
+
+int __init omap5xxx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+
+ of_clk_init(NULL);
+
+ omap_dt_clocks_register(omap54xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
+ sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+ abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ if (!rc)
+ rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index cd09da9..31ecf99 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -223,6 +223,8 @@ static inline void of_omap_clk_allow_autoidle_all(void) { }
static inline void of_omap_clk_deny_autoidle_all(void) { }
#endif
+int omap5xxx_clk_init(void);
+
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 11/45] CLK: TI: omap5: Initialize USB_DPLL at boot
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (9 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 10/45] CLK: TI: add omap5 clock init file Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 12/45] ARM: dts: dra7 clock data Tero Kristo
` (33 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree, Roger Quadros
From: Roger Quadros <rogerq@ti.com>
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-54xx.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index bf9dc00..b1163b7 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -19,6 +19,12 @@
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+/*
+ * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ 960000000
+
static struct omap_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
@@ -194,7 +200,7 @@ static struct omap_dt_clk omap54xx_clks[] = {
int __init omap5xxx_clk_init(void)
{
int rc;
- struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+ struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
of_clk_init(NULL);
@@ -211,5 +217,15 @@ int __init omap5xxx_clk_init(void)
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
+ rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
+ if (rc)
+ pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 12/45] ARM: dts: dra7 clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (10 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 11/45] CLK: TI: omap5: Initialize USB_DPLL at boot Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 13/45] ARM: dts: clk: Add apll related clocks Tero Kristo
` (32 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).
TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 2058 ++++++++++++++++++++++++++++++++++
1 file changed, 2058 insertions(+)
create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..ce9bbbb
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2058 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+atl_clkin0_ck: atl_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atl_clkin1_ck: atl_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atl_clkin2_ck: atl_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+atlclkin3_ck: atlclkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+hdmi_clkin_ck: hdmi_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+mlb_clkin_ck: mlb_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+mlbp_clkin_ck: mlbp_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+};
+
+ref_clkin0_ck: ref_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin1_ck: ref_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin2_ck: ref_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+ref_clkin3_ck: ref_clkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+rmii_clk_ck: rmii_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+sdvenc_clkin_ck: sdvenc_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_20000000_ck: virt_20000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+sys_clkin1: sys_clkin1@4ae06110 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x4ae06110 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+sys_clkin2: sys_clkin2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22579200>;
+};
+
+usb_otg_clkin_ck: usb_otg_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video1_clkin_ck: video1_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video1_m2_clkin_ck: video1_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video2_clkin_ck: video2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+video2_m2_clkin_ck: video2_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+};
+
+abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@4ae06118 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae06118 0x4>;
+ bit-mask = <0x1>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06114 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x4ae06114 0x4>;
+ bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x4ae0610c 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0051e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0051f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk@4ae0611c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4ae0611c 0x4>;
+ table = < 8 0 >, < 16 1 >;
+ bit-mask = <0x1>;
+};
+
+abe_clk: abe_clk@4a005108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a005108 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+aess_fclk: aess_fclk@4ae06178 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&abe_clk>;
+ reg = <0x4ae06178 0x4>;
+ bit-mask = <0x1>;
+};
+
+abe_giclk_div: abe_giclk_div@4ae06174 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&aess_fclk>;
+ reg = <0x4ae06174 0x4>;
+ bit-mask = <0x1>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div@4ae061d8 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4ae061d8 0x4>;
+ table = < 16 0 >, < 32 1 >;
+ bit-mask = <0x1>;
+};
+
+abe_sys_clk_div: abe_sys_clk_div@4ae06120 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06120 0x4>;
+ bit-mask = <0x1>;
+};
+
+adc_gfclk_mux: adc_gfclk_mux@4ae061dc {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+ reg = <0x4ae061dc 0x4>;
+ bit-mask = <0x7>;
+};
+
+dpll_pcie_ref_ck: dpll_pcie_ref_ck@4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin1>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+apll_pcie_ck: apll_pcie_ck@4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008224 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae061c8 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+sys_clk2_dclk_div: sys_clk2_dclk_div@4ae061cc {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin2>;
+ reg = <0x4ae061cc 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0051f0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+per_abe_x1_dclk_div: per_abe_x1_dclk_div@4ae061bc {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4ae061bc 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0051f4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051f4 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck@4a005120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00513c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00513c 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a005160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a005170 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005170 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mpu_dclk_div: mpu_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_dsp_ck: dpll_dsp_ck@4a005234 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+ reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_dsp_m2_ck: dpll_dsp_m2_ck@4a005244 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005244 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dsp_gclk_div: dsp_gclk_div@4ae0618c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_dsp_m2_ck>;
+ reg = <0x4ae0618c 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0051a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+ reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_iva_m2_ck: dpll_iva_m2_ck@4a0051b0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0051b0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+iva_dclk: iva_dclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_iva_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_gpu_ck: dpll_gpu_ck@4a0052d8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_gpu_m2_ck: dpll_gpu_m2_ck@4a0052e8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052e8 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+gpu_dclk: gpu_dclk@4ae061a0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_gpu_m2_ck>;
+ reg = <0x4ae061a0 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a005130 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005130 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@4a005210 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a005220 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005220 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+emif_phy_dclk_div: emif_phy_dclk_div@4ae06190 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ reg = <0x4ae06190 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+dpll_gmac_ck: dpll_gmac_ck@4a0052a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_gmac_m2_ck: dpll_gmac_m2_ck@4a0052b8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052b8 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+gmac_250m_dclk_div: gmac_250m_dclk_div@4ae0619c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ reg = <0x4ae0619c 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+video2_dclk_div: video2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_dclk_div: video1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_dclk_div: hdmi_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+ reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+ reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008190 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+l3init_480m_dclk_div: l3init_480m_dclk_div@4ae061ac {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4ae061ac 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+usb_otg_dclk_div: usb_otg_dclk_div@4ae06184 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&usb_otg_clkin_ck>;
+ reg = <0x4ae06184 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+sata_dclk_div: sata_dclk_div@4ae061c0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae061c0 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@4a008210 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008210 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+pcie2_dclk_div: pcie2_dclk_div@4ae061b8 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_pcie_ref_m2_ck>;
+ reg = <0x4ae061b8 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+pcie_dclk_div: pcie_dclk_div@4ae061b4 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&apll_pcie_m2_ck>;
+ reg = <0x4ae061b4 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+emu_dclk_div: emu_dclk_div@4ae06194 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06194 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+secure_32k_dclk_div: secure_32k_dclk_div@4ae061c4 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&secure_32k_clk_src_ck>;
+ reg = <0x4ae061c4 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_eve_ck: dpll_eve_ck@4a005284 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+ reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+};
+
+dpll_eve_m2_ck: dpll_eve_m2_ck@4a005294 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_eve_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005294 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+eve_dclk_div: eve_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_eve_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clkoutmux0_clk_mux: clkoutmux0_clk_mux@4ae06158 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae06158 0x4>;
+ bit-mask = <0x1f>;
+};
+
+clkoutmux1_clk_mux: clkoutmux1_clk_mux@4ae0615c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae0615c 0x4>;
+ bit-mask = <0x1f>;
+};
+
+clkoutmux2_clk_mux: clkoutmux2_clk_mux@4ae06160 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x4ae06160 0x4>;
+ bit-mask = <0x1f>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a005140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005140 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a005144 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005144 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a005154 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005154 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a005158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005158 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00515c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00515c 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@4a005228 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005228 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_dsp_ck>;
+};
+
+dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@4a005248 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a005248 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_gmac_ck>;
+};
+
+dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@4a0052c0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c0 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@4a0052c4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c4 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@4a0052c8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052c8 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@4a0052bc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0052bc 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008158 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a00815c 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h13x2_ck: dpll_per_h13x2_ck@4a008160 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008160 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008164 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a008150 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+eve_clk: eve_clk@4ae06180 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+ reg = <0x4ae06180 0x4>;
+ bit-mask = <0x1>;
+};
+
+func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gmii_m_clk_div: gmii_m_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_gmac_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hdmi_clk2_div: hdmi_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_div_clk: hdmi_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@4ae061a4 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061a4 0x4>;
+ bit-mask = <0x7>;
+};
+
+l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk@4a008104 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x4a008104 0x4>;
+ table = < 1 0 >, < 8 1 >;
+ bit-mask = <0x1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mlb_clk: mlb_clk@4ae06134 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mlb_clkin_ck>;
+ reg = <0x4ae06134 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+mlbp_clk: mlbp_clk@4ae06130 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mlbp_clkin_ck>;
+ reg = <0x4ae06130 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@4ae06138 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ reg = <0x4ae06138 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+timer_sys_clk_div: timer_sys_clk_div@4ae06144 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x4ae06144 0x4>;
+ bit-mask = <0x1>;
+};
+
+video1_clk2_div: video1_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_div_clk: video1_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video1_dpll_clk_mux: video1_dpll_clk_mux@4ae061d0 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061d0 0x4>;
+ bit-mask = <0x7>;
+};
+
+video2_clk2_div: video2_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video2_div_clk: video2_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+video2_dpll_clk_mux: video2_dpll_clk_mux@4ae061d4 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x4ae061d4 0x4>;
+ bit-mask = <0x7>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+ reg = <0x4ae06108 0x4>;
+ bit-mask = <0x1>;
+};
+
+dss_32khz_clk: dss_32khz_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <11>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_48m_fclk>;
+ bit-shift = <9>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_hdmi_clk: dss_hdmi_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&hdmi_dpll_clk_mux>;
+ bit-shift = <10>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_video1_clk: dss_video1_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&video1_dpll_clk_mux>;
+ bit-shift = <12>;
+ reg = <0x4a009120 0x4>;
+};
+
+dss_video2_clk: dss_video2_clk@4a009120 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&video2_dpll_clk_mux>;
+ bit-shift = <13>;
+ reg = <0x4a009120 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@4ae07838 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4ae07838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009760 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009760 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009768 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009768 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009770 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009770 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009778 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009778 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009780 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009780 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk@4a009810 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009810 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk@4a009818 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009818 0x4>;
+};
+
+mmc1_clk32k: mmc1_clk32k@4a009328 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009328 0x4>;
+};
+
+mmc2_clk32k: mmc2_clk32k@4a009330 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009330 0x4>;
+};
+
+mmc3_clk32k: mmc3_clk32k@4a009820 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009820 0x4>;
+};
+
+mmc4_clk32k: mmc4_clk32k@4a009828 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a009828 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk@4a009388 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_clkin1>;
+ bit-shift = <8>;
+ reg = <0x4a009388 0x4>;
+};
+
+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@4a0093f0 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ bit-shift = <8>;
+ reg = <0x4a0093f0 0x4>;
+};
+
+usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@4a009340 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ bit-shift = <8>;
+ reg = <0x4a009340 0x4>;
+};
+
+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@4a008640 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a008640 0x4>;
+};
+
+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@4a008688 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a008688 0x4>;
+};
+
+usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@4a008698 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a008698 0x4>;
+};
+
+atl_dpll_clk_mux: atl_dpll_clk_mux@4a008c00 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+ bit-shift = <24>;
+ reg = <0x4a008c00 0x4>;
+ bit-mask = <0x3>;
+};
+
+atl_gfclk_mux: atl_gfclk_mux@4a008c00 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+ bit-shift = <26>;
+ reg = <0x4a008c00 0x4>;
+ bit-mask = <0x3>;
+};
+
+dcan1_sys_clk_mux: dcan1_sys_clk_mux@4ae07888 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ bit-shift = <24>;
+ reg = <0x4ae07888 0x4>;
+ bit-mask = <0x1>;
+};
+
+gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a0093d0 0x4>;
+ table = < 2 0 >;
+ bit-mask = <0x1>;
+};
+
+gmac_rft_clk_mux: gmac_rft_clk_mux@4a0093d0 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+ bit-shift = <25>;
+ reg = <0x4a0093d0 0x4>;
+ bit-mask = <0x7>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009220 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009220 0x4>;
+ bit-mask = <0x3>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009220 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ bit-shift = <26>;
+ reg = <0x4a009220 0x4>;
+ bit-mask = <0x3>;
+};
+
+ipu1_gfclk_mux: ipu1_gfclk_mux@4a005520 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a005520 0x4>;
+ bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div@4a008e50 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ bit-shift = <24>;
+ reg = <0x4a008e50 0x4>;
+ table = < 8 0 >, < 16 1 >, < 32 2 >;
+ bit-mask = <0x3>;
+};
+
+mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@4a005550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <28>;
+ reg = <0x4a005550 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@4a005550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <24>;
+ reg = <0x4a005550 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@4a005550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <22>;
+ reg = <0x4a005550 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@4a009860 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <28>;
+ reg = <0x4a009860 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@4a009860 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <28>;
+ reg = <0x4a009860 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@4a009860 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <22>;
+ reg = <0x4a009860 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@4a009868 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009868 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@4a009868 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <22>;
+ reg = <0x4a009868 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@4a009898 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009898 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@4a009898 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <22>;
+ reg = <0x4a009898 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@4a009878 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009878 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@4a009878 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <22>;
+ reg = <0x4a009878 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@4a009904 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009904 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@4a009904 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <22>;
+ reg = <0x4a009904 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@4a009908 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009908 0x4>;
+ bit-mask = <0xf>;
+};
+
+mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@4a009908 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <22>;
+ reg = <0x4a009908 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp8_ahclk_mux: mcasp8_ahclk_mux@4a009890 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ bit-shift = <22>;
+ reg = <0x4a009890 0x4>;
+ bit-mask = <0x3>;
+};
+
+mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@4a009890 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ bit-shift = <24>;
+ reg = <0x4a009890 0x4>;
+ bit-mask = <0xf>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux@4a009328 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009328 0x4>;
+ bit-mask = <0x1>;
+};
+
+mmc1_fclk_div: mmc1_fclk_div@4a009328 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ bit-shift = <25>;
+ reg = <0x4a009328 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux@4a009330 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009330 0x4>;
+ bit-mask = <0x1>;
+};
+
+mmc2_fclk_div: mmc2_fclk_div@4a009330 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ bit-shift = <25>;
+ reg = <0x4a009330 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+mmc3_gfclk_mux: mmc3_gfclk_mux@4a009820 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009820 0x4>;
+ bit-mask = <0x1>;
+};
+
+mmc3_gfclk_div: mmc3_gfclk_div@4a009820 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc3_gfclk_mux>;
+ bit-shift = <25>;
+ reg = <0x4a009820 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+mmc4_gfclk_mux: mmc4_gfclk_mux@4a009828 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009828 0x4>;
+ bit-mask = <0x1>;
+};
+
+mmc4_gfclk_div: mmc4_gfclk_div@4a009828 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc4_gfclk_mux>;
+ bit-shift = <25>;
+ reg = <0x4a009828 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+qspi_gfclk_mux: qspi_gfclk_mux@4a009838 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009838 0x4>;
+ bit-mask = <0x1>;
+};
+
+qspi_gfclk_div: qspi_gfclk_div@4a009838 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&qspi_gfclk_mux>;
+ bit-shift = <25>;
+ reg = <0x4a009838 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux@4a009728 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009728 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux@4a009730 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009730 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer13_gfclk_mux: timer13_gfclk_mux@4a0097c8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a0097c8 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer14_gfclk_mux: timer14_gfclk_mux@4a0097d0 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a0097d0 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer15_gfclk_mux: timer15_gfclk_mux@4a0097d8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a0097d8 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer16_gfclk_mux: timer16_gfclk_mux@4a009830 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009830 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux@4ae07840 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4ae07840 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux@4a009738 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009738 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux@4a009740 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009740 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux@4a009748 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009748 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux@4a005558 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ bit-shift = <24>;
+ reg = <0x4a005558 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux@4a005560 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ bit-shift = <24>;
+ reg = <0x4a005560 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux@4a005568 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ bit-shift = <24>;
+ reg = <0x4a005568 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux@4a005570 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ bit-shift = <24>;
+ reg = <0x4a005570 0x4>;
+ bit-mask = <0xf>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux@4a009750 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ bit-shift = <24>;
+ reg = <0x4a009750 0x4>;
+ bit-mask = <0xf>;
+};
+
+uart10_gfclk_mux: uart10_gfclk_mux@4ae07880 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4ae07880 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart1_gfclk_mux: uart1_gfclk_mux@4a009840 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009840 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart2_gfclk_mux: uart2_gfclk_mux@4a009848 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009848 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart3_gfclk_mux: uart3_gfclk_mux@4a009850 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009850 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart4_gfclk_mux: uart4_gfclk_mux@4a009858 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009858 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart5_gfclk_mux: uart5_gfclk_mux@4a009870 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009870 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart6_gfclk_mux: uart6_gfclk_mux@4a005580 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a005580 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart7_gfclk_mux: uart7_gfclk_mux@4a0098d0 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a0098d0 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart8_gfclk_mux: uart8_gfclk_mux@4a0098e0 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a0098e0 0x4>;
+ bit-mask = <0x1>;
+};
+
+uart9_gfclk_mux: uart9_gfclk_mux@4a0098e8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a0098e8 0x4>;
+ bit-mask = <0x1>;
+};
+
+vip1_gclk_mux: vip1_gclk_mux@4a009020 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009020 0x4>;
+ bit-mask = <0x1>;
+};
+
+vip2_gclk_mux: vip2_gclk_mux@4a009028 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009028 0x4>;
+ bit-mask = <0x1>;
+};
+
+vip3_gclk_mux: vip3_gclk_mux@4a009030 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ bit-shift = <24>;
+ reg = <0x4a009030 0x4>;
+ bit-mask = <0x1>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 13/45] ARM: dts: clk: Add apll related clocks
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (11 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 12/45] ARM: dts: dra7 clock data Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 14/45] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock Tero Kristo
` (31 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree, Keerthy
From: Keerthy <j-keerthy@ti.com>
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index ce9bbbb..17340cc 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -324,12 +324,20 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 {
ti,autoidle-low;
};
+apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ compatible = "mux-clock";
+ clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a00821c 0x4>;
+ bit-mask = <0x80>;
+};
+
apll_pcie_ck: apll_pcie_ck@4a008200 {
#clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
- reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
- reg-names = "control", "idlest", "autoidle", "mult-div1";
+ compatible = "ti,dra7-apll-clock";
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+ reg-names = "control", "idlest";
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 14/45] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (12 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 13/45] ARM: dts: clk: Add apll related clocks Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 15/45] ARM: dts: DRA7: Add PCIe related clock nodes Tero Kristo
` (30 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree, Keerthy
From: Keerthy <j-keerthy@ti.com>
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 17340cc..397a60a 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -358,13 +358,10 @@ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 {
#clock-cells = <0>;
- compatible = "ti,divider-clock";
+ compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
- ti,autoidle-shift = <8>;
- reg = <0x4a008224 0x4>;
- bit-mask = <0x7f>;
- index-starts-at-one;
- ti,autoidle-low;
+ clock-mult = <1>;
+ clock-div = <1>;
};
sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 15/45] ARM: dts: DRA7: Add PCIe related clock nodes
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (13 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 14/45] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 16/45] CLK: TI: DRA7: Add APLL support Tero Kristo
` (29 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree, Keerthy
From: Keerthy <j-keerthy@ti.com>
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 397a60a..6a53d3b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -2061,3 +2061,27 @@ vip3_gclk_mux: vip3_gclk_mux@4a009030 {
reg = <0x4a009030 0x4>;
bit-mask = <0x1>;
};
+
+optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ compatible = "divider-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a00821c 0x4>;
+ bit-mask = <0x100>;
+};
+
+optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+ compatible = "gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ bit-shift = <9>;
+};
+
+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+ compatible = "gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ bit-shift = <10>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 16/45] CLK: TI: DRA7: Add APLL support
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (14 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 15/45] ARM: dts: DRA7: Add PCIe related clock nodes Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 17/45] CLK: TI: add dra7 clock init file Tero Kristo
` (28 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree, Keerthy
From: Keerthy <j-keerthy@ti.com>
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/apll.txt | 33 +++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/apll.c | 212 ++++++++++++++++++++
3 files changed, 246 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
create mode 100644 drivers/clk/ti/apll.c
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 0000000..ad0c13b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,33 @@
+Binding for Texas Instruments APLL clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be "ti,dra7-apll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the APLL.
+ It contains the information of registers in the same order as described by
+ reg-names.
+- reg-names: array of the register names for controlling the device, sorted
+ in the same order as the reg property.
+ "control" - contains the control register base address
+ "idlest" - contains the idlest register base address
+
+Examples:
+ apll_pcie_ck: apll_pcie_ck@4a008200 {
+ #clock-cells = <0>;
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+ reg-names = "control", "idlest";
+ compatible = "ti,dra7-apll-clock";
+ };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 36e4afc..2d4479c 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o gate.o \
- clockdomain.o clk-44xx.o \
+ clockdomain.o apll.o clk-44xx.o \
clk-54xx.o
endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 0000000..8590eba
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,212 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy <j-keerthy@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE 0x2
+#define MAX_APLL_WAIT_TRIES 1000000
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ int r = 0, i = 0;
+ struct dpll_data *ad;
+ const char *clk_name;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk->dpll_data;
+ if (!ad)
+ return -EINVAL;
+
+ clk_name = __clk_get_name(clk->hw.clk);
+
+ state <<= __ffs(ad->idlest_mask);
+
+ /* Check is already locked */
+ if ((readl(ad->idlest_reg) & ad->idlest_mask) == state)
+ return r;
+
+ v = readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+ writel(v, ad->control_reg);
+
+ state <<= __ffs(ad->idlest_mask);
+
+ while (((readl(ad->idlest_reg) & ad->idlest_mask) != state) &&
+ i < MAX_APLL_WAIT_TRIES) {
+ i++;
+ udelay(1);
+ }
+
+ if (i == MAX_APLL_WAIT_TRIES) {
+ pr_warn("clock: %s failed transition to '%s'\n",
+ clk_name, (state) ? "locked" : "bypassed");
+ } else {
+ pr_debug("clock: %s transition to '%s' in %d loops\n",
+ clk_name, (state) ? "locked" : "bypassed", i);
+
+ r = 0;
+ }
+
+ return r;
+}
+
+static void dra7_apll_disable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *ad;
+ u8 state = 1;
+ u32 v;
+
+ ad = clk->dpll_data;
+
+ state <<= __ffs(ad->idlest_mask);
+
+ v = readl(ad->control_reg);
+ v &= ~ad->enable_mask;
+ v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
+ writel(v, ad->control_reg);
+}
+
+static u8 dra7_init_apll_parent(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static const struct clk_ops apll_ck_ops = {
+ .enable = &dra7_apll_enable,
+ .disable = &dra7_apll_disable,
+ .get_parent = &dra7_init_apll_parent,
+};
+
+static struct clk *omap_clk_register_apll(struct device *dev, const char *name,
+ const char **parent_names, int num_parents, unsigned long flags,
+ struct dpll_data *dpll_data, const char *clkdm_name,
+ const struct clk_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { 0 };
+ struct clk_hw_omap *clk_hw;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ clk_hw->dpll_data = dpll_data;
+ clk_hw->hw.init = &init;
+
+ init.name = name;
+ init.ops = ops;
+ init.flags = flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* register the clock */
+ clk = clk_register(dev, &clk_hw->hw);
+
+ return clk;
+}
+
+void __init of_dra7_apll_setup(struct device_node *node)
+{
+ const struct clk_ops *ops;
+ struct clk *clk;
+ const char *clk_name = node->name;
+ int num_parents;
+ const char **parent_names = NULL;
+ u8 apll_flags = 0;
+ struct dpll_data *ad;
+ u32 idlest_mask = 0x1;
+ u32 autoidle_mask = 0x3;
+ int i;
+
+ ops = &apll_ck_ops;
+ ad = kzalloc(sizeof(*ad), GFP_KERNEL);
+ if (!ad) {
+ pr_err("%s: could not allocate dpll_data\n", __func__);
+ return;
+ }
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: omap dpll %s must have parent(s)\n",
+ __func__, node->name);
+ goto cleanup;
+ }
+
+ parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ ad->clk_ref = of_clk_get(node, 0);
+ ad->clk_bypass = of_clk_get(node, 1);
+
+ if (IS_ERR(ad->clk_ref)) {
+ pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ if (IS_ERR(ad->clk_bypass)) {
+ pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+ clk_name);
+ goto cleanup;
+ }
+
+ i = of_property_match_string(node, "reg-names", "control");
+ if (i >= 0)
+ ad->control_reg = of_iomap(node, i);
+
+ i = of_property_match_string(node, "reg-names", "idlest");
+ if (i >= 0)
+ ad->idlest_reg = of_iomap(node, i);
+
+ ad->idlest_mask = idlest_mask;
+ ad->enable_mask = autoidle_mask;
+
+ clk = omap_clk_register_apll(NULL, clk_name, parent_names,
+ num_parents, apll_flags, ad,
+ NULL, ops);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+cleanup:
+ kfree(parent_names);
+ kfree(ad);
+ return;
+}
+CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 17/45] CLK: TI: add dra7 clock init file
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (15 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 16/45] CLK: TI: DRA7: Add APLL support Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 18/45] CLK: DT: add support for set-rate-parent flag Tero Kristo
` (27 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk-7xx.c | 308 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 309 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-7xx.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 2d4479c..e612055 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o gate.o \
clockdomain.o apll.o clk-44xx.o \
- clk-54xx.o
+ clk-54xx.o clk-7xx.o
endif
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
new file mode 100644
index 0000000..c2fbc47
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx.c
@@ -0,0 +1,308 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+
+
+static struct omap_dt_clk dra7xx_clks[] = {
+ DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
+ DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
+ DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
+ DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"),
+ DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
+ DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
+ DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
+ DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
+ DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
+ DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
+ DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
+ DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
+ DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
+ DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
+ DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+ DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+ DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
+ DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
+ DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
+ DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
+ DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
+ DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
+ DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
+ DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
+ DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
+ DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
+ DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
+ DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+ DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+ DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+ DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+ DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+ DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+ DT_CLK(NULL, "abe_clk", "abe_clk"),
+ DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+ DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
+ DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+ DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
+ DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
+ DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
+ DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
+ DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
+ DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
+ DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
+ DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
+ DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
+ DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
+ DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+ DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
+ DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+ DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
+ DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
+ DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
+ DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
+ DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+ DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
+ DT_CLK(NULL, "iva_dclk", "iva_dclk"),
+ DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
+ DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
+ DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
+ DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+ DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
+ DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
+ DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
+ DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
+ DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
+ DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
+ DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
+ DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
+ DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
+ DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
+ DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
+ DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
+ DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
+ DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
+ DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
+ DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
+ DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
+ DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
+ DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
+ DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
+ DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
+ DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
+ DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
+ DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
+ DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
+ DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+ DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+ DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+ DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+ DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+ DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
+ DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
+ DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
+ DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
+ DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
+ DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
+ DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
+ DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
+ DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
+ DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
+ DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
+ DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
+ DT_CLK(NULL, "eve_clk", "eve_clk"),
+ DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
+ DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
+ DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
+ DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
+ DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
+ DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
+ DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
+ DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
+ DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
+ DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
+ DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
+ DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
+ DT_CLK(NULL, "mlb_clk", "mlb_clk"),
+ DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
+ DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
+ DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
+ DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
+ DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
+ DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
+ DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
+ DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
+ DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
+ DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
+ DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
+ DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
+ DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
+ DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
+ DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
+ DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
+ DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
+ DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
+ DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
+ DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
+ DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
+ DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
+ DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
+ DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
+ DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
+ DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
+ DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
+ DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
+ DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
+ DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
+ DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"),
+ DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
+ DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
+ DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
+ DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
+ DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
+ DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
+ DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
+ DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
+ DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
+ DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
+ DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
+ DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
+ DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
+ DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
+ DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
+ DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
+ DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
+ DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
+ DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
+ DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
+ DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
+ DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
+ DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
+ DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
+ DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
+ DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
+ DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
+ DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
+ DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
+ DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
+ DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
+ DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
+ DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
+ DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
+ DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
+ DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
+ DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+ DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+ DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+ DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+ { .node_name = NULL },
+};
+
+int __init dra7xx_clk_init(void)
+{
+ int rc;
+ struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+
+ of_clk_init(NULL);
+
+ omap_dt_clocks_register(dra7xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
+ sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
+ dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
+
+ rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
+ if (!rc)
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+ dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+
+ return rc;
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 18/45] CLK: DT: add support for set-rate-parent flag
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (16 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 17/45] CLK: TI: add dra7 clock init file Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 19/45] ARM: dts: am33xx clock data Tero Kristo
` (26 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
Adding set-rate-parent to clock node now allows a node to forward
clk_set_rate request to its parent clock.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/clk-divider.c | 6 +++++-
drivers/clk/clk-fixed-factor.c | 6 +++++-
drivers/clk/clk-gate.c | 8 ++++++--
drivers/clk/clk-mux.c | 6 +++++-
4 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 724f579..353fd5a 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -388,6 +388,7 @@ void of_divider_clk_setup(struct device_node *node)
u32 mask = 0;
u32 shift = 0;
struct clk_div_table *table;
+ u32 flags = 0;
of_property_read_string(node, "clock-output-names", &clk_name);
@@ -422,11 +423,14 @@ void of_divider_clk_setup(struct device_node *node)
if (of_property_read_bool(node, "hiword-mask"))
clk_divider_flags |= CLK_DIVIDER_HIWORD_MASK;
+ if (of_property_read_bool(node, "set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
table = of_clk_get_div_table(node);
if (IS_ERR(table))
return;
- clk = _register_divider(NULL, clk_name, parent_name, 0, reg, shift,
+ clk = _register_divider(NULL, clk_name, parent_name, flags, reg, shift,
mask, clk_divider_flags, table, NULL);
if (!IS_ERR(clk))
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 9ff7d51..30aa121 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -107,6 +107,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
const char *clk_name = node->name;
const char *parent_name;
u32 div, mult;
+ u32 flags = 0;
if (of_property_read_u32(node, "clock-div", &div)) {
pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
@@ -123,7 +124,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
of_property_read_string(node, "clock-output-names", &clk_name);
parent_name = of_clk_get_parent_name(node, 0);
- clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+ if (of_property_read_bool(node, "set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
mult, div);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 7ba3633..4a1360a 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -176,6 +176,7 @@ void of_gate_clk_setup(struct device_node *node)
const char *parent_name;
u8 clk_gate_flags = 0;
u32 bit_idx = 0;
+ u32 flags = 0;
of_property_read_string(node, "clock-output-names", &clk_name);
@@ -199,8 +200,11 @@ void of_gate_clk_setup(struct device_node *node)
if (of_property_read_bool(node, "hiword-mask"))
clk_gate_flags |= CLK_GATE_HIWORD_MASK;
- clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, bit_idx,
- clk_gate_flags, NULL);
+ if (of_property_read_bool(node, "set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ clk = clk_register_gate(NULL, clk_name, parent_name, flags, reg,
+ bit_idx, clk_gate_flags, NULL);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index cb68226..87a70d4 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -184,6 +184,7 @@ void of_mux_clk_setup(struct device_node *node)
u8 clk_mux_flags = 0;
u32 mask = 0;
u32 shift = 0;
+ u32 flags = 0;
of_property_read_string(node, "clock-output-names", &clk_name);
@@ -223,8 +224,11 @@ void of_mux_clk_setup(struct device_node *node)
if (of_property_read_bool(node, "hiword-mask"))
clk_mux_flags |= CLK_MUX_HIWORD_MASK;
+ if (of_property_read_bool(node, "set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
- 0, reg, shift, mask, clk_mux_flags, NULL, NULL);
+ flags, reg, shift, mask, clk_mux_flags, NULL, NULL);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 19/45] ARM: dts: am33xx clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (17 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 18/45] CLK: DT: add support for set-rate-parent flag Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 20/45] CLK: TI: add am33xx clock init file Tero Kristo
` (25 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am33xx-clocks.dtsi | 653 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/am33xx.dtsi | 7 +
2 files changed, 660 insertions(+)
create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..1bc1394
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,653 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@44e10040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+ bit-shift = <22>;
+ reg = <0x44e10040 0x4>;
+ bit-mask = <0x3>;
+};
+
+tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+dpll_core_ck: dpll_core_ck@44e00490 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck@44e00480 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e00480 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck@44e00484 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e00484 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck@44e004d8 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ reg = <0x44e004d8 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@44e00488 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x44e0042c 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@44e004a8 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ reg = <0x44e004a8 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@44e00494 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x44e00440 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@44e004a0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ reg = <0x44e004a0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+dpll_disp_ck: dpll_disp_ck@44e00498 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x44e00454 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck@44e004a4 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_disp_ck>;
+ reg = <0x44e004a4 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ set-rate-parent;
+};
+
+dpll_per_ck: dpll_per_ck@44e0048c {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-no-gate-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x44e0049c 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@44e004ac {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_ck>;
+ reg = <0x44e004ac 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cefuse_fck: cefuse_fck@44e00a20 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_clkin_ck>;
+ bit-shift = <1>;
+ reg = <0x44e00a20 0x4>;
+};
+
+clk_24mhz: clk_24mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_24mhz>;
+ clock-mult = <1>;
+ clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick@44e0014c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ck>;
+ reg = <0x44e0014c 0x4>;
+ bit-shift = <1>;
+};
+
+dcan0_fck: dcan0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3_gclk: l3_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk@44e00530 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+ reg = <0x44e00530 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcasp0_fck: mcasp0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmu_fck: mmu_fck@44e00914 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ bit-shift = <1>;
+ reg = <0x44e00914 0x4>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+timer1_fck: timer1_fck@44e00528 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ reg = <0x44e00528 0x4>;
+ bit-mask = <0x7>;
+};
+
+timer2_fck: timer2_fck@44e00508 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00508 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer3_fck: timer3_fck@44e0050c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0050c 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer4_fck: timer4_fck@44e00510 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00510 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer5_fck: timer5_fck@44e00518 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00518 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer6_fck: timer6_fck@44e0051c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0051c 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer7_fck: timer7_fck@44e00504 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00504 0x4>;
+ bit-mask = <0x3>;
+};
+
+usbotg_fck: usbotg_fck@44e0047c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_ck>;
+ bit-shift = <8>;
+ reg = <0x44e0047c 0x4>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+ieee5000_fck: ieee5000_fck@44e000e4 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ bit-shift = <1>;
+ reg = <0x44e000e4 0x4>;
+};
+
+wdt1_fck: wdt1_fck@44e00538 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e00538 0x4>;
+ bit-mask = <0x3>;
+};
+
+l4_rtc_gclk: l4_rtc_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4fw_gclk: l4fw_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sysclk_div_ck: sysclk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44e00520 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+ reg = <0x44e00520 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44e0053c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+ reg = <0x44e0053c 0x4>;
+ bit-mask = <0x3>;
+};
+
+gpio0_dbclk: gpio0_dbclk@44e00408 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpio0_dbclk_mux_ck>;
+ bit-shift = <18>;
+ reg = <0x44e00408 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@44e000ac {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <18>;
+ reg = <0x44e000ac 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@44e000b0 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <18>;
+ reg = <0x44e000b0 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@44e000b4 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <18>;
+ reg = <0x44e000b4 0x4>;
+};
+
+lcd_gclk: lcd_gclk@44e00534 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+ reg = <0x44e00534 0x4>;
+ bit-mask = <0x3>;
+ set-rate-parent;
+};
+
+mmc_clk: mmc_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44e0052c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+ bit-shift = <1>;
+ reg = <0x44e0052c 0x4>;
+ bit-mask = <0x1>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck@44e0052c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&gfx_fclk_clksel_ck>;
+ reg = <0x44e0052c 0x4>;
+ table = < 1 0 >, < 2 1 >;
+ bit-mask = <0x1>;
+};
+
+sysclkout_pre_ck: sysclkout_pre_ck@44e00700 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ reg = <0x44e00700 0x4>;
+ bit-mask = <0x7>;
+};
+
+clkout2_div_ck: clkout2_div_ck@44e00700 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sysclkout_pre_ck>;
+ bit-shift = <3>;
+ reg = <0x44e00700 0x4>;
+ table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >;
+ bit-mask = <0x7>;
+};
+
+dbg_sysclk_ck: dbg_sysclk_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_clkin_ck>;
+ bit-shift = <19>;
+ reg = <0x44e00414 0x4>;
+};
+
+dbg_clka_ck: dbg_clka_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ bit-shift = <30>;
+ reg = <0x44e00414 0x4>;
+};
+
+stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ bit-shift = <22>;
+ reg = <0x44e00414 0x4>;
+ bit-mask = <0x3>;
+};
+
+trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ bit-shift = <20>;
+ reg = <0x44e00414 0x4>;
+ bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&stm_pmd_clock_mux_ck>;
+ bit-shift = <27>;
+ reg = <0x44e00414 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck@44e00414 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&trace_pmd_clk_mux_ck>;
+ bit-shift = <24>;
+ reg = <0x44e00414 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+clkout2_ck: clkout2_ck@44e00700 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkout2_div_ck>;
+ bit-shift = <7>;
+ reg = <0x44e00700 0x4>;
+};
+
+ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <0>;
+ reg = <0x44e10664 0x4>;
+};
+
+ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <1>;
+ reg = <0x44e10664 0x4>;
+};
+
+ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_m2_ck>;
+ bit-shift = <2>;
+ reg = <0x44e10664 0x4>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 38b446b..4701e3c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -531,4 +531,11 @@
status = "disabled";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am33xx-clocks.dtsi"
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 20/45] CLK: TI: add am33xx clock init file
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (18 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 19/45] ARM: dts: am33xx clock data Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 21/45] ARM: AM33xx: remove old clock data and link in new clock init code Tero Kristo
` (24 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.
This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock.h | 1 -
drivers/clk/ti/clk-33xx.c | 162 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
3 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clk-33xx.c
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 106c5c2..2e6cbeb 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
new file mode 100644
index 0000000..cfc999d
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx.c
@@ -0,0 +1,162 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct omap_dt_clk am33xx_clks[] = {
+ DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+ DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
+ DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+ DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+ DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+ DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+ DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+ DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+ DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+ DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+ DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+ DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
+ DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+ DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+ DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+ DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
+ DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+ DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+ DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
+ DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+ DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+ DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+ DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+ DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+ DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
+ DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+ DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+ DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+ DT_CLK(NULL, "mmu_fck", "mmu_fck"),
+ DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+ DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+ DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+ DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+ DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+ DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+ DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+ DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+ DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+ DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+ DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+ DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
+ DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
+ DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+ DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+ DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+ DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+ DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
+ DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+ DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+ DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
+ DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+ DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+ DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+ DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+ DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+ DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
+ DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
+ DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
+ DT_CLK(NULL, "mmc_clk", "mmc_clk"),
+ DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
+ DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
+ DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
+ DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
+ DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+ DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
+ DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
+ DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
+ DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
+ DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
+ DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
+ DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
+ DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+ DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+ DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+ { .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+ "dpll_ddr_m2_ck",
+ "dpll_mpu_m2_ck",
+ "l3_gclk",
+ "l4hs_gclk",
+ "l4fw_gclk",
+ "l4ls_gclk",
+ /* Required for external peripherals like, Audio codecs */
+ "clkout2_ck",
+};
+
+int __init am33xx_clk_init(void)
+{
+ struct clk *clk1, *clk2;
+
+ of_clk_init(NULL);
+
+ omap_dt_clocks_register(am33xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+ * physically present, in such a case HWMOD enabling of
+ * clock would be failure with default parent. And timer
+ * probe thinks clock is already enabled, this leads to
+ * crash upon accessing timer 3 & 6 registers in probe.
+ * Fix by setting parent of both these timers to master
+ * oscillator clock.
+ */
+
+ clk1 = clk_get_sys(NULL, "sys_clkin_ck");
+ clk2 = clk_get_sys(NULL, "timer3_fck");
+ clk_set_parent(clk2, clk1);
+
+ clk2 = clk_get_sys(NULL, "timer6_fck");
+ clk_set_parent(clk2, clk1);
+ /*
+ * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+ * the design/spec, so as a result, for example, timer which supposed
+ * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+ * not expected by any use-case, so change WDT1 clock source to PRCM
+ * 32KHz clock.
+ */
+ clk1 = clk_get_sys(NULL, "wdt1_fck");
+ clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+ clk_set_parent(clk1, clk2);
+
+ return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 31ecf99..9039b24 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -208,6 +208,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
int omap2_dflt_clk_enable(struct clk_hw *hw);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 21/45] ARM: AM33xx: remove old clock data and link in new clock init code
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (19 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 20/45] CLK: TI: add am33xx clock init file Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 22/45] CLK: TI: add interface clock support for OMAP3 Tero Kristo
` (23 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/Makefile | 1 -
arch/arm/mach-omap2/cclock33xx_data.c | 1059 ---------------------------------
drivers/clk/ti/Makefile | 2 +-
3 files changed, 1 insertion(+), 1061 deletions(-)
delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f518360..020079e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -187,7 +187,6 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index ba6534d..0000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1059 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
- "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
- "virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
- AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
- AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
- AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
- 0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
- "sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
- .hw = {
- .clk = &dpll_core_ck,
- },
- .dpll_data = &dpll_core_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
- "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
- .recalc_rate = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
- .hw = {
- .clk = &dpll_core_x2_ck,
- },
- .flags = CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
- NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
- 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
- AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
- .recalc_rate = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
- .hw = {
- .clk = &dpll_mpu_ck,
- },
- .dpll_data = &dpll_mpu_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
- 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
- .recalc_rate = &omap3_dpll_recalc,
- .get_parent = &omap2_init_dpll_parent,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
- .hw = {
- .clk = &dpll_ddr_ck,
- },
- .dpll_data = &dpll_ddr_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
- 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
- 0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
- .mult_mask = AM33XX_DPLL_MULT_MASK,
- .div1_mask = AM33XX_DPLL_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
- .hw = {
- .clk = &dpll_disp_ck,
- },
- .dpll_data = &dpll_disp_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
- CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
- AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
- .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
- .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
- .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
- .enable_mask = AM33XX_DPLL_EN_MASK,
- .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
- .max_multiplier = 2047,
- .max_divider = 128,
- .min_divider = 1,
- .flags = DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
- .hw = {
- .clk = &dpll_per_ck,
- },
- .dpll_data = &dpll_per_dd,
- .ops = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
- AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
- NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
- &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
- &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
- &dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
- 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
- 8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
- "dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
- "dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- * - hwmod data is not present for these modules, either hwmod
- * control is not required or its not populated.
- * - Driver code is not yet migrated to use hwmod/runtime pm
- * - Modules outside kernel access (to disable them by default)
- *
- * - mmu (gfx domain)
- * - cefuse
- * - usbotg_fck (its additional clock and not really a modulemode)
- * - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
- AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
- AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
- 0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
- "clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
- .is_enabled = &omap2_dflt_clk_is_enabled,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
- .hw = {
- .clk = &clkdiv32k_ick,
- },
- .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
- .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
- .clkdm_name = "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
- AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
- 0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
- 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
- AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
- { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
- { .parent = &tclkin_ck, .rates = div_1_2_rates },
- { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
- { .parent = &clk_32768_ck, .rates = div_1_4_rates },
- { .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
- "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
- "clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
- .hw = {
- .clk = &timer1_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer1_clkmux_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
- { .parent = &tclkin_ck, .rates = div_1_0_rates },
- { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
- "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
- .hw = {
- .clk = &timer2_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
- .hw = {
- .clk = &timer3_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
- .hw = {
- .clk = &timer4_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
- .hw = {
- .clk = &timer5_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
- .hw = {
- .clk = &timer6_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
- .hw = {
- .clk = &timer7_fck,
- },
- .clkdm_name = "l4ls_clkdm",
- .clksel = timer2_to_7_clk_sel,
- .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
- "dpll_core_m5_ck",
- &dpll_core_m5_ck,
- 0x0,
- 1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
- { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
- "dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
- .hw = {
- .clk = &cpsw_cpts_rft_clk,
- },
- .clkdm_name = "cpsw_125mhz_clkdm",
- .clksel = cpsw_cpts_rft_clkmux_sel,
- .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
- .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
- "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- { .parent = &clk_32768_ck, .rates = div_1_1_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
- .recalc_rate = &omap2_clksel_recalc,
- .get_parent = &omap2_clksel_find_parent_index,
- .set_parent = &omap2_clksel_set_parent,
- .init = &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
- .hw = {
- .clk = &gpio0_dbclk_mux_ck,
- },
- .clkdm_name = "l4_wkup_clkdm",
- .clksel = gpio0_dbclk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
- AM33XX_CM_WKUP_GPIO0_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO1_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO2_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
- AM33XX_CM_PER_GPIO3_CLKCTRL,
- AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
- "l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
- { .parent = &l3_gclk, .rates = div_1_0_rates },
- { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
- .hw = {
- .clk = &pruss_ocp_gclk,
- },
- .clkdm_name = "pruss_ocp_clkdm",
- .clksel = pruss_ocp_clk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
- "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
- { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
- { .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
- .hw = {
- .clk = &lcd_gclk,
- },
- .clkdm_name = "lcdc_clkdm",
- .clksel = lcd_clk_mux_sel,
- .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
- gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
- "dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
- { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
- .hw = {
- .clk = &gfx_fclk_clksel_ck,
- },
- .clksel = gfx_clksel_sel,
- .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
- .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
- { .div = 1, .val = 0, },
- { .div = 2, .val = 1, },
- { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
- &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
- AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
- 0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
- "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
- "lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
- { .parent = &clk_32768_ck, .rates = div_1_0_rates },
- { .parent = &l3_gclk, .rates = div_1_1_rates },
- { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
- { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
- { .parent = &lcd_gclk, .rates = div_1_4_rates },
- { .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
- .hw = {
- .clk = &sysclkout_pre_ck,
- },
- .clksel = sysclkout_pre_sel,
- .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
- .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
- { .div = 1, .val = 0, },
- { .div = 2, .val = 1, },
- { .div = 3, .val = 2, },
- { .div = 4, .val = 3, },
- { .div = 5, .val = 4, },
- { .div = 6, .val = 5, },
- { .div = 7, .val = 6, },
- { .div = 8, .val = 7, },
- { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
- 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
- AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
- AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
- "clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
- { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
- .hw = {
- .clk = &wdt1_fck,
- },
- .clkdm_name = "l4_wkup_clkdm",
- .clksel = wdt_clkmux_sel,
- .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
- .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
- "dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
- .enable = &omap2_dflt_clk_enable,
- .disable = &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS0_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS1_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
- NULL, NULL, 0,
- AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
- AM33XX_PWMSS2_TBCLKEN_SHIFT,
- NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
- 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
- "dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
- AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_TRC_PMD_CLKSEL_SHIFT,
- AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
- &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
- AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
- &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
- AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
- CLK(NULL, "clk_32768_ck", &clk_32768_ck),
- CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
- CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
- CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
- CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
- CLK(NULL, "tclkin_ck", &tclkin_ck),
- CLK(NULL, "dpll_core_ck", &dpll_core_ck),
- CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
- CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
- CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
- CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
- CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
- CLK("cpu0", NULL, &dpll_mpu_ck),
- CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
- CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
- CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
- CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
- CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
- CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
- CLK(NULL, "dpll_per_ck", &dpll_per_ck),
- CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
- CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
- CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
- CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
- CLK(NULL, "cefuse_fck", &cefuse_fck),
- CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
- CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
- CLK(NULL, "dcan0_fck", &dcan0_fck),
- CLK("481cc000.d_can", NULL, &dcan0_fck),
- CLK(NULL, "dcan1_fck", &dcan1_fck),
- CLK("481d0000.d_can", NULL, &dcan1_fck),
- CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
- CLK(NULL, "mcasp0_fck", &mcasp0_fck),
- CLK(NULL, "mcasp1_fck", &mcasp1_fck),
- CLK(NULL, "mmu_fck", &mmu_fck),
- CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
- CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
- CLK(NULL, "sha0_fck", &sha0_fck),
- CLK(NULL, "aes0_fck", &aes0_fck),
- CLK(NULL, "timer1_fck", &timer1_fck),
- CLK(NULL, "timer2_fck", &timer2_fck),
- CLK(NULL, "timer3_fck", &timer3_fck),
- CLK(NULL, "timer4_fck", &timer4_fck),
- CLK(NULL, "timer5_fck", &timer5_fck),
- CLK(NULL, "timer6_fck", &timer6_fck),
- CLK(NULL, "timer7_fck", &timer7_fck),
- CLK(NULL, "usbotg_fck", &usbotg_fck),
- CLK(NULL, "ieee5000_fck", &ieee5000_fck),
- CLK(NULL, "wdt1_fck", &wdt1_fck),
- CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
- CLK(NULL, "l3_gclk", &l3_gclk),
- CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
- CLK(NULL, "l4hs_gclk", &l4hs_gclk),
- CLK(NULL, "l3s_gclk", &l3s_gclk),
- CLK(NULL, "l4fw_gclk", &l4fw_gclk),
- CLK(NULL, "l4ls_gclk", &l4ls_gclk),
- CLK(NULL, "clk_24mhz", &clk_24mhz),
- CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
- CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
- CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
- CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
- CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
- CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
- CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
- CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
- CLK(NULL, "lcd_gclk", &lcd_gclk),
- CLK(NULL, "mmc_clk", &mmc_clk),
- CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
- CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
- CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
- CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
- CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
- CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
- CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck),
- CLK(NULL, "dbg_clka_ck", &dbg_clka_ck),
- CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
- CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
- CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
- CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
- CLK(NULL, "clkout2_ck", &clkout2_ck),
- CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
- CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
- CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
- "dpll_ddr_m2_ck",
- "dpll_mpu_m2_ck",
- "l3_gclk",
- "l4hs_gclk",
- "l4fw_gclk",
- "l4ls_gclk",
- "clkout2_ck", /* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
- if (soc_is_am33xx())
- cpu_mask = RATE_IN_AM33XX;
-
- omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
- omap2_clk_disable_autoidle_all();
-
- omap2_clk_enable_init_clocks(enable_init_clks,
- ARRAY_SIZE(enable_init_clks));
-
- /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
- * physically present, in such a case HWMOD enabling of
- * clock would be failure with default parent. And timer
- * probe thinks clock is already enabled, this leads to
- * crash upon accessing timer 3 & 6 registers in probe.
- * Fix by setting parent of both these timers to master
- * oscillator clock.
- */
-
- clk_set_parent(&timer3_fck, &sys_clkin_ck);
- clk_set_parent(&timer6_fck, &sys_clkin_ck);
- /*
- * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
- * the design/spec, so as a result, for example, timer which supposed
- * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
- * not expected by any use-case, so change WDT1 clock source to PRCM
- * 32KHz clock.
- */
- clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
- return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index e612055..bdc632c 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o gate.o \
clockdomain.o apll.o clk-44xx.o \
- clk-54xx.o clk-7xx.o
+ clk-54xx.o clk-7xx.o clk-33xx.o
endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 22/45] CLK: TI: add interface clock support for OMAP3
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (20 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 21/45] ARM: AM33xx: remove old clock data and link in new clock init code Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 23/45] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm Tero Kristo
` (22 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
.../devicetree/bindings/clock/ti/interface.txt | 53 +++++++++
arch/arm/mach-omap2/clock.h | 6 -
drivers/clk/ti/Makefile | 3 +-
drivers/clk/ti/interface.c | 124 ++++++++++++++++++++
include/linux/clk/ti.h | 7 ++
5 files changed, 186 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
create mode 100644 drivers/clk/ti/interface.c
diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
new file mode 100644
index 0000000..297b3e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -0,0 +1,53 @@
+Binding for Texas Instruments interface clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features, including
+companion clock finding (match corresponding functional gate
+clock) and hardware autoidle enable / disable.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,omap3-interface-clock" - basic OMAP3 interface clock
+ "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
+ capability for waiting clock to be ready
+ "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
+ handling
+ "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
+ "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
+ "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for the control register
+
+Optional properties:
+- ti,enable-bit : bit shift for the bit enabling/disabling the clock
+ (default 0)
+
+Examples:
+ aes1_ick: aes1_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,enable-bit = <3>;
+ };
+
+ cam_ick: cam_ick@48004f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004f10 0x4>;
+ ti,enable-bit = <0>;
+ };
+
+ ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <0>;
+ };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2e6cbeb..d1b227e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -266,14 +266,8 @@ extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
-extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index bdc632c..d681ae7 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,6 @@
ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o gate.o \
clockdomain.o apll.o clk-44xx.o \
- clk-54xx.o clk-7xx.o clk-33xx.o
+ clk-54xx.o clk-7xx.o clk-33xx.o \
+ interface.o
endif
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
new file mode 100644
index 0000000..17e293f
--- /dev/null
+++ b/drivers/clk/ti/interface.c
@@ -0,0 +1,124 @@
+/*
+ * OMAP interface clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static const struct clk_ops omap_interface_clk_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+void __init _of_omap_interface_clk_setup(struct device_node *node,
+ const struct clk_hw_omap_ops *ops)
+{
+ struct clk *clk;
+ struct clk_init_data init = { 0 };
+ struct clk_hw_omap *clk_hw;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ u32 val;
+
+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+ if (!clk_hw) {
+ pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+ return;
+ }
+
+ clk_hw->hw.init = &init;
+ clk_hw->ops = ops;
+ clk_hw->enable_reg = of_iomap(node, 0);
+
+ if (!of_property_read_u32(node, "ti,enable-bit", &val))
+ clk_hw->enable_bit = val;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ init.name = clk_name;
+ init.ops = &omap_interface_clk_ops;
+ init.flags = 0;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ if (!parent_name) {
+ pr_err("%s: %s must have a parent\n", __func__, clk_name);
+ goto cleanup;
+ }
+
+ init.num_parents = 1;
+ init.parent_names = &parent_name;
+
+ clk = clk_register(NULL, &clk_hw->hw);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ omap2_init_clk_hw_omap_clocks(clk);
+ return;
+ }
+
+cleanup:
+ kfree(clk_hw);
+}
+
+static void __init of_omap_interface_clk_setup(struct device_node *node)
+{
+ _of_omap_interface_clk_setup(node, &clkhwops_iclk_wait);
+}
+CLK_OF_DECLARE(omap_interface_clk, "ti,omap3-interface-clock",
+ of_omap_interface_clk_setup);
+
+static void __init of_omap_no_wait_interface_clk_setup(struct device_node *node)
+{
+ _of_omap_interface_clk_setup(node, &clkhwops_iclk);
+}
+CLK_OF_DECLARE(omap_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
+ of_omap_no_wait_interface_clk_setup);
+
+static void __init
+of_omap_hsotgusb_interface_clk_setup(struct device_node *node)
+{
+ _of_omap_interface_clk_setup(node,
+ &clkhwops_omap3430es2_iclk_hsotgusb_wait);
+}
+CLK_OF_DECLARE(omap_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
+ of_omap_hsotgusb_interface_clk_setup);
+
+static void __init of_omap_dss_interface_clk_setup(struct device_node *node)
+{
+ _of_omap_interface_clk_setup(node,
+ &clkhwops_omap3430es2_iclk_dss_usbhost_wait);
+}
+CLK_OF_DECLARE(omap_dss_interface_clk, "ti,omap3-dss-interface-clock",
+ of_omap_dss_interface_clk_setup);
+
+static void __init of_omap_ssi_interface_clk_setup(struct device_node *node)
+{
+ _of_omap_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
+}
+CLK_OF_DECLARE(omap_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
+ of_omap_ssi_interface_clk_setup);
+
+static void __init of_omap_am35xx_interface_clk_setup(struct device_node *node)
+{
+ _of_omap_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
+}
+CLK_OF_DECLARE(omap_am35xx_interface_clk, "ti,am35xx-interface-clock",
+ of_omap_am35xx_interface_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9039b24..1e189af 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -231,5 +231,12 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
+
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 23/45] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (21 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 22/45] CLK: TI: add interface clock support for OMAP3 Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 24/45] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name Tero Kristo
` (21 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9dade6c..ec82989 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -656,6 +656,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
if (oh->clkdm) {
return oh->clkdm;
} else if (oh->_clk) {
+ if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+ return NULL;
clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
return clk->clkdm;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 24/45] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (22 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 23/45] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 25/45] ARM: dts: omap3 clock data Tero Kristo
` (20 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.
Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.
This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index ec82989..ef61582 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1544,7 +1544,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
if (!oh->clkdm) {
pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
oh->name, oh->clkdm_name);
- return -EINVAL;
+ return 0;
}
pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4115,6 +4115,7 @@ void __init omap_hwmod_init(void)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+ soc_ops.init_clkdm = _init_clkdm;
} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 25/45] ARM: dts: omap3 clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (23 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 24/45] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 26/45] CLK: TI: add omap3 clock init file Tero Kristo
` (19 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).
TODO: add still missing am35xx only clock nodes
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap3.dtsi | 7 +
arch/arm/boot/dts/omap3430es1-clocks.dtsi | 158 ++
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi | 222 +++
arch/arm/boot/dts/omap34xx.dtsi | 111 +-
.../omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 196 +++
arch/arm/boot/dts/omap36xx-clocks.dtsi | 80 ++
.../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 175 +++
arch/arm/boot/dts/omap36xx.dtsi | 112 +-
arch/arm/boot/dts/omap3xxx-clocks.dtsi | 1513 ++++++++++++++++++++
9 files changed, 2572 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7d95cda..939cc20 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -533,4 +533,11 @@
ram-bits = <12>;
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap3xxx-clocks.dtsi"
+ };
};
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 0000000..cfd737e
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,158 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+gfx_l3_ck: gfx_l3_ck@48004b10 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b10 0x4>;
+ ti,enable-bit = <0>;
+};
+
+gfx_l3_fck: gfx_l3_fck@48004b40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b40 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+gfx_l3_ick: gfx_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&gfx_l3_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gfx_cg1_ck: gfx_cg1_ck@48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gfx_l3_fck>;
+ reg = <0x48004b00 0x4>;
+ ti,enable-bit = <1>;
+};
+
+gfx_cg2_ck: gfx_cg2_ck@48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gfx_l3_fck>;
+ reg = <0x48004b00 0x4>;
+ ti,enable-bit = <2>;
+};
+
+d2d_26m_fck: d2d_26m_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <3>;
+};
+
+fshostusb_fck: fshostusb_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <5>;
+};
+
+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&corex2_fck>;
+ bit-shift = <8>;
+ reg = <0x48004a40 0x4>;
+ table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+ bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1@48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&ssi_ssr_div_fck_3430es1>;
+ bit-shift = <0>;
+ reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck_3430es1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hsotgusb_ick: hsotgusb_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <4>;
+};
+
+fac_ick: fac_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <8>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+ssi_ick_3430es1: ssi_ick_3430es1@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <0>;
+};
+
+usb_l4_div_ick: usb_l4_div_ick@48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l4_ick>;
+ bit-shift = <4>;
+ reg = <0x48004a40 0x4>;
+ bit-mask = <0x3>;
+ index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&usb_l4_div_ick>;
+ bit-shift = <5>;
+ reg = <0x48004a10 0x4>;
+};
+
+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1@48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ bit-shift = <0>;
+};
+
+dss_ick_3430es1: dss_ick_3430es1@48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004e10 0x4>;
+ ti,enable-bit = <0>;
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 0000000..7d97890
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,222 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+security_l4_ick2: security_l4_ick2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes1_ick: aes1_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,enable-bit = <3>;
+};
+
+rng_ick: rng_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,enable-bit = <2>;
+};
+
+sha11_ick: sha11_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,enable-bit = <1>;
+};
+
+des1_ick: des1_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x48004a14 0x4>;
+ ti,enable-bit = <0>;
+};
+
+cam_mclk: cam_mclk@48004f00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m5x2_ck>;
+ bit-shift = <0>;
+ reg = <0x48004f00 0x4>;
+ set-rate-parent;
+};
+
+cam_ick: cam_ick@48004f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004f10 0x4>;
+ ti,enable-bit = <0>;
+};
+
+csi2_96m_fck: csi2_96m_fck@48004f00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004f00 0x4>;
+ bit-shift = <1>;
+};
+
+security_l3_ick: security_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pka_ick: pka_ick@48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l3_ick>;
+ reg = <0x48004a14 0x4>;
+ ti,enable-bit = <4>;
+};
+
+icr_ick: icr_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <29>;
+};
+
+des2_ick: des2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <26>;
+};
+
+mspro_ick: mspro_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <23>;
+};
+
+mailboxes_ick: mailboxes_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <7>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sr1_fck: sr1_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004c00 0x4>;
+ ti,enable-bit = <6>;
+};
+
+sr2_fck: sr2_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004c00 0x4>;
+ ti,enable-bit = <7>;
+};
+
+sr_l4_ick: sr_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll2_fck: dpll2_fck@48004040 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&core_ck>;
+ bit-shift = <19>;
+ reg = <0x48004040 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+dpll2_ck: dpll2_ck@48004004 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ ti,modes = <0xa2>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>;
+};
+
+dpll2_m2_ck: dpll2_m2_ck@48004044 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll2_ck>;
+ reg = <0x48004044 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+iva2_ck: iva2_ck@48004000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll2_m2_ck>;
+ reg = <0x48004000 0x4>;
+ ti,enable-bit = <0>;
+};
+
+modem_fck: modem_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <31>;
+};
+
+sad2d_ick: sad2d_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <3>;
+};
+
+mad2d_ick: mad2d_ick@48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004a18 0x4>;
+ ti,enable-bit = <3>;
+};
+
+mspro_fck: mspro_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <23>;
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d61..acd5b76 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -25,4 +25,113 @@
clock-latency = <300000>; /* From legacy driver */
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap34xx-omap36xx-clocks.dtsi"
+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
+ <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
+ <&wdt2_fck>;
+ };
+
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cam_ick>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
+ <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
+ <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
+ <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
+ <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
+ <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
+ <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
+ <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
+ <&uart1_fck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
+ <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
+ <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
+ <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
+ <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..18457cf
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,196 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll5_ck: dpll5_ck@48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ ti,modes = <0x82>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll5_ck>;
+ reg = <0x48004d50 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+core_d3_ck: core_d3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+core_d4_ck: core_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+core_d6_ck: core_d6_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <6>;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+core_d2_ck: core_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+corex2_d3_fck: corex2_d3_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+};
+
+corex2_d5_fck: corex2_d5_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <5>;
+};
+
+sgx_mux_fck: sgx_mux_fck@48004b40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+ reg = <0x48004b40 0x4>;
+ table = <&core_d3_ck 0>, <&core_d4_ck 1>, <&core_d6_ck 2>, <&cm_96m_fck 3>, <&omap_192m_alwon_fck 4>, <&core_d2_ck 5>, <&corex2_d3_fck 6>, <&corex2_d5_fck 7>;
+ bit-mask = <0x7>;
+};
+
+sgx_fck: sgx_fck@48004b00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sgx_mux_fck>;
+ bit-shift = <1>;
+ reg = <0x48004b00 0x4>;
+};
+
+sgx_ick: sgx_ick@48004b10 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x48004b10 0x4>;
+ ti,enable-bit = <0>;
+};
+
+cpefuse_fck: cpefuse_fck@48004a08 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004a08 0x4>;
+ bit-shift = <0>;
+};
+
+ts_fck: ts_fck@48004a08 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&omap_32k_fck>;
+ reg = <0x48004a08 0x4>;
+ bit-shift = <1>;
+};
+
+usbtll_fck: usbtll_fck@48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x48004a08 0x4>;
+ ti,enable-bit = <2>;
+};
+
+usbtll_ick: usbtll_ick@48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a18 0x4>;
+ ti,enable-bit = <2>;
+};
+
+mmchs3_ick: mmchs3_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <30>;
+};
+
+mmchs3_fck: mmchs3_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <30>;
+};
+
+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ reg = <0x48004e00 0x4>;
+ ti,enable-bit = <0>;
+};
+
+dss_ick_3430es2: dss_ick_3430es2@48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48004e10 0x4>;
+ ti,enable-bit = <0>;
+};
+
+usbhost_120m_fck: usbhost_120m_fck@48005400 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x48005400 0x4>;
+ bit-shift = <1>;
+};
+
+usbhost_48m_fck: usbhost_48m_fck@48005400 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&omap_48m_fck>;
+ reg = <0x48005400 0x4>;
+ ti,enable-bit = <0>;
+};
+
+usbhost_ick: usbhost_ick@48005410 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x48005410 0x4>;
+ ti,enable-bit = <0>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 0000000..831643b
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll4_ck: dpll4_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-j-type-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ ti,modes = <0x82>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ reg = <0x48004d00 0x4>;
+ ti,enable-bit = <0x1b>;
+ ti,set-bit-to-disable;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ reg = <0x48004d00 0x4>;
+ ti,enable-bit = <0xc>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ reg = <0x48004d00 0x4>;
+ ti,enable-bit = <0x1c>;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ reg = <0x48004d00 0x4>;
+ ti,enable-bit = <0x1e>;
+ ti,set-rate-parent;
+ ti,set-bit-to-disable;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ reg = <0x48004d00 0x4>;
+ ti,enable-bit = <0x1f>;
+ ti,set-bit-to-disable;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+uart4_fck: uart4_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x48005000 0x4>;
+ ti,enable-bit = <18>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..ac39d76
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,175 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&corex2_fck>;
+ bit-shift = <8>;
+ reg = <0x48004a40 0x4>;
+ table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+ bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2@48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&ssi_ssr_div_fck_3430es2>;
+ bit-shift = <0>;
+ reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck_3430es2>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+hsotgusb_ick: hsotgusb_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-hsotgusb-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <4>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <0>;
+};
+
+dpll5_ck: dpll5_ck@48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ ti,modes = <0x82>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll5_ck>;
+ reg = <0x48004d50 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <20>;
+};
+
+sys_d2_ck: sys_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_96m_d2_fck: omap_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_96m_d4_fck: omap_96m_d4_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+omap_96m_d8_fck: omap_96m_d8_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+omap_96m_d10_fck: omap_96m_d10_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <10>;
+};
+
+dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+usim_mux_fck: usim_mux_fck@48004c40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
+ bit-shift = <3>;
+ reg = <0x48004c40 0x4>;
+ table = <&sys_ck 1>, <&dpll5_m2_d20_ck 10>, <&sys_d2_ck 2>, <&omap_96m_d2_fck 3>, <&omap_96m_d4_fck 4>, <&omap_96m_d8_fck 5>, <&omap_96m_d10_fck 6>, <&dpll5_m2_d4_ck 7>, <&dpll5_m2_d8_ck 8>, <&dpll5_m2_d16_ck 9>;
+ bit-mask = <0xf>;
+};
+
+usim_fck: usim_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&usim_mux_fck>;
+ bit-shift = <9>;
+ reg = <0x48004c00 0x4>;
+};
+
+usim_ick: usim_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,enable-bit = <9>;
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f8b3765..833d1f1 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -35,4 +35,114 @@
clock-frequency = <48000000>;
};
};
-};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "omap36xx-clocks.dtsi"
+ /include/ "omap34xx-omap36xx-clocks.dtsi"
+ /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
+ <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
+ <&wdt2_fck>;
+ };
+
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cam_ick>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
+ <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
+ <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
+ <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
+ <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
+ <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
+ <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
+ <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
+ <&uart1_fck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
+ <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
+ <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
+ <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
+ <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mad2d_ick>, <&sad2d_ick>, <&modem_fck>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 0000000..c83ea8a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1513 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dummy_apb_pclk: dummy_apb_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+omap_32k_fck: omap_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_12m_ck: virt_12m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+virt_13m_ck: virt_13m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+virt_38_4m_ck: virt_38_4m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+};
+
+virt_16_8m_ck: virt_16_8m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+};
+
+osc_sys_ck: osc_sys_ck@48306d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+ reg = <0x48306d40 0x4>;
+ bit-mask = <0x7>;
+};
+
+sys_ck: sys_ck@48307270 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&osc_sys_ck>;
+ bit-shift = <6>;
+ reg = <0x48307270 0x4>;
+ bit-mask = <0x3>;
+ index-starts-at-one;
+};
+
+dpll4_ck: dpll4_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ ti,modes = <0x82>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+};
+
+dpll4_m2_ck: dpll4_m2_ck@48004d48 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004d48 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+};
+
+dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ bit-shift = <0x1b>;
+ reg = <0x48004d00 0x4>;
+ set-bit-to-disable;
+};
+
+omap_96m_alwon_fck: omap_96m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll3_ck: dpll3_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-core-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>;
+};
+
+dpll3_m3_ck: dpll3_m3_ck@48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll3_ck>;
+ bit-shift = <16>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ bit-shift = <0xc>;
+ reg = <0x48004d00 0x4>;
+ set-bit-to-disable;
+};
+
+emu_core_alwon_ck: emu_core_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sys_altclk: sys_altclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+mcbsp_clks: mcbsp_clks {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+};
+
+sys_clkout1: sys_clkout1@48306d70 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&osc_sys_ck>;
+ reg = <0x48306d70 0x4>;
+ bit-shift = <7>;
+};
+
+dpll3_m2_ck: dpll3_m2_ck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll3_ck>;
+ bit-shift = <27>;
+ reg = <0x48004d40 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+core_ck: core_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll1_fck: dpll1_fck@48004940 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&core_ck>;
+ bit-shift = <19>;
+ reg = <0x48004940 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+dpll1_ck: dpll1_ck@48004904 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll1_fck>;
+ reg-names = "control", "idlest", "autoidle", "mult-div1";
+ reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>;
+};
+
+dpll1_x2_ck: dpll1_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll1_x2m2_ck: dpll1_x2m2_ck@48004944 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll1_x2_ck>;
+ reg = <0x48004944 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+};
+
+dpll3_x2_ck: dpll3_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll3_m2x2_ck: dpll3_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_x2_ck: dpll4_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+cm_96m_fck: cm_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+omap_96m_fck: omap_96m_fck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&cm_96m_fck>, <&sys_ck>;
+ bit-shift = <6>;
+ reg = <0x48004d40 0x4>;
+ bit-mask = <0x1>;
+};
+
+dpll4_m3_ck: dpll4_m3_ck@48004e40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
+ bit-shift = <8>;
+ reg = <0x48004e40 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+};
+
+dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ bit-shift = <0x1c>;
+ reg = <0x48004d00 0x4>;
+ set-bit-to-disable;
+};
+
+omap_54m_fck: omap_54m_fck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+ bit-shift = <5>;
+ reg = <0x48004d40 0x4>;
+ bit-mask = <0x1>;
+};
+
+cm_96m_d2_fck: cm_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cm_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+omap_48m_fck: omap_48m_fck@48004d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+ bit-shift = <3>;
+ reg = <0x48004d40 0x4>;
+ table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>;
+ bit-mask = <0x1>;
+};
+
+omap_12m_fck: omap_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll4_m4_ck: dpll4_m4_ck@48004e40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004e40 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+};
+
+dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m4x2_ck: dpll4_m4x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m4x2_mul_ck>;
+ bit-shift = <0x1d>;
+ reg = <0x48004d00 0x4>;
+ set-bit-to-disable;
+};
+
+dpll4_m5_ck: dpll4_m5_ck@48004f40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
+ reg = <0x48004f40 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+};
+
+dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m5_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ bit-shift = <0x1e>;
+ reg = <0x48004d00 0x4>;
+ set-bit-to-disable;
+};
+
+dpll4_m6_ck: dpll4_m6_ck@48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
+ bit-shift = <24>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x3f>;
+ index-starts-at-one;
+};
+
+dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ bit-shift = <0x1f>;
+ reg = <0x48004d00 0x4>;
+ set-bit-to-disable;
+};
+
+emu_per_alwon_ck: emu_per_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clkout2_src_mux_ck: clkout2_src_mux_ck@48004d70 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+ reg = <0x48004d70 0x4>;
+ bit-mask = <0x3>;
+};
+
+clkout2_src_ck: clkout2_src_ck@48004d70 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkout2_src_mux_ck>;
+ bit-shift = <7>;
+ reg = <0x48004d70 0x4>;
+};
+
+sys_clkout2: sys_clkout2@48004d70 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&clkout2_src_ck>;
+ bit-shift = <3>;
+ reg = <0x48004d70 0x4>;
+ bit-mask = <0x7>;
+ index-power-of-two;
+};
+
+corex2_fck: corex2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mpu_ck: mpu_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_x2m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+arm_fck: arm_fck@48004924 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mpu_ck>;
+ reg = <0x48004924 0x4>;
+ bit-mask = <0x1>;
+};
+
+emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3_ick: l3_ick@48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&core_ck>;
+ reg = <0x48004a40 0x4>;
+ bit-mask = <0x3>;
+ index-starts-at-one;
+};
+
+l4_ick: l4_ick@48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l3_ick>;
+ bit-shift = <2>;
+ reg = <0x48004a40 0x4>;
+ bit-mask = <0x3>;
+ index-starts-at-one;
+};
+
+rm_ick: rm_ick@48004c40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l4_ick>;
+ bit-shift = <1>;
+ reg = <0x48004c40 0x4>;
+ bit-mask = <0x3>;
+ index-starts-at-one;
+};
+
+gpt10_mux_fck: gpt10_mux_fck@48004a40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <6>;
+ reg = <0x48004a40 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt10_fck: gpt10_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt10_mux_fck>;
+ bit-shift = <11>;
+ reg = <0x48004a00 0x4>;
+};
+
+gpt11_mux_fck: gpt11_mux_fck@48004a40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <7>;
+ reg = <0x48004a40 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt11_fck: gpt11_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt11_mux_fck>;
+ bit-shift = <12>;
+ reg = <0x48004a00 0x4>;
+};
+
+core_96m_fck: core_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmchs2_fck: mmchs2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <25>;
+};
+
+mmchs1_fck: mmchs1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <24>;
+};
+
+i2c3_fck: i2c3_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <17>;
+};
+
+i2c2_fck: i2c2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <16>;
+};
+
+i2c1_fck: i2c1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <15>;
+};
+
+mcbsp5_mux_fck: mcbsp5_mux_fck@480022d8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ bit-shift = <4>;
+ reg = <0x480022d8 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcbsp5_fck: mcbsp5_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp5_mux_fck>;
+ bit-shift = <10>;
+ reg = <0x48004a00 0x4>;
+};
+
+mcbsp1_mux_fck: mcbsp1_mux_fck@48002274 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ bit-shift = <2>;
+ reg = <0x48002274 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcbsp1_fck: mcbsp1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp1_mux_fck>;
+ bit-shift = <9>;
+ reg = <0x48004a00 0x4>;
+};
+
+core_48m_fck: core_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcspi4_fck: mcspi4_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <21>;
+};
+
+mcspi3_fck: mcspi3_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <20>;
+};
+
+mcspi2_fck: mcspi2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <19>;
+};
+
+mcspi1_fck: mcspi1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <18>;
+};
+
+uart2_fck: uart2_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <14>;
+};
+
+uart1_fck: uart1_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <13>;
+};
+
+core_12m_fck: core_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_12m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+hdq_fck: hdq_fck@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_12m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <22>;
+};
+
+core_l3_ick: core_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sdrc_ick: sdrc_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <1>;
+};
+
+gpmc_fck: gpmc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+core_l4_ick: core_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mmchs2_ick: mmchs2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <25>;
+};
+
+mmchs1_ick: mmchs1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <24>;
+};
+
+hdq_ick: hdq_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <22>;
+};
+
+mcspi4_ick: mcspi4_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <21>;
+};
+
+mcspi3_ick: mcspi3_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <20>;
+};
+
+mcspi2_ick: mcspi2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <19>;
+};
+
+mcspi1_ick: mcspi1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <18>;
+};
+
+i2c3_ick: i2c3_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <17>;
+};
+
+i2c2_ick: i2c2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <16>;
+};
+
+i2c1_ick: i2c1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <15>;
+};
+
+uart2_ick: uart2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <14>;
+};
+
+uart1_ick: uart1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <13>;
+};
+
+gpt11_ick: gpt11_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <12>;
+};
+
+gpt10_ick: gpt10_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <11>;
+};
+
+mcbsp5_ick: mcbsp5_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <10>;
+};
+
+mcbsp1_ick: mcbsp1_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <9>;
+};
+
+omapctrl_ick: omapctrl_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <6>;
+};
+
+dss_tv_fck: dss_tv_fck@48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&omap_54m_fck>;
+ reg = <0x48004e00 0x4>;
+ bit-shift = <2>;
+};
+
+dss_96m_fck: dss_96m_fck@48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&omap_96m_fck>;
+ reg = <0x48004e00 0x4>;
+ bit-shift = <2>;
+};
+
+dss2_alwon_fck: dss2_alwon_fck@48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x48004e00 0x4>;
+ bit-shift = <1>;
+};
+
+gpt1_mux_fck: gpt1_mux_fck@48004c40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg = <0x48004c40 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt1_fck: gpt1_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt1_mux_fck>;
+ bit-shift = <0>;
+ reg = <0x48004c00 0x4>;
+};
+
+aes2_ick: aes2_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <28>;
+};
+
+wkup_32k_fck: wkup_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio1_dbck: gpio1_dbck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x48004c00 0x4>;
+ bit-shift = <3>;
+};
+
+sha12_ick: sha12_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <27>;
+};
+
+wdt2_fck: wdt2_fck@48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x48004c00 0x4>;
+ ti,enable-bit = <5>;
+};
+
+wkup_l4_ick: wkup_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+wdt2_ick: wdt2_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,enable-bit = <5>;
+};
+
+wdt1_ick: wdt1_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,enable-bit = <4>;
+};
+
+gpio1_ick: gpio1_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,enable-bit = <3>;
+};
+
+omap_32ksync_ick: omap_32ksync_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,enable-bit = <2>;
+};
+
+gpt12_ick: gpt12_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,enable-bit = <1>;
+};
+
+gpt1_ick: gpt1_ick@48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x48004c10 0x4>;
+ ti,enable-bit = <0>;
+};
+
+per_96m_fck: per_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+per_48m_fck: per_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+uart3_fck: uart3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x48005000 0x4>;
+ ti,enable-bit = <11>;
+};
+
+gpt2_mux_fck: gpt2_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt2_fck: gpt2_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt2_mux_fck>;
+ bit-shift = <3>;
+ reg = <0x48005000 0x4>;
+};
+
+gpt3_mux_fck: gpt3_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <1>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt3_fck: gpt3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt3_mux_fck>;
+ bit-shift = <4>;
+ reg = <0x48005000 0x4>;
+};
+
+gpt4_mux_fck: gpt4_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <2>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt4_fck: gpt4_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt4_mux_fck>;
+ bit-shift = <5>;
+ reg = <0x48005000 0x4>;
+};
+
+gpt5_mux_fck: gpt5_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <3>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt5_fck: gpt5_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt5_mux_fck>;
+ bit-shift = <6>;
+ reg = <0x48005000 0x4>;
+};
+
+gpt6_mux_fck: gpt6_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <4>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt6_fck: gpt6_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt6_mux_fck>;
+ bit-shift = <7>;
+ reg = <0x48005000 0x4>;
+};
+
+gpt7_mux_fck: gpt7_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <5>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt7_fck: gpt7_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt7_mux_fck>;
+ bit-shift = <8>;
+ reg = <0x48005000 0x4>;
+};
+
+gpt8_mux_fck: gpt8_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <6>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt8_fck: gpt8_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt8_mux_fck>;
+ bit-shift = <9>;
+ reg = <0x48005000 0x4>;
+};
+
+gpt9_mux_fck: gpt9_mux_fck@48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ bit-shift = <7>;
+ reg = <0x48005040 0x4>;
+ bit-mask = <0x1>;
+};
+
+gpt9_fck: gpt9_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt9_mux_fck>;
+ bit-shift = <10>;
+ reg = <0x48005000 0x4>;
+};
+
+per_32k_alwon_fck: per_32k_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio6_dbck: gpio6_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ bit-shift = <17>;
+};
+
+gpio5_dbck: gpio5_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ bit-shift = <16>;
+};
+
+gpio4_dbck: gpio4_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ bit-shift = <15>;
+};
+
+gpio3_dbck: gpio3_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ bit-shift = <14>;
+};
+
+gpio2_dbck: gpio2_dbck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ bit-shift = <13>;
+};
+
+wdt3_fck: wdt3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x48005000 0x4>;
+ ti,enable-bit = <12>;
+};
+
+per_l4_ick: per_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+gpio6_ick: gpio6_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <17>;
+};
+
+gpio5_ick: gpio5_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <16>;
+};
+
+gpio4_ick: gpio4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <15>;
+};
+
+gpio3_ick: gpio3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <14>;
+};
+
+gpio2_ick: gpio2_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <13>;
+};
+
+wdt3_ick: wdt3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <12>;
+};
+
+uart3_ick: uart3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <11>;
+};
+
+uart4_ick: uart4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <18>;
+};
+
+gpt9_ick: gpt9_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <10>;
+};
+
+gpt8_ick: gpt8_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <9>;
+};
+
+gpt7_ick: gpt7_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <8>;
+};
+
+gpt6_ick: gpt6_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <7>;
+};
+
+gpt5_ick: gpt5_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <6>;
+};
+
+gpt4_ick: gpt4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <5>;
+};
+
+gpt3_ick: gpt3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <4>;
+};
+
+gpt2_ick: gpt2_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <3>;
+};
+
+mcbsp2_ick: mcbsp2_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <0>;
+};
+
+mcbsp3_ick: mcbsp3_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <1>;
+};
+
+mcbsp4_ick: mcbsp4_ick@48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x48005010 0x4>;
+ ti,enable-bit = <2>;
+};
+
+mcbsp2_mux_fck: mcbsp2_mux_fck@48002274 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ bit-shift = <6>;
+ reg = <0x48002274 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcbsp2_fck: mcbsp2_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp2_mux_fck>;
+ bit-shift = <0>;
+ reg = <0x48005000 0x4>;
+};
+
+mcbsp3_mux_fck: mcbsp3_mux_fck@480022d8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ reg = <0x480022d8 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcbsp3_fck: mcbsp3_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp3_mux_fck>;
+ bit-shift = <1>;
+ reg = <0x48005000 0x4>;
+};
+
+mcbsp4_mux_fck: mcbsp4_mux_fck@480022d8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ bit-shift = <2>;
+ reg = <0x480022d8 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcbsp4_fck: mcbsp4_fck@48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp4_mux_fck>;
+ bit-shift = <2>;
+ reg = <0x48005000 0x4>;
+};
+
+emu_src_mux_ck: emu_src_mux_ck@48005140 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x3>;
+};
+
+emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+};
+
+pclk_fck: pclk_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&emu_src_ck>;
+ bit-shift = <8>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+pclkx2_fck: pclkx2_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&emu_src_ck>;
+ bit-shift = <6>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x3>;
+ index-starts-at-one;
+};
+
+atclk_fck: atclk_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&emu_src_ck>;
+ bit-shift = <4>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x3>;
+ index-starts-at-one;
+};
+
+traceclk_src_fck: traceclk_src_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ bit-shift = <2>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x3>;
+};
+
+traceclk_fck: traceclk_fck@48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&traceclk_src_fck>;
+ bit-shift = <11>;
+ reg = <0x48005140 0x4>;
+ bit-mask = <0x7>;
+ index-starts-at-one;
+};
+
+secure_32k_fck: secure_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+gpt12_fck: gpt12_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+wdt1_fck: wdt1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 26/45] CLK: TI: add omap3 clock init file
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (24 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 25/45] ARM: dts: omap3 clock data Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 27/45] ARM: dts: AM35xx clock data Tero Kristo
` (18 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock3xxx.h | 1 -
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/clk-3xxx.c | 388 +++++++++++++++++++++++++++++++++++++++
include/linux/clk/ti.h | 1 +
4 files changed, 390 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/ti/clk-3xxx.c
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index dab90e2..78d9f56 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -11,7 +11,6 @@
int omap3xxx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
extern struct clk *sdrc_ick_p;
extern struct clk *arm_fck_p;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index d681ae7..2dec2d9 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,5 +2,5 @@ ifneq ($(CONFIG_OF),)
obj-y += clk.o dpll.o autoidle.o gate.o \
clockdomain.o apll.o clk-44xx.o \
clk-54xx.o clk-7xx.o clk-33xx.o \
- interface.o
+ interface.o clk-3xxx.o
endif
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
new file mode 100644
index 0000000..7283dc8
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -0,0 +1,388 @@
+/*
+ * OMAP3 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+
+static struct omap_dt_clk omap3xxx_clks[] = {
+ DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
+ DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
+ DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
+ DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
+ DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
+ DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
+ DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
+ DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
+ DT_CLK("twl", "fck", "osc_sys_ck"),
+ DT_CLK(NULL, "sys_ck", "sys_ck"),
+ DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
+ DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
+ DT_CLK(NULL, "sys_altclk", "sys_altclk"),
+ DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
+ DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
+ DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
+ DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
+ DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
+ DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
+ DT_CLK(NULL, "core_ck", "core_ck"),
+ DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
+ DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
+ DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
+ DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
+ DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
+ DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
+ DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
+ DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
+ DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
+ DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
+ DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
+ DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
+ DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
+ DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
+ DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
+ DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
+ DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
+ DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
+ DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
+ DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
+ DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
+ DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
+ DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
+ DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
+ DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
+ DT_CLK(NULL, "corex2_fck", "corex2_fck"),
+ DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
+ DT_CLK(NULL, "mpu_ck", "mpu_ck"),
+ DT_CLK(NULL, "arm_fck", "arm_fck"),
+ DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
+ DT_CLK(NULL, "l3_ick", "l3_ick"),
+ DT_CLK(NULL, "l4_ick", "l4_ick"),
+ DT_CLK(NULL, "rm_ick", "rm_ick"),
+ DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
+ DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
+ DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
+ DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
+ DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
+ DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
+ DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
+ DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
+ DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
+ DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
+ DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
+ DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
+ DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
+ DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
+ DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
+ DT_CLK(NULL, "uart2_fck", "uart2_fck"),
+ DT_CLK(NULL, "uart1_fck", "uart1_fck"),
+ DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
+ DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
+ DT_CLK(NULL, "hdq_fck", "hdq_fck"),
+ DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
+ DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
+ DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
+ DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
+ DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
+ DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
+ DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
+ DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
+ DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
+ DT_CLK(NULL, "hdq_ick", "hdq_ick"),
+ DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
+ DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
+ DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
+ DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
+ DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
+ DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
+ DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
+ DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
+ DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
+ DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
+ DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
+ DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
+ DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
+ DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
+ DT_CLK(NULL, "uart2_ick", "uart2_ick"),
+ DT_CLK(NULL, "uart1_ick", "uart1_ick"),
+ DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
+ DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
+ DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
+ DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
+ DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
+ DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
+ DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
+ DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
+ DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
+ DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
+ DT_CLK(NULL, "aes2_ick", "aes2_ick"),
+ DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
+ DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
+ DT_CLK(NULL, "sha12_ick", "sha12_ick"),
+ DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
+ DT_CLK("omap_wdt", "ick", "wdt2_ick"),
+ DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
+ DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
+ DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
+ DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
+ DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
+ DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
+ DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
+ DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
+ DT_CLK(NULL, "uart3_fck", "uart3_fck"),
+ DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
+ DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
+ DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
+ DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
+ DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
+ DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
+ DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
+ DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
+ DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
+ DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
+ DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
+ DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
+ DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
+ DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
+ DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
+ DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
+ DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
+ DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
+ DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
+ DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
+ DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
+ DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
+ DT_CLK(NULL, "uart3_ick", "uart3_ick"),
+ DT_CLK(NULL, "uart4_ick", "uart4_ick"),
+ DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
+ DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
+ DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
+ DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
+ DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
+ DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
+ DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
+ DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
+ DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
+ DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
+ DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
+ DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
+ DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
+ DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
+ DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
+ DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
+ DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
+ DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
+ DT_CLK(NULL, "pclk_fck", "pclk_fck"),
+ DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
+ DT_CLK(NULL, "atclk_fck", "atclk_fck"),
+ DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
+ DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
+ DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
+ DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
+ DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+ DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
+ DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
+ DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
+ { .node_name = NULL },
+};
+
+static struct omap_dt_clk omap34xx_omap36xx_clks[] = {
+ DT_CLK(NULL, "aes1_ick", "aes1_ick"),
+ DT_CLK("omap_rng", "ick", "rng_ick"),
+ DT_CLK(NULL, "sha11_ick", "sha11_ick"),
+ DT_CLK(NULL, "des1_ick", "des1_ick"),
+ DT_CLK(NULL, "cam_mclk", "cam_mclk"),
+ DT_CLK(NULL, "cam_ick", "cam_ick"),
+ DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
+ DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
+ DT_CLK(NULL, "pka_ick", "pka_ick"),
+ DT_CLK(NULL, "icr_ick", "icr_ick"),
+ DT_CLK("omap-aes", "ick", "aes2_ick"),
+ DT_CLK("omap-sham", "ick", "sha12_ick"),
+ DT_CLK(NULL, "des2_ick", "des2_ick"),
+ DT_CLK(NULL, "mspro_ick", "mspro_ick"),
+ DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
+ DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
+ DT_CLK(NULL, "sr1_fck", "sr1_fck"),
+ DT_CLK(NULL, "sr2_fck", "sr2_fck"),
+ DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
+ DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
+ DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
+ DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
+ DT_CLK(NULL, "iva2_ck", "iva2_ck"),
+ DT_CLK(NULL, "modem_fck", "modem_fck"),
+ DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
+ DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
+ DT_CLK(NULL, "mspro_fck", "mspro_fck"),
+ DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
+ DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
+ { .node_name = NULL },
+};
+
+static struct omap_dt_clk omap36xx_omap3430es2plus_clks[] = {
+ DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
+ DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
+ DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
+ DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
+ DT_CLK(NULL, "usim_fck", "usim_fck"),
+ DT_CLK(NULL, "usim_ick", "usim_ick"),
+ { .node_name = NULL },
+};
+
+static struct omap_dt_clk omap3430es1_clks[] = {
+ DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
+ DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
+ DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
+ DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
+ DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
+ DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
+ DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
+ DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
+ DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
+ DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
+ DT_CLK(NULL, "fac_ick", "fac_ick"),
+ DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
+ DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
+ DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
+ DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
+ DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
+ { .node_name = NULL },
+};
+
+static struct omap_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
+ DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
+ DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
+ DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
+ DT_CLK(NULL, "sgx_fck", "sgx_fck"),
+ DT_CLK(NULL, "sgx_ick", "sgx_ick"),
+ DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
+ DT_CLK(NULL, "ts_fck", "ts_fck"),
+ DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
+ DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
+ DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
+ DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
+ DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
+ DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
+ DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
+ DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
+ DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
+ DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
+ DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
+ { .node_name = NULL },
+};
+
+static struct omap_dt_clk am35xx_clks[] = {
+ DT_CLK(NULL, "ipss_ick", "ipss_ick"),
+ DT_CLK(NULL, "rmii_ck", "rmii_ck"),
+ DT_CLK(NULL, "pclk_ck", "pclk_ck"),
+ DT_CLK(NULL, "emac_ick", "emac_ick"),
+ DT_CLK(NULL, "emac_fck", "emac_fck"),
+ DT_CLK("davinci_emac.0", NULL, "emac_ick"),
+ DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
+ DT_CLK("vpfe-capture", "master", "vpfe_ick"),
+ DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
+ DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
+ DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
+ DT_CLK(NULL, "hecc_ck", "hecc_ck"),
+ DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
+ DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
+ { .node_name = NULL },
+};
+
+static const char *enable_init_clks[] = {
+ "sdrc_ick",
+ "gpmc_fck",
+ "omapctrl_ick",
+};
+
+enum {
+ OMAP3_SOC_AM35XX,
+ OMAP3_SOC_OMAP3430_ES1,
+ OMAP3_SOC_OMAP3430_ES2_PLUS,
+ OMAP3_SOC_OMAP3630,
+ OMAP3_SOC_TI81XX,
+};
+
+static int __init omap3xxx_clk_init(int soc_type)
+{
+ of_clk_init(NULL);
+
+ if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+ omap_dt_clocks_register(omap3xxx_clks);
+
+ if (soc_type == OMAP3_SOC_AM35XX)
+ omap_dt_clocks_register(am35xx_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+ omap_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES1)
+ omap_dt_clocks_register(omap3430es1_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+ soc_type == OMAP3_SOC_OMAP3630)
+ omap_dt_clocks_register(omap36xx_omap3430es2plus_clks);
+
+ if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+ soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+ soc_type == OMAP3_SOC_OMAP3630)
+ omap_dt_clocks_register(omap34xx_omap36xx_clks);
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
+ (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
+ (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+
+ if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
+ omap3_clk_lock_dpll5();
+
+ return 0;
+}
+
+int __init omap3430_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
+}
+
+int __init omap3630_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_OMAP3630);
+}
+
+int __init am35xx_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_AM35XX);
+}
+
+int __init ti81xx_clk_init(void)
+{
+ return omap3xxx_clk_init(OMAP3_SOC_TI81XX);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 1e189af..90cb61b 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -214,6 +214,7 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+void omap3_clk_lock_dpll5(void);
void omap_dt_clocks_register(struct omap_dt_clk *oclks);
#ifdef CONFIG_OF
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 27/45] ARM: dts: AM35xx clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (25 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 26/45] CLK: TI: add omap3 clock init file Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 28/45] ARM: dts: AM35xx: use DT " Tero Kristo
` (17 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each AM35xx specific clock in the
AM35xx power, reset and clock manager (PRCM). Most of the AM35xx clock
data is shared with OMAP3xxx, this patch only creates the delta.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am35xx-clocks.dtsi | 101 ++++++++++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 0000000..7749413
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,101 @@
+/*
+ * Device Tree Source for AM35xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ipss_ick: ipss_ick@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <4>;
+};
+
+rmii_ck: rmii_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+};
+
+pclk_ck: pclk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+};
+
+emac_ick: emac_ick@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,enable-bit = <1>;
+};
+
+emac_fck: emac_fck@4800259c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&rmii_ck>;
+ reg = <0x4800259c 0x4>;
+ bit-shift = <9>;
+};
+
+vpfe_ick: vpfe_ick@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,enable-bit = <2>;
+};
+
+vpfe_fck: vpfe_fck@4800259c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&pclk_ck>;
+ reg = <0x4800259c 0x4>;
+ bit-shift = <10>;
+};
+
+hsotgusb_ick: hsotgusb_ick@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&ipss_ick>;
+ reg = <0x4800259c 0x4>;
+ ti,enable-bit = <0>;
+};
+
+hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x4800259c 0x4>;
+ bit-shift = <8>;
+};
+
+hecc_ck: hecc_ck@4800259c {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x4800259c 0x4>;
+ ti,enable-bit = <3>;
+};
+
+uart4_ick_am35xx: uart4_ick_am35xx@48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x48004a10 0x4>;
+ ti,enable-bit = <23>;
+};
+
+uart4_fck_am35xx: uart4_fck_am35xx@48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x48004a00 0x4>;
+ ti,enable-bit = <23>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 28/45] ARM: dts: AM35xx: use DT clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (26 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 27/45] ARM: dts: AM35xx clock data Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 29/45] ARM: OMAP3: use DT clock init if DT data is available Tero Kristo
` (16 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am3517-evm.dts | 2 +-
arch/arm/boot/dts/am3517.dtsi | 116 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/am3517_mt_ventoux.dts | 2 +-
3 files changed, 118 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/am3517.dtsi
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e99dfaf..9ff51d7 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
/ {
model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
new file mode 100644
index 0000000..47aa7c2
--- /dev/null
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -0,0 +1,116 @@
+/*
+ * Device Tree Source for AM3517 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "omap3.dtsi"
+
+/ {
+ cpus {
+ cpu@0 {
+ /* OMAP343x/OMAP35xx variants OPP1-5 */
+ operating-points = <
+ /* kHz uV */
+ 125000 975000
+ 250000 1075000
+ 500000 1200000
+ 550000 1270000
+ 600000 1350000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "am35xx-clocks.dtsi"
+ /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+ };
+
+ clockdomains {
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+ };
+
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
+ <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
+ <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
+ <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
+ <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
+ <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
+ <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
+ <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
+ <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
+ <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
+ <&uart1_fck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
+ <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
+ <&wdt2_fck>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
+ <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
+ <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
+ <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
+ <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
+ <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
+ <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index fdf5ce6..d00e934 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
/ {
model = "TeeJet Mt.Ventoux";
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 29/45] ARM: OMAP3: use DT clock init if DT data is available
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (27 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 28/45] ARM: dts: AM35xx: use DT " Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 30/45] ARM: dts: am43xx clock data Tero Kristo
` (15 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clock3xxx.h | 4 ++++
arch/arm/mach-omap2/io.c | 13 ++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 78d9f56..a5e2308 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,6 +9,10 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
int omap3xxx_clk_init(void);
+int omap3430_clk_init(void);
+int omap3630_clk_init(void);
+int ti81xx_clk_init(void);
+int am35xx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 205bb1d..fd4bb71 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -488,21 +488,29 @@ void __init omap3_init_early(void)
void __init omap3430_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3430_clk_init;
}
void __init omap35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3430_clk_init;
}
void __init omap3630_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = omap3630_clk_init;
}
void __init am35xx_init_early(void)
{
omap3_init_early();
+ if (of_have_populated_dt())
+ omap_clk_init = am35xx_clk_init;
}
void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
- omap_clk_init = omap3xxx_clk_init;
+ if (of_have_populated_dt())
+ omap_clk_init = ti81xx_clk_init;
+ else
+ omap_clk_init = omap3xxx_clk_init;
}
void __init omap3_init_late(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 30/45] ARM: dts: am43xx clock data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (28 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 29/45] ARM: OMAP3: use DT clock init if DT data is available Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 31/45] ARM: OMAP2+: Add support to parse 'main_clk' info from DT Tero Kristo
` (14 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 681 ++++++++++++++++++++++++++++++++++
1 file changed, 681 insertions(+)
create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 0000000..d580e38
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,681 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@44e10040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+ bit-shift = <22>;
+ reg = <0x44e10040 0x4>;
+ bit-mask = <0x3>;
+};
+
+tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+};
+
+dpll_core_ck: dpll_core_ck@44df2d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-lock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2d20 0x4>, <0x44df2d24 0x4>, <0x44df2d2c 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck@44df2d38 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d38 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck@44df2d3c {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d3c 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck@44df2d40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d40 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@44df2d60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2d60 0x4>, <0x44df2d64 0x4>, <0x44df2d6c 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@44df2d70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2d70 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@44df2da0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2da0 0x4>, <0x44df2da4 0x4>, <0x44df2dac 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@44df2db0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2db0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_disp_ck: dpll_disp_ck@44df2e20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2e20 0x4>, <0x44df2e24 0x4>, <0x44df2e2c 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck@44df2e30 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_disp_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2e30 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_ck: dpll_per_ck@44df2de0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2de0 0x4>, <0x44df2de4 0x4>, <0x44df2dec 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@44df2df0 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2df0 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clk_24mhz: clk_24mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_24mhz>;
+ clock-mult = <1>;
+ clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick@44df2a38 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ck>;
+ bit-shift = <8>;
+ reg = <0x44df2a38 0x4>;
+};
+
+dcan0_fck: dcan0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sysclk_div: sysclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk@44df4248 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+ reg = <0x44df4248 0x4>;
+ bit-mask = <0x1>;
+};
+
+mcasp0_fck: mcasp0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+clk_32k_tpm_ck: clk_32k_tpm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+timer1_fck: timer1_fck@44df4200 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4200 0x4>;
+ bit-mask = <0x7>;
+};
+
+timer2_fck: timer2_fck@44df4204 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4204 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer3_fck: timer3_fck@44df4208 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4208 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer4_fck: timer4_fck@44df420c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df420c 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer5_fck: timer5_fck@44df4210 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4210 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer6_fck: timer6_fck@44df4214 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4214 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer7_fck: timer7_fck@44df4218 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4218 0x4>;
+ bit-mask = <0x3>;
+};
+
+wdt1_fck: wdt1_fck@44df422c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df422c 0x4>;
+ bit-mask = <0x1>;
+};
+
+l3_gclk: l3_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sysclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44df4238 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+ reg = <0x44df4238 0x4>;
+ bit-mask = <0x3>;
+};
+
+clk_32k_mosc_ck: clk_32k_mosc_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44df4240 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4240 0x4>;
+ bit-mask = <0x7>;
+};
+
+gpio0_dbclk: gpio0_dbclk@44df2b68 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpio0_dbclk_mux_ck>;
+ bit-shift = <8>;
+ reg = <0x44df2b68 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@44df8c78 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <8>;
+ reg = <0x44df8c78 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@44df8c80 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <8>;
+ reg = <0x44df8c80 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@44df8c88 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <8>;
+ reg = <0x44df8c88 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@44df8c90 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <8>;
+ reg = <0x44df8c90 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@44df8c98 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ bit-shift = <8>;
+ reg = <0x44df8c98 0x4>;
+};
+
+mmc_clk: mmc_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44df423c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+ bit-shift = <1>;
+ reg = <0x44df423c 0x4>;
+ bit-mask = <0x1>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck@44df423c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&gfx_fclk_clksel_ck>;
+ reg = <0x44df423c 0x4>;
+ bit-mask = <0x1>;
+};
+
+disp_clk: disp_clk@44df4244 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+ reg = <0x44df4244 0x4>;
+ bit-mask = <0x3>;
+};
+
+dpll_extdev_ck: dpll_extdev_ck@44df2e60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x44df2e60 0x4>, <0x44df2e64 0x4>, <0x44df2e6c 0x4>;
+ reg-names = "control", "idlest", "mult-div1";
+};
+
+dpll_extdev_m2_ck: dpll_extdev_m2_ck@44df2e70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_extdev_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2e70 0x4>;
+ bit-mask = <0x7f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+mux_synctimer32k_ck: mux_synctimer32k_ck@44df4230 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+ reg = <0x44df4230 0x4>;
+ bit-mask = <0x3>;
+};
+
+synctimer_32kclk: synctimer_32kclk@44df2a30 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mux_synctimer32k_ck>;
+ bit-shift = <8>;
+ reg = <0x44df2a30 0x4>;
+};
+
+timer8_fck: timer8_fck@44df421c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df421c 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer9_fck: timer9_fck@44df4220 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4220 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer10_fck: timer10_fck@44df4224 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4224 0x4>;
+ bit-mask = <0x3>;
+};
+
+timer11_fck: timer11_fck@44df4228 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4228 0x4>;
+ bit-mask = <0x3>;
+};
+
+cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cpsw_50m_clkdiv>;
+ clock-mult = <1>;
+ clock-div = <10>;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_m4_ck: dpll_ddr_m4_ck@44df2db8 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x44df2db8 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+};
+
+dll_aging_clk_div: dll_aging_clk_div@44df4250 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&sys_clkin_ck>;
+ reg = <0x44df4250 0x4>;
+ table = < 8 0 >, < 16 1 >, < 32 2 >;
+ bit-mask = <0x3>;
+};
+
+div_core_25m_ck: div_core_25m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sysclk_div>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+func_12m_clk: func_12m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+};
+
+vtp_clk_div: vtp_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+};
+
+usbphy_32khz_clkmux: usbphy_32khz_clkmux@44df4260 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ reg = <0x44df4260 0x4>;
+ bit-mask = <0x1>;
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 31/45] ARM: OMAP2+: Add support to parse 'main_clk' info from DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (29 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 30/45] ARM: dts: am43xx clock data Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 32/45] ARM: OMAP2+: Add support to parse optional clk " Tero Kristo
` (13 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
From: Rajendra Nayak <rnayak@ti.com>
With clocks for OMAP moving to DT, its now possible to pass the 'main_clk'
data for each device from DT instead of having it in hwmod.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 34 +++++++++++++++++++++-------------
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index ef61582..838af96 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -730,14 +730,18 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
* functional clock pointer) if a main_clk is present. Returns 0 on
* success or -EINVAL on error.
*/
-static int _init_main_clk(struct omap_hwmod *oh)
+static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
{
int ret = 0;
- if (!oh->main_clk)
+ if (!oh->main_clk && !of_get_property(np, "clocks", NULL))
return 0;
- oh->_clk = clk_get(NULL, oh->main_clk);
+ if (oh->main_clk)
+ oh->_clk = clk_get(NULL, oh->main_clk);
+ else
+ oh->_clk = of_clk_get_by_name(np, "fck");
+
if (IS_ERR(oh->_clk)) {
pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
oh->name, oh->main_clk);
@@ -1563,7 +1567,8 @@ static int _init_clkdm(struct omap_hwmod *oh)
* Resolves all clock names embedded in the hwmod. Returns 0 on
* success, or a negative error code on failure.
*/
-static int _init_clocks(struct omap_hwmod *oh, void *data)
+static int _init_clocks(struct omap_hwmod *oh, void *data,
+ struct device_node *np)
{
int ret = 0;
@@ -1575,7 +1580,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
if (soc_ops.init_clkdm)
ret |= soc_ops.init_clkdm(oh);
- ret |= _init_main_clk(oh);
+ ret |= _init_main_clk(oh, np);
ret |= _init_interface_clks(oh);
ret |= _init_opt_clks(oh);
@@ -2363,11 +2368,11 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
* are part of the device's address space can be ioremapped properly.
* No return value.
*/
-static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
+static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
+ struct device_node *np)
{
struct omap_hwmod_addr_space *mem;
void __iomem *va_start = NULL;
- struct device_node *np;
if (!oh)
return;
@@ -2383,12 +2388,10 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
oh->name);
/* Extract the IO space from device tree blob */
- if (!of_have_populated_dt())
+ if (!np)
return;
- np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
- if (np)
- va_start = of_iomap(np, oh->mpu_rt_idx);
+ va_start = of_iomap(np, 0);
} else {
va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
}
@@ -2420,14 +2423,19 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
static int __init _init(struct omap_hwmod *oh, void *data)
{
int r;
+ struct device_node *np = NULL;
if (oh->_state != _HWMOD_STATE_REGISTERED)
return 0;
+ /* If booting with DT, parse the DT node for IO space/clocks etc */
+ if (of_have_populated_dt())
+ np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
+
if (oh->class->sysc)
- _init_mpu_rt_base(oh, NULL);
+ _init_mpu_rt_base(oh, NULL, np);
- r = _init_clocks(oh, NULL);
+ r = _init_clocks(oh, NULL, np);
if (r < 0) {
WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
return -EINVAL;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 32/45] ARM: OMAP2+: Add support to parse optional clk info from DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (30 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 31/45] ARM: OMAP2+: Add support to parse 'main_clk' info from DT Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 33/45] ARM: OMAP2+: hwmod: fix opt_clk handling with DT Tero Kristo
` (12 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
From: Rajendra Nayak <rnayak@ti.com>
With clocks for OMAP moving to DT, its now possible to pass all optional clock
data for each device from DT instead of having it in hwmod.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 66 ++++++++++++++++++++++++++++++++++++--
1 file changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 838af96..116219e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -807,6 +807,65 @@ static int _init_interface_clks(struct omap_hwmod *oh)
return ret;
}
+static const char **_parse_opt_clks_dt(struct omap_hwmod *oh,
+ struct device_node *np,
+ int *opt_clks_cnt)
+{
+ int i, clks_cnt;
+ const char *clk_name;
+ const char **opt_clk_names;
+
+ clks_cnt = of_property_count_strings(np, "clock-names");
+ if (!clks_cnt)
+ return NULL;
+
+ opt_clk_names = kzalloc(sizeof(char *)*clks_cnt, GFP_KERNEL);
+ if (!opt_clk_names)
+ return NULL;
+
+ for (i = 0; i < clks_cnt; i++) {
+ of_property_read_string_index(np, "clock-names", i, &clk_name);
+ if (!strcmp(clk_name, "fck"))
+ continue;
+ opt_clks_cnt++;
+ opt_clk_names[i] = clk_name;
+ }
+ return opt_clk_names;
+}
+
+static int _init_opt_clks_dt(struct omap_hwmod *oh, struct device_node *np)
+{
+ struct clk *c;
+ int i, opt_clks_cnt = 0;
+ int ret = 0;
+ const char **opt_clk_names;
+
+ opt_clk_names = _parse_opt_clks_dt(oh, np, &opt_clks_cnt);
+ if (!opt_clk_names)
+ return -EINVAL;
+
+ oh->opt_clks = kzalloc(sizeof(struct omap_hwmod_opt_clk *)
+ * opt_clks_cnt, GFP_KERNEL);
+ if (!oh->opt_clks)
+ return -ENOMEM;
+
+ oh->opt_clks_cnt = opt_clks_cnt;
+
+ for (i = 0; i < oh->opt_clks_cnt; i++) {
+ c = of_clk_get_by_name(np, opt_clk_names[i]);
+ if (IS_ERR(c)) {
+ pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
+ oh->name, opt_clk_names[i]);
+ ret = -EINVAL;
+ }
+ oh->opt_clks[i]._clk = c;
+ oh->opt_clks[i].role = opt_clk_names[i];
+ oh->opt_clks_cnt++;
+ clk_prepare(oh->opt_clks[i]._clk);
+ }
+ return ret;
+}
+
/**
* _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
* @oh: struct omap_hwmod *
@@ -814,13 +873,16 @@ static int _init_interface_clks(struct omap_hwmod *oh)
* Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
* clock pointers. Returns 0 on success or -EINVAL on error.
*/
-static int _init_opt_clks(struct omap_hwmod *oh)
+static int _init_opt_clks(struct omap_hwmod *oh, struct device_node *np)
{
struct omap_hwmod_opt_clk *oc;
struct clk *c;
int i;
int ret = 0;
+ if (of_get_property(np, "clocks", NULL))
+ return _init_opt_clks_dt(oh, np);
+
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
c = clk_get(NULL, oc->clk);
if (IS_ERR(c)) {
@@ -1582,7 +1644,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data,
ret |= _init_main_clk(oh, np);
ret |= _init_interface_clks(oh);
- ret |= _init_opt_clks(oh);
+ ret |= _init_opt_clks(oh, np);
if (!ret)
oh->_state = _HWMOD_STATE_CLKS_INITED;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 33/45] ARM: OMAP2+: hwmod: fix opt_clk handling with DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (31 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 32/45] ARM: OMAP2+: Add support to parse optional clk " Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 34/45] ARM: OMAP2+: timer: fix boot crash with DT only boot and DT clocks Tero Kristo
` (11 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
Rajendra's patch had a bug which caused opt clocks to fail initialize
completely, causing boot warnings with devices that depend on them.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 116219e..f24246c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -827,8 +827,7 @@ static const char **_parse_opt_clks_dt(struct omap_hwmod *oh,
of_property_read_string_index(np, "clock-names", i, &clk_name);
if (!strcmp(clk_name, "fck"))
continue;
- opt_clks_cnt++;
- opt_clk_names[i] = clk_name;
+ opt_clk_names[(*opt_clks_cnt)++] = clk_name;
}
return opt_clk_names;
}
@@ -851,7 +850,7 @@ static int _init_opt_clks_dt(struct omap_hwmod *oh, struct device_node *np)
oh->opt_clks_cnt = opt_clks_cnt;
- for (i = 0; i < oh->opt_clks_cnt; i++) {
+ for (i = 0; i < opt_clks_cnt; i++) {
c = of_clk_get_by_name(np, opt_clk_names[i]);
if (IS_ERR(c)) {
pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 34/45] ARM: OMAP2+: timer: fix boot crash with DT only boot and DT clocks
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (32 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 33/45] ARM: OMAP2+: hwmod: fix opt_clk handling with DT Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 35/45] ARM: OMAP4: dts: Add main and optional clock data into DT Tero Kristo
` (10 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
Timer failed to init properly with DT clock data, as it still tried
to use clock info from hwmod. Changed init order slightly so that
timer hwmod is initialized earlier, which also makes sure the
timer clock is initialized and can be referenced from the driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/timer.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1e77f11..bf8467c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -276,8 +276,13 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
if (!timer->io_base)
return -ENXIO;
+ omap_hwmod_setup_one(oh_name);
+
/* After the dmtimer is using hwmod these clocks won't be needed */
- timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
+ if (oh->_clk)
+ timer->fclk = oh->_clk;
+ else
+ timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
if (IS_ERR(timer->fclk))
return PTR_ERR(timer->fclk);
@@ -297,7 +302,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
clk_put(src);
- omap_hwmod_setup_one(oh_name);
omap_hwmod_enable(oh);
__omap_dm_timer_init_regs(timer);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 35/45] ARM: OMAP4: dts: Add main and optional clock data into DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (33 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 34/45] ARM: OMAP2+: timer: fix boot crash with DT only boot and DT clocks Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 36/45] ARM: dts: omap3: " Tero Kristo
` (9 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
From: Rajendra Nayak <rnayak@ti.com>
With support to parse clock data from DT, move all main and optional
clock information from hwmod to DT.
We still retain clocks in hwmod for devices which do not have a DT node.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[t-kristo@ti.com: refreshed against latest hwmod data]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap4.dtsi | 100 +++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 109 ----------------------------
2 files changed, 100 insertions(+), 109 deletions(-)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 22d9f2b..0b35761 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,8 @@
compatible = "ti,omap-counter32k";
reg = <0x4a304000 0x20>;
ti,hwmods = "counter_32k";
+ clocks = <&sys_32k_ck>;
+ clock-names = "fck";
};
omap4_pmx_core: pinmux@4a100040 {
@@ -136,6 +138,8 @@
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
+ clocks = <&l3_div_ck>;
+ clock-names = "fck";
};
gpio1: gpio@4a310000 {
@@ -143,6 +147,8 @@
reg = <0x4a310000 0x200>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio1";
+ clocks = <&l4_wkup_clk_mux_ck>, <&gpio1_dbclk>;
+ clock-names = "fck", "dbclk";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
@@ -155,6 +161,8 @@
reg = <0x48055000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio2";
+ clocks = <&l4_div_ck>, <&gpio2_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -166,6 +174,8 @@
reg = <0x48057000 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio3";
+ clocks = <&l4_div_ck>, <&gpio3_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -177,6 +187,8 @@
reg = <0x48059000 0x200>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio4";
+ clocks = <&l4_div_ck>, <&gpio4_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -188,6 +200,8 @@
reg = <0x4805b000 0x200>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio5";
+ clocks = <&l4_div_ck>, <&gpio5_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -199,6 +213,8 @@
reg = <0x4805d000 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio6";
+ clocks = <&l4_div_ck>, <&gpio6_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -221,6 +237,8 @@
reg = <0x4806a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -229,6 +247,8 @@
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -237,6 +257,8 @@
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -245,6 +267,8 @@
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -255,6 +279,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
i2c2: i2c@48072000 {
@@ -264,6 +290,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
i2c3: i2c@48060000 {
@@ -273,6 +301,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
i2c4: i2c@48350000 {
@@ -282,6 +312,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
mcspi1: spi@48098000 {
@@ -291,6 +323,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
@@ -311,6 +345,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
@@ -326,6 +362,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>, <&sdma 16>;
dma-names = "tx0", "rx0";
@@ -338,6 +376,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
@@ -348,6 +388,8 @@
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
+ clocks = <&hsmmc1_fclk>;
+ clock-names = "fck";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma 61>, <&sdma 62>;
@@ -359,6 +401,8 @@
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
+ clocks = <&hsmmc2_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
@@ -369,6 +413,8 @@
reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
@@ -379,6 +425,8 @@
reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
dma-names = "tx", "rx";
@@ -389,6 +437,8 @@
reg = <0x480d5000 0x400>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc5";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 59>, <&sdma 60>;
dma-names = "tx", "rx";
@@ -399,6 +449,8 @@
reg = <0x4a314000 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
+ clocks = <&sys_32k_ck>;
+ clock-names = "fck";
};
mcpdm: mcpdm@40132000 {
@@ -408,6 +460,8 @@
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mcpdm";
+ clocks = <&pad_clks_ck>;
+ clock-names = "fck";
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
@@ -420,6 +474,8 @@
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dmic";
+ clocks = <&func_dmic_abe_gfclk>;
+ clock-names = "fck";
dmas = <&sdma 67>;
dma-names = "up_link";
};
@@ -433,6 +489,8 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
+ clocks = <&func_mcbsp1_gfclk>, <&pad_clks_ck>, <&mcbsp1_sync_mux_ck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
@@ -447,6 +505,8 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp2";
+ clocks = <&func_mcbsp2_gfclk>, <&pad_clks_ck>, <&mcbsp2_sync_mux_ck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
@@ -461,6 +521,8 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
+ clocks = <&func_mcbsp3_gfclk>, <&pad_clks_ck>, <&mcbsp3_sync_mux_ck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
@@ -474,6 +536,8 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
+ clocks = <&per_mcbsp4_gfclk>, <&pad_clks_ck>, <&mcbsp4_sync_mux_ck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
@@ -485,6 +549,8 @@
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
reg-names = "mpu";
ti,hwmods = "kbd";
+ clocks = <&sys_32k_ck>;
+ clock-names = "fck";
};
emif1: emif@4c000000 {
@@ -492,6 +558,8 @@
reg = <0x4c000000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif1";
+ clocks = <&ddrphy_ck>;
+ clock-names = "fck";
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
@@ -503,6 +571,8 @@
reg = <0x4d000000 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif2";
+ clocks = <&ddrphy_ck>;
+ clock-names = "fck";
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
@@ -516,6 +586,8 @@
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp_usb_phy";
+ clocks = <&ocp2scp_usb_phy_phy_48m>;
+ clock-names = "fck";
usb2_phy: usb2phy@4a0ad080 {
compatible = "ti,omap-usb2";
reg = <0x4a0ad080 0x58>;
@@ -528,6 +600,8 @@
reg = <0x4a318000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
+ clocks = <&dmt1_clk_mux>;
+ clock-names = "fck";
ti,timer-alwon;
};
@@ -536,6 +610,8 @@
reg = <0x48032000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
+ clocks = <&cm2_dm2_mux>;
+ clock-names = "fck";
};
timer3: timer@48034000 {
@@ -543,6 +619,8 @@
reg = <0x48034000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
+ clocks = <&cm2_dm3_mux>;
+ clock-names = "fck";
};
timer4: timer@48036000 {
@@ -550,6 +628,8 @@
reg = <0x48036000 0x80>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer4";
+ clocks = <&cm2_dm4_mux>;
+ clock-names = "fck";
};
timer5: timer@40138000 {
@@ -558,6 +638,8 @@
<0x49038000 0x80>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer5";
+ clocks = <&timer5_sync_mux>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -567,6 +649,8 @@
<0x4903a000 0x80>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer6";
+ clocks = <&timer6_sync_mux>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -576,6 +660,8 @@
<0x4903c000 0x80>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer7";
+ clocks = <&timer7_sync_mux>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -585,6 +671,8 @@
<0x4903e000 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
+ clocks = <&timer8_sync_mux>;
+ clock-names = "fck";
ti,timer-pwm;
ti,timer-dsp;
};
@@ -594,6 +682,8 @@
reg = <0x4803e000 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
+ clocks = <&cm2_dm9_mux>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -602,6 +692,8 @@
reg = <0x48086000 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
+ clocks = <&cm2_dm10_mux>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -610,6 +702,8 @@
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
+ clocks = <&cm2_dm11_mux>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -618,12 +712,16 @@
reg = <0x4a062000 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "usb_tll_hs";
+ clocks = <&usb_tll_hs_ick>;
+ clock-names = "fck";
};
usbhshost: usbhshost@4a064000 {
compatible = "ti,usbhs-host";
reg = <0x4a064000 0x800>;
ti,hwmods = "usb_host_hs";
+ clocks = <&usb_host_hs_fck>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -657,6 +755,8 @@
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
+ clocks = <&usb_otg_hs_ick>, <&usb_otg_hs_xclk>;
+ clock-names = "fck", "xclk";
usb-phy = <&usb2_phy>;
multipoint = <1>;
num-eps = <16>;
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 9c3b504..6543383 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -334,7 +334,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
.class = &omap44xx_counter_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
@@ -479,7 +478,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
.class = &omap44xx_dma_hwmod_class,
.clkdm_name = "l3_dma_clkdm",
.mpu_irqs = omap44xx_dma_system_irqs,
- .main_clk = "l3_div_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
@@ -514,7 +512,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
.name = "dmic",
.class = &omap44xx_dmic_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "func_dmic_abe_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
@@ -915,7 +912,6 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
.class = &omap44xx_emif_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .main_clk = "ddrphy_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
@@ -931,7 +927,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
.class = &omap44xx_emif_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .main_clk = "ddrphy_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
@@ -1015,15 +1010,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
static struct omap_hwmod omap44xx_gpio1_hwmod = {
.name = "gpio1",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .main_clk = "l4_wkup_clk_mux_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
@@ -1031,22 +1022,16 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
static struct omap_hwmod omap44xx_gpio2_hwmod = {
.name = "gpio2",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
@@ -1054,22 +1039,16 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
static struct omap_hwmod omap44xx_gpio3_hwmod = {
.name = "gpio3",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
@@ -1077,22 +1056,16 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio4_dbclk" },
-};
static struct omap_hwmod omap44xx_gpio4_hwmod = {
.name = "gpio4",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
@@ -1100,22 +1073,16 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio5 */
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio5_dbclk" },
-};
static struct omap_hwmod omap44xx_gpio5_hwmod = {
.name = "gpio5",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
@@ -1123,22 +1090,16 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio5_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio6 */
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio6_dbclk" },
-};
static struct omap_hwmod omap44xx_gpio6_hwmod = {
.name = "gpio6",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
@@ -1146,8 +1107,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio6_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.dev_attr = &gpio_dev_attr,
};
@@ -1337,7 +1296,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
@@ -1354,7 +1312,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
@@ -1371,7 +1328,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
@@ -1388,7 +1344,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
@@ -1542,7 +1497,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
.name = "kbd",
.class = &omap44xx_kbd_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
@@ -1643,16 +1597,11 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
};
/* mcbsp1 */
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
-};
static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp1_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
@@ -1660,21 +1609,14 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mcbsp1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
};
/* mcbsp2 */
-static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
-};
static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp2_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
@@ -1682,21 +1624,14 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mcbsp2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
};
/* mcbsp3 */
-static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
-};
static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp3_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
@@ -1704,21 +1639,14 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mcbsp3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
};
/* mcbsp4 */
-static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
-};
static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .main_clk = "per_mcbsp4_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
@@ -1726,8 +1654,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mcbsp4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
};
/*
@@ -1768,7 +1694,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
* results 'slow motion' audio playback.
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
- .main_clk = "pad_clks_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
@@ -1823,7 +1748,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.sdma_reqs = omap44xx_mcspi1_sdma_reqs,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
@@ -1853,7 +1777,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.sdma_reqs = omap44xx_mcspi2_sdma_reqs,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
@@ -1883,7 +1806,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.sdma_reqs = omap44xx_mcspi3_sdma_reqs,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
@@ -1911,7 +1833,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.sdma_reqs = omap44xx_mcspi4_sdma_reqs,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
@@ -1961,7 +1882,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.sdma_reqs = omap44xx_mmc1_sdma_reqs,
- .main_clk = "hsmmc1_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
@@ -1984,7 +1904,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.sdma_reqs = omap44xx_mmc2_sdma_reqs,
- .main_clk = "hsmmc2_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
@@ -2006,7 +1925,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.sdma_reqs = omap44xx_mmc3_sdma_reqs,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
@@ -2028,7 +1946,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.sdma_reqs = omap44xx_mmc4_sdma_reqs,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
@@ -2050,7 +1967,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.sdma_reqs = omap44xx_mmc5_sdma_reqs,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
@@ -2261,7 +2177,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
* So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
* to be the best workaround.
*/
- .main_clk = "ocp2scp_usb_phy_phy_48m",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -2629,7 +2544,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "dmt1_clk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
@@ -2646,7 +2560,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "cm2_dm2_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
@@ -2661,7 +2574,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
.name = "timer3",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm3_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
@@ -2676,7 +2588,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
.name = "timer4",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm4_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
@@ -2691,7 +2602,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
.name = "timer5",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer5_sync_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
@@ -2707,7 +2617,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
.name = "timer6",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer6_sync_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
@@ -2723,7 +2632,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
.name = "timer7",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer7_sync_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
@@ -2739,7 +2647,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
.name = "timer8",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer8_sync_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
@@ -2755,7 +2662,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
.name = "timer9",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm9_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
@@ -2772,7 +2678,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "cm2_dm10_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
@@ -2788,7 +2693,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
.name = "timer11",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm11_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
@@ -2827,7 +2731,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
@@ -2843,7 +2746,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
@@ -2859,7 +2761,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
@@ -2875,7 +2776,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
@@ -2954,7 +2854,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
.name = "usb_host_hs",
.class = &omap44xx_usb_host_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_host_hs_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
@@ -3036,16 +2935,12 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
};
/* usb_otg_hs */
-static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
- { .role = "xclk", .clk = "usb_otg_hs_xclk" },
-};
static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.name = "usb_otg_hs",
.class = &omap44xx_usb_otg_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "usb_otg_hs_ick",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
@@ -3053,8 +2948,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = usb_otg_hs_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
};
/*
@@ -3082,7 +2975,6 @@ static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
.name = "usb_tll_hs",
.class = &omap44xx_usb_tll_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_tll_hs_ick",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
@@ -3121,7 +3013,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 36/45] ARM: dts: omap3: Add main and optional clock data into DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (34 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 35/45] ARM: OMAP4: dts: Add main and optional clock data into DT Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 37/45] ARM: OMAP3: hwmod_data: remove main and optional clock info from hwmod Tero Kristo
` (8 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
With support to partse clock data from DT, move all main and optional
clock information from hwmod to DT.
We still retain clocks in hwmod for devices which do not have a DT node.
Also, this patch does not remove the clock info from hwmod yet, to
retain legacy boot mode support.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap3.dtsi | 82 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 939cc20..b7b5522 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -80,6 +80,8 @@
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
ti,hwmods = "counter_32k";
+ clocks = <&wkup_32k_fck>;
+ clock-names = "fck";
};
intc: interrupt-controller@48200000 {
@@ -100,6 +102,8 @@
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <96>;
+ clocks = <&core_l3_ick>;
+ clock-names = "fck";
};
omap3_pmx_core: pinmux@48002030 {
@@ -125,6 +129,8 @@
reg = <0x48310000 0x200>;
interrupts = <29>;
ti,hwmods = "gpio1";
+ clocks = <&gpio1_ick>, <&gpio1_dbck>;
+ clock-names = "fck", "dbclk";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
@@ -137,6 +143,8 @@
reg = <0x49050000 0x200>;
interrupts = <30>;
ti,hwmods = "gpio2";
+ clocks = <&gpio2_ick>, <&gpio2_dbck>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -148,6 +156,8 @@
reg = <0x49052000 0x200>;
interrupts = <31>;
ti,hwmods = "gpio3";
+ clocks = <&gpio3_ick>, <&gpio3_dbck>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -159,6 +169,8 @@
reg = <0x49054000 0x200>;
interrupts = <32>;
ti,hwmods = "gpio4";
+ clocks = <&gpio4_ick>, <&gpio4_dbck>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -170,6 +182,8 @@
reg = <0x49056000 0x200>;
interrupts = <33>;
ti,hwmods = "gpio5";
+ clocks = <&gpio5_ick>, <&gpio5_dbck>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -181,6 +195,8 @@
reg = <0x49058000 0x200>;
interrupts = <34>;
ti,hwmods = "gpio6";
+ clocks = <&gpio6_ick>, <&gpio6_dbck>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -190,18 +206,24 @@
uart1: serial@4806a000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart1";
+ clocks = <&uart1_fck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
uart2: serial@4806c000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart2";
+ clocks = <&uart2_fck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
uart3: serial@49020000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart3";
+ clocks = <&uart3_fck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -210,6 +232,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
+ clocks = <&i2c1_fck>;
+ clock-names = "fck";
};
i2c2: i2c@48072000 {
@@ -217,6 +241,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
+ clocks = <&i2c2_fck>;
+ clock-names = "fck";
};
i2c3: i2c@48060000 {
@@ -224,6 +250,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
+ clocks = <&i2c3_fck>;
+ clock-names = "fck";
};
mcspi1: spi@48098000 {
@@ -231,6 +259,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
+ clocks = <&mcspi1_fck>;
+ clock-names = "fck";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
@@ -249,6 +279,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
+ clocks = <&mcspi2_fck>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
@@ -262,6 +294,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
+ clocks = <&mcspi3_fck>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>,
<&sdma 16>,
@@ -275,6 +309,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
+ clocks = <&mcspi4_fck>;
+ clock-names = "fck";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
@@ -283,6 +319,8 @@
mmc1: mmc@4809c000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc1";
+ clocks = <&mmchs1_fck>, <&omap_32k_fck>;
+ clock-names = "fck", "dbck";
ti,dual-volt;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
@@ -291,6 +329,8 @@
mmc2: mmc@480b4000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc2";
+ clocks = <&mmchs2_fck>, <&omap_32k_fck>;
+ clock-names = "fck", "dbck";
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
};
@@ -298,6 +338,8 @@
mmc3: mmc@480ad000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc3";
+ clocks = <&mmchs3_fck>, <&omap_32k_fck>;
+ clock-names = "fck", "dbck";
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
};
@@ -305,6 +347,8 @@
wdt2: wdt@48314000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
+ clocks = <&wdt2_fck>;
+ clock-names = "fck";
};
mcbsp1: mcbsp@48074000 {
@@ -317,6 +361,8 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
+ clocks = <&mcbsp1_fck>, <&mcbsp_clks>, <&core_96m_fck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
@@ -366,6 +412,8 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
+ clocks = <&mcbsp4_fck>, <&mcbsp_clks>, <&per_96m_fck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
@@ -381,6 +429,8 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp5";
+ clocks = <&mcbsp5_fck>, <&mcbsp_clks>, <&core_96m_fck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 21>,
<&sdma 22>;
dma-names = "tx", "rx";
@@ -391,6 +441,8 @@
reg = <0x48318000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
+ clocks = <&gpt1_fck>;
+ clock-names = "fck";
ti,timer-alwon;
};
@@ -399,6 +451,8 @@
reg = <0x49032000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
+ clocks = <&gpt2_fck>;
+ clock-names = "fck";
};
timer3: timer@49034000 {
@@ -406,6 +460,8 @@
reg = <0x49034000 0x400>;
interrupts = <39>;
ti,hwmods = "timer3";
+ clocks = <&gpt3_fck>;
+ clock-names = "fck";
};
timer4: timer@49036000 {
@@ -413,6 +469,8 @@
reg = <0x49036000 0x400>;
interrupts = <40>;
ti,hwmods = "timer4";
+ clocks = <&gpt4_fck>;
+ clock-names = "fck";
};
timer5: timer@49038000 {
@@ -420,6 +478,8 @@
reg = <0x49038000 0x400>;
interrupts = <41>;
ti,hwmods = "timer5";
+ clocks = <&gpt5_fck>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -428,6 +488,8 @@
reg = <0x4903a000 0x400>;
interrupts = <42>;
ti,hwmods = "timer6";
+ clocks = <&gpt6_fck>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -436,6 +498,8 @@
reg = <0x4903c000 0x400>;
interrupts = <43>;
ti,hwmods = "timer7";
+ clocks = <&gpt7_fck>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -444,6 +508,8 @@
reg = <0x4903e000 0x400>;
interrupts = <44>;
ti,hwmods = "timer8";
+ clocks = <&gpt8_fck>;
+ clock-names = "fck";
ti,timer-pwm;
ti,timer-dsp;
};
@@ -453,6 +519,8 @@
reg = <0x49040000 0x400>;
interrupts = <45>;
ti,hwmods = "timer9";
+ clocks = <&gpt9_fck>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -461,6 +529,8 @@
reg = <0x48086000 0x400>;
interrupts = <46>;
ti,hwmods = "timer10";
+ clocks = <&gpt10_fck>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -469,6 +539,8 @@
reg = <0x48088000 0x400>;
interrupts = <47>;
ti,hwmods = "timer11";
+ clocks = <&gpt11_fck>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -477,6 +549,8 @@
reg = <0x48304000 0x400>;
interrupts = <95>;
ti,hwmods = "timer12";
+ clocks = <&gpt12_fck>;
+ clock-names = "fck";
ti,timer-alwon;
ti,timer-secure;
};
@@ -486,12 +560,16 @@
reg = <0x48062000 0x1000>;
interrupts = <78>;
ti,hwmods = "usb_tll_hs";
+ clocks = <&usbtll_fck>;
+ clock-names = "fck";
};
usbhshost: usbhshost@48064000 {
compatible = "ti,usbhs-host";
reg = <0x48064000 0x400>;
ti,hwmods = "usb_host_hs";
+ clocks = <&usbhost_48m_fck>, <&usbhost_120m_fck>;
+ clock-names = "fck", "ehci_logic_fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -514,6 +592,8 @@
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc";
ti,hwmods = "gpmc";
+ clocks = <&gpmc_fck>;
+ clock-names = "fck";
reg = <0x6e000000 0x02d0>;
interrupts = <20>;
gpmc,num-cs = <8>;
@@ -528,6 +608,8 @@
interrupts = <92>, <93>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
+ clocks = <&hsotgusb_ick>;
+ clock-names = "fck";
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 37/45] ARM: OMAP3: hwmod_data: remove main and optional clock info from hwmod
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (35 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 36/45] ARM: dts: omap3: " Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 38/45] ARM: OMAP2+: omap_device: use dev pointer to optimize code Tero Kristo
` (7 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
With support to parse clock data from DT, remove the main and optional
clock information from hwmod.
We still retain clocks in hwmod for devices which do not have a DT node.
NOTE: This patch should only be merged once non-DT boot support for OMAP3 is
no longer needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 119 ----------------------------
1 file changed, 119 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 0c3a427..52591eb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -200,7 +200,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1",
.mpu_irqs = omap2_timer1_mpu_irqs,
- .main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -219,7 +218,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
static struct omap_hwmod omap3xxx_timer2_hwmod = {
.name = "timer2",
.mpu_irqs = omap2_timer2_mpu_irqs,
- .main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -237,7 +235,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
static struct omap_hwmod omap3xxx_timer3_hwmod = {
.name = "timer3",
.mpu_irqs = omap2_timer3_mpu_irqs,
- .main_clk = "gpt3_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -255,7 +252,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
static struct omap_hwmod omap3xxx_timer4_hwmod = {
.name = "timer4",
.mpu_irqs = omap2_timer4_mpu_irqs,
- .main_clk = "gpt4_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -273,7 +269,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
static struct omap_hwmod omap3xxx_timer5_hwmod = {
.name = "timer5",
.mpu_irqs = omap2_timer5_mpu_irqs,
- .main_clk = "gpt5_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -292,7 +287,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
static struct omap_hwmod omap3xxx_timer6_hwmod = {
.name = "timer6",
.mpu_irqs = omap2_timer6_mpu_irqs,
- .main_clk = "gpt6_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -311,7 +305,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
static struct omap_hwmod omap3xxx_timer7_hwmod = {
.name = "timer7",
.mpu_irqs = omap2_timer7_mpu_irqs,
- .main_clk = "gpt7_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -330,7 +323,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
static struct omap_hwmod omap3xxx_timer8_hwmod = {
.name = "timer8",
.mpu_irqs = omap2_timer8_mpu_irqs,
- .main_clk = "gpt8_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -349,7 +341,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
static struct omap_hwmod omap3xxx_timer9_hwmod = {
.name = "timer9",
.mpu_irqs = omap2_timer9_mpu_irqs,
- .main_clk = "gpt9_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -368,7 +359,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
static struct omap_hwmod omap3xxx_timer10_hwmod = {
.name = "timer10",
.mpu_irqs = omap2_timer10_mpu_irqs,
- .main_clk = "gpt10_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -387,7 +377,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
static struct omap_hwmod omap3xxx_timer11_hwmod = {
.name = "timer11",
.mpu_irqs = omap2_timer11_mpu_irqs,
- .main_clk = "gpt11_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -411,7 +400,6 @@ static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
static struct omap_hwmod omap3xxx_timer12_hwmod = {
.name = "timer12",
.mpu_irqs = omap3xxx_timer12_mpu_irqs,
- .main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -467,7 +455,6 @@ static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap3xxx_wd_timer_hwmod_class,
- .main_clk = "wdt2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -489,7 +476,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
.name = "uart1",
.mpu_irqs = omap2_uart1_mpu_irqs,
.sdma_reqs = omap2_uart1_sdma_reqs,
- .main_clk = "uart1_fck",
.flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap2 = {
@@ -508,7 +494,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
.name = "uart2",
.mpu_irqs = omap2_uart2_mpu_irqs,
.sdma_reqs = omap2_uart2_sdma_reqs,
- .main_clk = "uart2_fck",
.flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap2 = {
@@ -527,7 +512,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
.name = "uart3",
.mpu_irqs = omap2_uart3_mpu_irqs,
.sdma_reqs = omap2_uart3_sdma_reqs,
- .main_clk = "uart3_fck",
.flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
@@ -807,7 +791,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap2_i2c1_mpu_irqs,
.sdma_reqs = omap2_i2c1_sdma_reqs,
- .main_clk = "i2c1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -832,7 +815,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap2_i2c2_mpu_irqs,
.sdma_reqs = omap2_i2c2_sdma_reqs,
- .main_clk = "i2c2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -868,7 +850,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = i2c3_mpu_irqs,
.sdma_reqs = i2c3_sdma_reqs,
- .main_clk = "i2c3_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -911,17 +892,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbck", },
-};
static struct omap_hwmod omap3xxx_gpio1_hwmod = {
.name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio1_irqs,
- .main_clk = "gpio1_ick",
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -936,17 +911,11 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
};
/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbck", },
-};
static struct omap_hwmod omap3xxx_gpio2_hwmod = {
.name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio2_irqs,
- .main_clk = "gpio2_ick",
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -961,17 +930,11 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
};
/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbck", },
-};
static struct omap_hwmod omap3xxx_gpio3_hwmod = {
.name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio3_irqs,
- .main_clk = "gpio3_ick",
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -986,17 +949,11 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
};
/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio4_dbck", },
-};
static struct omap_hwmod omap3xxx_gpio4_hwmod = {
.name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio4_irqs,
- .main_clk = "gpio4_ick",
- .opt_clks = gpio4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1016,17 +973,11 @@ static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
{ .irq = -1 },
};
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio5_dbck", },
-};
static struct omap_hwmod omap3xxx_gpio5_hwmod = {
.name = "gpio5",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio5_irqs,
- .main_clk = "gpio5_ick",
- .opt_clks = gpio5_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1046,17 +997,11 @@ static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
{ .irq = -1 },
};
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio6_dbck", },
-};
static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.name = "gpio6",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio6_irqs,
- .main_clk = "gpio6_ick",
- .opt_clks = gpio6_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1100,7 +1045,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
.name = "dma",
.class = &omap3xxx_dma_hwmod_class,
.mpu_irqs = omap2_dma_system_irqs,
- .main_clk = "core_l3_ick",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1135,15 +1079,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
};
/* McBSP functional clock mapping */
-static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
- { .role = "pad_fck", .clk = "mcbsp_clks" },
- { .role = "prcm_fck", .clk = "core_96m_fck" },
-};
-static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
- { .role = "pad_fck", .clk = "mcbsp_clks" },
- { .role = "prcm_fck", .clk = "per_96m_fck" },
-};
/* mcbsp1 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
@@ -1158,7 +1094,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp1_irqs,
.sdma_reqs = omap2_mcbsp1_sdma_reqs,
- .main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1168,8 +1103,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
},
},
- .opt_clks = mcbsp15_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
};
/* mcbsp2 */
@@ -1189,7 +1122,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_irqs,
.sdma_reqs = omap2_mcbsp2_sdma_reqs,
- .main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1199,8 +1131,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
},
},
- .opt_clks = mcbsp234_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
.dev_attr = &omap34xx_mcbsp2_dev_attr,
};
@@ -1221,7 +1151,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_irqs,
.sdma_reqs = omap2_mcbsp3_sdma_reqs,
- .main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1231,8 +1160,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
},
},
- .opt_clks = mcbsp234_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
.dev_attr = &omap34xx_mcbsp3_dev_attr,
};
@@ -1255,7 +1182,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp4_irqs,
.sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
- .main_clk = "mcbsp4_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1265,8 +1191,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
},
},
- .opt_clks = mcbsp234_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
};
/* mcbsp5 */
@@ -1288,7 +1212,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp5_irqs,
.sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
- .main_clk = "mcbsp5_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1298,8 +1221,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
},
},
- .opt_clks = mcbsp15_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
};
/* 'mcbsp sidetone' class */
@@ -1324,7 +1245,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
.name = "mcbsp2_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
- .main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1346,7 +1266,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
.name = "mcbsp3_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
- .main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1571,7 +1490,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
.name = "mcspi1",
.mpu_irqs = omap2_mcspi1_mpu_irqs,
.sdma_reqs = omap2_mcspi1_sdma_reqs,
- .main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1594,7 +1512,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
.name = "mcspi2",
.mpu_irqs = omap2_mcspi2_mpu_irqs,
.sdma_reqs = omap2_mcspi2_sdma_reqs,
- .main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1630,7 +1547,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
.name = "mcspi3",
.mpu_irqs = omap34xx_mcspi3_mpu_irqs,
.sdma_reqs = omap34xx_mcspi3_sdma_reqs,
- .main_clk = "mcspi3_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1664,7 +1580,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
.name = "mcspi4",
.mpu_irqs = omap34xx_mcspi4_mpu_irqs,
.sdma_reqs = omap34xx_mcspi4_sdma_reqs,
- .main_clk = "mcspi4_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1707,7 +1622,6 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
.name = "usb_otg_hs",
.mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
- .main_clk = "hsotgusb_ick",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1782,9 +1696,6 @@ static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
{ .dma_req = -1 }
};
-static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
- { .role = "dbck", .clk = "omap_32k_fck", },
-};
static struct omap_mmc_dev_attr mmc1_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
@@ -1800,9 +1711,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
.name = "mmc1",
.mpu_irqs = omap34xx_mmc1_mpu_irqs,
.sdma_reqs = omap34xx_mmc1_sdma_reqs,
- .opt_clks = omap34xx_mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
- .main_clk = "mmchs1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1820,9 +1728,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
.name = "mmc1",
.mpu_irqs = omap34xx_mmc1_mpu_irqs,
.sdma_reqs = omap34xx_mmc1_sdma_reqs,
- .opt_clks = omap34xx_mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
- .main_clk = "mmchs1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1849,9 +1754,6 @@ static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
{ .dma_req = -1 }
};
-static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
- { .role = "dbck", .clk = "omap_32k_fck", },
-};
/* See 35xx errata 2.1.1.128 in SPRZ278F */
static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
@@ -1862,9 +1764,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
.name = "mmc2",
.mpu_irqs = omap34xx_mmc2_mpu_irqs,
.sdma_reqs = omap34xx_mmc2_sdma_reqs,
- .opt_clks = omap34xx_mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
- .main_clk = "mmchs2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1882,9 +1781,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
.name = "mmc2",
.mpu_irqs = omap34xx_mmc2_mpu_irqs,
.sdma_reqs = omap34xx_mmc2_sdma_reqs,
- .opt_clks = omap34xx_mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
- .main_clk = "mmchs2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -1910,17 +1806,11 @@ static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
{ .dma_req = -1 }
};
-static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
- { .role = "dbck", .clk = "omap_32k_fck", },
-};
static struct omap_hwmod omap3xxx_mmc3_hwmod = {
.name = "mmc3",
.mpu_irqs = omap34xx_mmc3_mpu_irqs,
.sdma_reqs = omap34xx_mmc3_sdma_reqs,
- .opt_clks = omap34xx_mmc3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
- .main_clk = "mmchs3_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1954,9 +1844,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
.sysc = &omap3xxx_usb_host_hs_sysc,
};
-static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
- { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
-};
static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
{ .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
@@ -1969,7 +1856,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
.class = &omap3xxx_usb_host_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap3xxx_usb_host_hs_irqs,
- .main_clk = "usbhost_48m_fck",
.prcm = {
.omap2 = {
.module_offs = OMAP3430ES2_USBHOST_MOD,
@@ -1980,8 +1866,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
.idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
},
},
- .opt_clks = omap3xxx_usb_host_hs_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
/*
* Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -2062,7 +1946,6 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
.class = &omap3xxx_usb_tll_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap3xxx_usb_tll_hs_irqs,
- .main_clk = "usbtll_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
@@ -2139,7 +2022,6 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
.class = &omap3xxx_counter_hwmod_class,
.clkdm_name = "wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkup_32k_fck",
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
@@ -2181,7 +2063,6 @@ static struct omap_hwmod omap3xxx_gpmc_hwmod = {
.class = &omap3xxx_gpmc_hwmod_class,
.clkdm_name = "core_l3_clkdm",
.mpu_irqs = omap3xxx_gpmc_irqs,
- .main_clk = "gpmc_fck",
/*
* XXX HWMOD_INIT_NO_RESET should not be needed for this IP
* block. It is not being added due to any known bugs with
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 38/45] ARM: OMAP2+: omap_device: use dev pointer to optimize code
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (36 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 37/45] ARM: OMAP3: hwmod_data: remove main and optional clock info from hwmod Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 39/45] ARM: OMAP2+: omap_device: no need to add a clock dev for aliases Tero Kristo
` (6 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
From: Nishanth Menon <nm@ti.com>
_add_clkdev uses &od->pdev->dev for all reference of device struct.
Simplify the usage with a variable.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_device.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index f99f68e..070d17b 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -47,31 +47,29 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
{
struct clk *r;
struct clk_lookup *l;
+ struct device *dev = &od->pdev->dev;
if (!clk_alias || !clk_name)
return;
- dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
+ dev_dbg(dev, "Creating %s -> %s\n", clk_alias, clk_name);
- r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
+ r = clk_get_sys(dev_name(dev), clk_alias);
if (!IS_ERR(r)) {
- dev_warn(&od->pdev->dev,
- "alias %s already exists\n", clk_alias);
+ dev_warn(dev, "alias %s already exists\n", clk_alias);
clk_put(r);
return;
}
r = clk_get(NULL, clk_name);
if (IS_ERR(r)) {
- dev_err(&od->pdev->dev,
- "clk_get for %s failed\n", clk_name);
+ dev_err(dev, "clk_get for %s failed\n", clk_name);
return;
}
- l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
+ l = clkdev_alloc(r, clk_alias, dev_name(dev));
if (!l) {
- dev_err(&od->pdev->dev,
- "clkdev_alloc for %s failed\n", clk_alias);
+ dev_err(dev, "clkdev_alloc for %s failed\n", clk_alias);
return;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 39/45] ARM: OMAP2+: omap_device: no need to add a clock dev for aliases
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (37 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 38/45] ARM: OMAP2+: omap_device: use dev pointer to optimize code Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 40/45] ARM: OMAP2+: omap_device: use dt aware clk_get to lookup clk Tero Kristo
` (5 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
From: Nishanth Menon <nm@ti.com>
When we create aliases, we have an handy clk_add_alias which
can be used instead of creating new nodes in the clock tree.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_device.c | 19 +++++--------------
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 070d17b..7c796e2 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -45,8 +45,8 @@
static void _add_clkdev(struct omap_device *od, const char *clk_alias,
const char *clk_name)
{
+ int ret;
struct clk *r;
- struct clk_lookup *l;
struct device *dev = &od->pdev->dev;
if (!clk_alias || !clk_name)
@@ -61,19 +61,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
return;
}
- r = clk_get(NULL, clk_name);
- if (IS_ERR(r)) {
- dev_err(dev, "clk_get for %s failed\n", clk_name);
- return;
- }
-
- l = clkdev_alloc(r, clk_alias, dev_name(dev));
- if (!l) {
- dev_err(dev, "clkdev_alloc for %s failed\n", clk_alias);
- return;
- }
-
- clkdev_add(l);
+ ret = clk_add_alias(clk_alias, dev_name(dev), (char *)clk_name, dev);
+ if (ret)
+ dev_err(dev, "Failed to alias %s to %s: %d\n", clk_alias,
+ clk_name, ret);
}
/**
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 40/45] ARM: OMAP2+: omap_device: use dt aware clk_get to lookup clk
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (38 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 39/45] ARM: OMAP2+: omap_device: no need to add a clock dev for aliases Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 41/45] ARM: dts: omap5: Add main and optional clock data into DT Tero Kristo
` (4 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
From: Nishanth Menon <nm@ti.com>
clk_get does a check to find nodes on DT prior to trying clk_get_sys.
To make omap_device dt clock node aware, use clk_get instead of
clk_get_sys.
As part of this, add warnings for device node entries which do not
declare their own clock nodes for the expected aliases.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap_device.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 7c796e2..9946900 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -48,19 +48,25 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
int ret;
struct clk *r;
struct device *dev = &od->pdev->dev;
+ struct device_node *node = dev->of_node;
if (!clk_alias || !clk_name)
return;
dev_dbg(dev, "Creating %s -> %s\n", clk_alias, clk_name);
- r = clk_get_sys(dev_name(dev), clk_alias);
+ r = clk_get(dev, clk_alias);
if (!IS_ERR(r)) {
- dev_warn(dev, "alias %s already exists\n", clk_alias);
+ if (!node)
+ dev_warn(dev, "alias '%s' already exists\n", clk_alias);
clk_put(r);
return;
}
+ if (node)
+ dev_err(dev, "FIXME: clock-name '%s' DOES NOT exist in dt!\n",
+ clk_alias);
+
ret = clk_add_alias(clk_alias, dev_name(dev), (char *)clk_name, dev);
if (ret)
dev_err(dev, "Failed to alias %s to %s: %d\n", clk_alias,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 41/45] ARM: dts: omap5: Add main and optional clock data into DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (39 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 40/45] ARM: OMAP2+: omap_device: use dt aware clk_get to lookup clk Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 42/45] ARM: dts: am335x: " Tero Kristo
` (3 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
With support to parse clock data from DT, move all main and optional
clock information from hwmod to DT.
We still retain clocks in hwmod for devices which do not have a DT node.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap5.dtsi | 102 ++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 119 ----------------------------
2 files changed, 102 insertions(+), 119 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 59f7246..d269355 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -100,6 +100,8 @@
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
ti,hwmods = "counter_32k";
+ clocks = <&wkupaon_iclk_mux>;
+ clock-names = "fck";
};
omap5_pmx_core: pinmux@4a002840 {
@@ -129,6 +131,8 @@
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
};
gpio1: gpio@4ae10000 {
@@ -136,6 +140,8 @@
reg = <0x4ae10000 0x200>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio1";
+ clocks = <&wkupaon_iclk_mux>, <&gpio1_dbclk>;
+ clock-names = "fck", "dbclk";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
@@ -148,6 +154,8 @@
reg = <0x48055000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio2";
+ clocks = <&l4_root_clk_div>, <&gpio2_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -159,6 +167,8 @@
reg = <0x48057000 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio3";
+ clocks = <&l4_root_clk_div>, <&gpio3_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -170,6 +180,8 @@
reg = <0x48059000 0x200>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio4";
+ clocks = <&l4_root_clk_div>, <&gpio4_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -181,6 +193,8 @@
reg = <0x4805b000 0x200>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio5";
+ clocks = <&l4_root_clk_div>, <&gpio5_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -192,6 +206,8 @@
reg = <0x4805d000 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio6";
+ clocks = <&l4_root_clk_div>, <&gpio6_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -203,6 +219,8 @@
reg = <0x48051000 0x200>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio7";
+ clocks = <&l4_root_clk_div>, <&gpio7_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -214,6 +232,8 @@
reg = <0x48053000 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio8";
+ clocks = <&l4_root_clk_div>, <&gpio8_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -238,6 +258,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
i2c2: i2c@48072000 {
@@ -247,6 +269,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
i2c3: i2c@48060000 {
@@ -256,6 +280,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
i2c4: i2c@4807a000 {
@@ -265,6 +291,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
i2c5: i2c@4807c000 {
@@ -274,6 +302,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c5";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
};
mcspi1: spi@48098000 {
@@ -283,6 +313,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
@@ -303,6 +335,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
@@ -318,6 +352,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>, <&sdma 16>;
dma-names = "tx0", "rx0";
@@ -330,6 +366,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
@@ -340,6 +378,8 @@
reg = <0x4806a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -348,6 +388,8 @@
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -356,6 +398,8 @@
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -364,6 +408,8 @@
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -372,6 +418,8 @@
reg = <0x48066000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -380,6 +428,8 @@
reg = <0x48068000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
clock-frequency = <48000000>;
};
@@ -388,6 +438,8 @@
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
+ clocks = <&mmc1_fclk>, <&mmc1_32khz_clk>;
+ clock-names = "fck", "32khz_clk";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma 61>, <&sdma 62>;
@@ -399,6 +451,8 @@
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
+ clocks = <&mmc2_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
@@ -409,6 +463,8 @@
reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
@@ -419,6 +475,8 @@
reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
dma-names = "tx", "rx";
@@ -429,6 +487,8 @@
reg = <0x480d5000 0x400>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc5";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
ti,needs-special-reset;
dmas = <&sdma 59>, <&sdma 60>;
dma-names = "tx", "rx";
@@ -438,6 +498,8 @@
compatible = "ti,omap4-keypad";
reg = <0x4ae1c000 0x400>;
ti,hwmods = "kbd";
+ clocks = <&sys_32k_ck>;
+ clock-names = "fck";
};
mcpdm: mcpdm@40132000 {
@@ -447,6 +509,8 @@
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mcpdm";
+ clocks = <&pad_clks_ck>;
+ clock-names = "fck";
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
@@ -459,6 +523,8 @@
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dmic";
+ clocks = <&dmic_gfclk>;
+ clock-names = "fck";
dmas = <&sdma 67>;
dma-names = "up_link";
};
@@ -472,6 +538,8 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
+ clocks = <&mcbsp1_gfclk>, <&pad_clks_ck>, <&mcbsp1_sync_mux_ck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
@@ -486,6 +554,8 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp2";
+ clocks = <&mcbsp2_gfclk>, <&pad_clks_ck>, <&mcbsp2_sync_mux_ck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
@@ -500,6 +570,8 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
+ clocks = <&mcbsp3_gfclk>, <&pad_clks_ck>, <&mcbsp3_sync_mux_ck>;
+ clock-names = "fck", "pad_fck", "prcm_fck";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
@@ -510,6 +582,8 @@
reg = <0x4ae18000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
+ clocks = <&timer1_gfclk_mux>;
+ clock-names = "fck";
ti,timer-alwon;
};
@@ -518,6 +592,8 @@
reg = <0x48032000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
+ clocks = <&timer2_gfclk_mux>;
+ clock-names = "fck";
};
timer3: timer@48034000 {
@@ -525,6 +601,8 @@
reg = <0x48034000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
+ clocks = <&timer3_gfclk_mux>;
+ clock-names = "fck";
};
timer4: timer@48036000 {
@@ -532,6 +610,8 @@
reg = <0x48036000 0x80>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer4";
+ clocks = <&timer4_gfclk_mux>;
+ clock-names = "fck";
};
timer5: timer@40138000 {
@@ -540,6 +620,8 @@
<0x49038000 0x80>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer5";
+ clocks = <&timer5_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
ti,timer-pwm;
};
@@ -550,6 +632,8 @@
<0x4903a000 0x80>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer6";
+ clocks = <&timer6_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
ti,timer-pwm;
};
@@ -560,6 +644,8 @@
<0x4903c000 0x80>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer7";
+ clocks = <&timer7_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -569,6 +655,8 @@
<0x4903e000 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
+ clocks = <&timer8_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
ti,timer-pwm;
};
@@ -578,6 +666,8 @@
reg = <0x4803e000 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
+ clocks = <&timer9_gfclk_mux>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -586,6 +676,8 @@
reg = <0x48086000 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
+ clocks = <&timer10_gfclk_mux>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -594,6 +686,8 @@
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
+ clocks = <&timer11_gfclk_mux>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -602,11 +696,15 @@
reg = <0x4ae14000 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
+ clocks = <&sys_32k_ck>;
+ clock-names = "fck";
};
emif1: emif@0x4c000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif1";
+ clocks = <&dpll_core_h11x2_ck>;
+ clock-names = "fck";
phy-type = <2>; /* DDR PHY type: Intelli PHY */
reg = <0x4c000000 0x400>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -618,6 +716,8 @@
emif2: emif@0x4d000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif2";
+ clocks = <&dpll_core_h11x2_ck>;
+ clock-names = "fck";
phy-type = <2>; /* DDR PHY type: Intelli PHY */
reg = <0x4d000000 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
@@ -637,6 +737,8 @@
omap_dwc3@4a020000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss";
+ clocks = <&dpll_core_h13x2_ck>, <&usb_otg_ss_refclk960m>;
+ clock-names = "fck", "refclk960m";
reg = <0x4a020000 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 3c70f5c..ef50f7c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -235,7 +235,6 @@ static struct omap_hwmod omap54xx_counter_32k_hwmod = {
.class = &omap54xx_counter_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
@@ -289,7 +288,6 @@ static struct omap_hwmod omap54xx_dma_system_hwmod = {
.class = &omap54xx_dma_hwmod_class,
.clkdm_name = "dma_clkdm",
.mpu_irqs = omap54xx_dma_system_irqs,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
@@ -324,7 +322,6 @@ static struct omap_hwmod omap54xx_dmic_hwmod = {
.name = "dmic",
.class = &omap54xx_dmic_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "dmic_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
@@ -354,7 +351,6 @@ static struct omap_hwmod omap54xx_emif1_hwmod = {
.class = &omap54xx_emif_hwmod_class,
.clkdm_name = "emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .main_clk = "dpll_core_h11x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
@@ -370,7 +366,6 @@ static struct omap_hwmod omap54xx_emif2_hwmod = {
.class = &omap54xx_emif_hwmod_class,
.clkdm_name = "emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .main_clk = "dpll_core_h11x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
@@ -410,15 +405,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio1_hwmod = {
.name = "gpio1",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
- .main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
@@ -426,22 +417,16 @@ static struct omap_hwmod omap54xx_gpio1_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio2_hwmod = {
.name = "gpio2",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
@@ -449,22 +434,16 @@ static struct omap_hwmod omap54xx_gpio2_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio3_hwmod = {
.name = "gpio3",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
@@ -472,22 +451,16 @@ static struct omap_hwmod omap54xx_gpio3_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio4_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio4_hwmod = {
.name = "gpio4",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
@@ -495,22 +468,16 @@ static struct omap_hwmod omap54xx_gpio4_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio5 */
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio5_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio5_hwmod = {
.name = "gpio5",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
@@ -518,22 +485,16 @@ static struct omap_hwmod omap54xx_gpio5_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio5_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio6 */
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio6_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio6_hwmod = {
.name = "gpio6",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
@@ -541,22 +502,16 @@ static struct omap_hwmod omap54xx_gpio6_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio6_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio7 */
-static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio7_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio7_hwmod = {
.name = "gpio7",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
@@ -564,22 +519,16 @@ static struct omap_hwmod omap54xx_gpio7_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio7_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio8 */
-static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio8_dbclk" },
-};
static struct omap_hwmod omap54xx_gpio8_hwmod = {
.name = "gpio8",
.class = &omap54xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
@@ -587,8 +536,6 @@ static struct omap_hwmod omap54xx_gpio8_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio8_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
.dev_attr = &gpio_dev_attr,
};
@@ -627,7 +574,6 @@ static struct omap_hwmod omap54xx_i2c1_hwmod = {
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
@@ -644,7 +590,6 @@ static struct omap_hwmod omap54xx_i2c2_hwmod = {
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
@@ -661,7 +606,6 @@ static struct omap_hwmod omap54xx_i2c3_hwmod = {
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
@@ -678,7 +622,6 @@ static struct omap_hwmod omap54xx_i2c4_hwmod = {
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
@@ -695,7 +638,6 @@ static struct omap_hwmod omap54xx_i2c5_hwmod = {
.class = &omap54xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
@@ -730,7 +672,6 @@ static struct omap_hwmod omap54xx_kbd_hwmod = {
.name = "kbd",
.class = &omap54xx_kbd_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
@@ -760,16 +701,11 @@ static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
};
/* mcbsp1 */
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
-};
static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp1_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
@@ -777,21 +713,14 @@ static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mcbsp1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
};
/* mcbsp2 */
-static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
-};
static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp2_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
@@ -799,21 +728,14 @@ static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mcbsp2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
};
/* mcbsp3 */
-static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
-};
static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp3_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
@@ -821,8 +743,6 @@ static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mcbsp3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
};
/*
@@ -864,7 +784,6 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = {
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK,
- .main_clk = "pad_clks_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
@@ -906,7 +825,6 @@ static struct omap_hwmod omap54xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
@@ -927,7 +845,6 @@ static struct omap_hwmod omap54xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
@@ -948,7 +865,6 @@ static struct omap_hwmod omap54xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
@@ -969,7 +885,6 @@ static struct omap_hwmod omap54xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
@@ -1003,9 +918,6 @@ static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
};
/* mmc1 */
-static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
- { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
-};
/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
@@ -1016,7 +928,6 @@ static struct omap_hwmod omap54xx_mmc1_hwmod = {
.name = "mmc1",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l3init_clkdm",
- .main_clk = "mmc1_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
@@ -1024,8 +935,6 @@ static struct omap_hwmod omap54xx_mmc1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
.dev_attr = &mmc1_dev_attr,
};
@@ -1034,7 +943,6 @@ static struct omap_hwmod omap54xx_mmc2_hwmod = {
.name = "mmc2",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l3init_clkdm",
- .main_clk = "mmc2_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
@@ -1049,7 +957,6 @@ static struct omap_hwmod omap54xx_mmc3_hwmod = {
.name = "mmc3",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
@@ -1064,7 +971,6 @@ static struct omap_hwmod omap54xx_mmc4_hwmod = {
.name = "mmc4",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
@@ -1079,7 +985,6 @@ static struct omap_hwmod omap54xx_mmc5_hwmod = {
.name = "mmc5",
.class = &omap54xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
@@ -1155,7 +1060,6 @@ static struct omap_hwmod omap54xx_timer1_hwmod = {
.name = "timer1",
.class = &omap54xx_timer_1ms_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
- .main_clk = "timer1_gfclk_mux",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.prcm = {
.omap4 = {
@@ -1171,7 +1075,6 @@ static struct omap_hwmod omap54xx_timer2_hwmod = {
.name = "timer2",
.class = &omap54xx_timer_1ms_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer2_gfclk_mux",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.prcm = {
.omap4 = {
@@ -1187,7 +1090,6 @@ static struct omap_hwmod omap54xx_timer3_hwmod = {
.name = "timer3",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer3_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
@@ -1202,7 +1104,6 @@ static struct omap_hwmod omap54xx_timer4_hwmod = {
.name = "timer4",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer4_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
@@ -1217,7 +1118,6 @@ static struct omap_hwmod omap54xx_timer5_hwmod = {
.name = "timer5",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer5_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
@@ -1232,7 +1132,6 @@ static struct omap_hwmod omap54xx_timer6_hwmod = {
.name = "timer6",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer6_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
@@ -1247,7 +1146,6 @@ static struct omap_hwmod omap54xx_timer7_hwmod = {
.name = "timer7",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer7_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
@@ -1262,7 +1160,6 @@ static struct omap_hwmod omap54xx_timer8_hwmod = {
.name = "timer8",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .main_clk = "timer8_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
@@ -1277,7 +1174,6 @@ static struct omap_hwmod omap54xx_timer9_hwmod = {
.name = "timer9",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer9_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
@@ -1292,7 +1188,6 @@ static struct omap_hwmod omap54xx_timer10_hwmod = {
.name = "timer10",
.class = &omap54xx_timer_1ms_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer10_gfclk_mux",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.prcm = {
.omap4 = {
@@ -1308,7 +1203,6 @@ static struct omap_hwmod omap54xx_timer11_hwmod = {
.name = "timer11",
.class = &omap54xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer11_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
@@ -1345,7 +1239,6 @@ static struct omap_hwmod omap54xx_uart1_hwmod = {
.name = "uart1",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
@@ -1360,7 +1253,6 @@ static struct omap_hwmod omap54xx_uart2_hwmod = {
.name = "uart2",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
@@ -1376,7 +1268,6 @@ static struct omap_hwmod omap54xx_uart3_hwmod = {
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = DEBUG_OMAP4UART3_FLAGS,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
@@ -1392,7 +1283,6 @@ static struct omap_hwmod omap54xx_uart4_hwmod = {
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = DEBUG_OMAP4UART4_FLAGS,
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
@@ -1407,7 +1297,6 @@ static struct omap_hwmod omap54xx_uart5_hwmod = {
.name = "uart5",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
@@ -1422,7 +1311,6 @@ static struct omap_hwmod omap54xx_uart6_hwmod = {
.name = "uart6",
.class = &omap54xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
@@ -1454,16 +1342,12 @@ static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
};
/* usb_otg_ss */
-static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
- { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
-};
static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
.name = "usb_otg_ss",
.class = &omap54xx_usb_otg_ss_hwmod_class,
.clkdm_name = "l3init_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "dpll_core_h13x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
@@ -1471,8 +1355,6 @@ static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = usb_otg_ss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
};
/*
@@ -1503,7 +1385,6 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap54xx_wd_timer_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 42/45] ARM: dts: am335x: Add main and optional clock data into DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (40 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 41/45] ARM: dts: omap5: Add main and optional clock data into DT Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 43/45] ARM: dts: DRA7: link in clock DT data Tero Kristo
` (2 subsequent siblings)
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
With support to parse clock data from DT, move all main and optional
clock information from hwmod to DT.
We still retain clocks in hwmod for devices which do not have a DT node.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 88 ++++++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 64 --------------------
2 files changed, 88 insertions(+), 64 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 4701e3c..509eab3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -87,6 +87,8 @@
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
+ clocks = <&l3_gclk>;
+ clock-names = "fck";
intc: interrupt-controller@48200000 {
compatible = "ti,omap2-intc";
@@ -99,6 +101,8 @@
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
+ clocks = <&dpll_core_m4_div2_ck>, <&gpio0_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -110,6 +114,8 @@
gpio1: gpio@4804c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
+ clocks = <&l4ls_gclk>, <&gpio1_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -121,6 +127,8 @@
gpio2: gpio@481ac000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
+ clocks = <&l4ls_gclk>, <&gpio2_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -132,6 +140,8 @@
gpio3: gpio@481ae000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
+ clocks = <&l4ls_gclk>, <&gpio3_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -143,6 +153,8 @@
uart0: serial@44e09000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart1";
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
reg = <0x44e09000 0x2000>;
interrupts = <72>;
@@ -152,6 +164,8 @@
uart1: serial@48022000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart2";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
reg = <0x48022000 0x2000>;
interrupts = <73>;
@@ -161,6 +175,8 @@
uart2: serial@48024000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart3";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
reg = <0x48024000 0x2000>;
interrupts = <74>;
@@ -170,6 +186,8 @@
uart3: serial@481a6000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart4";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
reg = <0x481a6000 0x2000>;
interrupts = <44>;
@@ -179,6 +197,8 @@
uart4: serial@481a8000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart5";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
reg = <0x481a8000 0x2000>;
interrupts = <45>;
@@ -188,6 +208,8 @@
uart5: serial@481aa000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart6";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
clock-frequency = <48000000>;
reg = <0x481aa000 0x2000>;
interrupts = <46>;
@@ -199,6 +221,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ clock-names = "fck";
reg = <0x44e0b000 0x1000>;
interrupts = <70>;
status = "disabled";
@@ -209,6 +233,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
reg = <0x4802a000 0x1000>;
interrupts = <71>;
status = "disabled";
@@ -219,6 +245,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
reg = <0x4819c000 0x1000>;
interrupts = <30>;
status = "disabled";
@@ -227,6 +255,8 @@
wdt2: wdt@44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
+ clocks = <&wdt1_fck>;
+ clock-names = "fck";
reg = <0x44e35000 0x1000>;
interrupts = <91>;
};
@@ -234,6 +264,8 @@
dcan0: d_can@481cc000 {
compatible = "bosch,d_can";
ti,hwmods = "d_can0";
+ clocks = <&dcan0_fck>;
+ clock-names = "fck";
reg = <0x481cc000 0x2000
0x44e10644 0x4>;
interrupts = <52>;
@@ -243,6 +275,8 @@
dcan1: d_can@481d0000 {
compatible = "bosch,d_can";
ti,hwmods = "d_can1";
+ clocks = <&dcan1_fck>;
+ clock-names = "fck";
reg = <0x481d0000 0x2000
0x44e10644 0x4>;
interrupts = <55>;
@@ -254,6 +288,8 @@
reg = <0x44e31000 0x400>;
interrupts = <67>;
ti,hwmods = "timer1";
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
ti,timer-alwon;
};
@@ -262,6 +298,8 @@
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@48042000 {
@@ -269,6 +307,8 @@
reg = <0x48042000 0x400>;
interrupts = <69>;
ti,hwmods = "timer3";
+ clocks = <&timer3_fck>;
+ clock-names = "fck";
};
timer4: timer@48044000 {
@@ -276,6 +316,8 @@
reg = <0x48044000 0x400>;
interrupts = <92>;
ti,hwmods = "timer4";
+ clocks = <&timer4_fck>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -284,6 +326,8 @@
reg = <0x48046000 0x400>;
interrupts = <93>;
ti,hwmods = "timer5";
+ clocks = <&timer5_fck>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -292,6 +336,8 @@
reg = <0x48048000 0x400>;
interrupts = <94>;
ti,hwmods = "timer6";
+ clocks = <&timer6_fck>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -300,6 +346,8 @@
reg = <0x4804a000 0x400>;
interrupts = <95>;
ti,hwmods = "timer7";
+ clocks = <&timer7_fck>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -309,6 +357,8 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
+ clocks = <&clk_32768_ck>;
+ clock-names = "fck";
};
spi0: spi@48030000 {
@@ -319,6 +369,8 @@
interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
status = "disabled";
};
@@ -330,6 +382,8 @@
interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
status = "disabled";
};
@@ -348,12 +402,16 @@
port1-mode = <3>;
power = <250>;
ti,hwmods = "usb_otg_hs";
+ clocks = <&usbotg_fck>;
+ clock-names = "fck";
};
epwmss0: epwmss@48300000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
@@ -366,6 +424,8 @@
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
ti,hwmods = "ecap0";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -374,6 +434,8 @@
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
ti,hwmods = "ehrpwm0";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
status = "disabled";
};
};
@@ -382,6 +444,8 @@
compatible = "ti,am33xx-pwmss";
reg = <0x48302000 0x10>;
ti,hwmods = "epwmss1";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
@@ -394,6 +458,8 @@
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
ti,hwmods = "ecap1";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -402,6 +468,8 @@
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
ti,hwmods = "ehrpwm1";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
status = "disabled";
};
};
@@ -410,6 +478,8 @@
compatible = "ti,am33xx-pwmss";
reg = <0x48304000 0x10>;
ti,hwmods = "epwmss2";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
@@ -422,6 +492,8 @@
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
ti,hwmods = "ecap2";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -430,6 +502,8 @@
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
ti,hwmods = "ehrpwm2";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
status = "disabled";
};
};
@@ -437,6 +511,8 @@
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
+ clocks = <&cpsw_125mhz_gclk>;
+ clock-names = "fck";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
@@ -466,6 +542,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
+ clocks = <&cpsw_125mhz_gclk>;
+ clock-names = "fck";
bus_freq = <1000000>;
reg = <0x4a101000 0x100>;
};
@@ -485,6 +563,8 @@
compatible = "ti,am3352-ocmcram";
reg = <0x40300000 0x10000>;
ti,hwmods = "ocmcram";
+ clocks = <&l3_gclk>;
+ clock-names = "fck";
};
wkup_m3: wkup_m3@44d00000 {
@@ -492,6 +572,8 @@
reg = <0x44d00000 0x4000 /* M3 UMEM */
0x44d80000 0x2000>; /* M3 DMEM */
ti,hwmods = "wkup_m3";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-names = "fck";
};
elm: elm@48080000 {
@@ -499,6 +581,8 @@
reg = <0x48080000 0x2000>;
interrupts = <4>;
ti,hwmods = "elm";
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -508,6 +592,8 @@
interrupt-parent = <&intc>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
+ clocks = <&adc_tsc_fck>;
+ clock-names = "fck";
status = "disabled";
tsc {
@@ -522,6 +608,8 @@
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
+ clocks = <&l3s_gclk>;
+ clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <100>;
gpmc,num-cs = <7>;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index eb2f3b9..46de57b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -75,7 +75,6 @@ static struct omap_hwmod am33xx_l3_main_hwmod = {
.class = &am33xx_l3_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
@@ -199,7 +198,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
- .main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
@@ -306,7 +304,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
.name = "adc_tsc",
.class = &am33xx_adc_tsc_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .main_clk = "adc_tsc_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
@@ -473,7 +470,6 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
@@ -561,7 +557,6 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.class = &am33xx_cpgmac0_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- .main_clk = "cpsw_125mhz_gclk",
.mpu_rt_idx = 1,
.prcm = {
.omap4 = {
@@ -582,7 +577,6 @@ static struct omap_hwmod am33xx_mdio_hwmod = {
.name = "davinci_mdio",
.class = &am33xx_mdio_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
- .main_clk = "cpsw_125mhz_gclk",
};
/*
@@ -597,7 +591,6 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
.name = "d_can0",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "dcan0_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
@@ -611,7 +604,6 @@ static struct omap_hwmod am33xx_dcan1_hwmod = {
.name = "d_can1",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "dcan1_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
@@ -641,7 +633,6 @@ static struct omap_hwmod am33xx_elm_hwmod = {
.name = "elm",
.class = &am33xx_elm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
@@ -683,7 +674,6 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
.name = "epwmss0",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
@@ -697,7 +687,6 @@ static struct omap_hwmod am33xx_ecap0_hwmod = {
.name = "ecap0",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
};
/* eqep0 */
@@ -713,7 +702,6 @@ static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
.name = "ehrpwm0",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
};
/* epwmss1 */
@@ -721,7 +709,6 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
.name = "epwmss1",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
@@ -735,7 +722,6 @@ static struct omap_hwmod am33xx_ecap1_hwmod = {
.name = "ecap1",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
};
/* eqep1 */
@@ -751,7 +737,6 @@ static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
};
/* epwmss2 */
@@ -759,7 +744,6 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
.name = "epwmss2",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
@@ -773,7 +757,6 @@ static struct omap_hwmod am33xx_ecap2_hwmod = {
.name = "ecap2",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
};
/* eqep2 */
@@ -789,7 +772,6 @@ static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
};
/*
@@ -819,90 +801,66 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio0 */
-static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio0_dbclk" },
-};
static struct omap_hwmod am33xx_gpio0_hwmod = {
.name = "gpio1",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = gpio0_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
static struct omap_hwmod am33xx_gpio1_hwmod = {
.name = "gpio2",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
static struct omap_hwmod am33xx_gpio2_hwmod = {
.name = "gpio3",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
static struct omap_hwmod am33xx_gpio3_hwmod = {
.name = "gpio4",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.dev_attr = &gpio_dev_attr,
};
@@ -927,7 +885,6 @@ static struct omap_hwmod am33xx_gpmc_hwmod = {
.class = &am33xx_gpmc_hwmod_class,
.clkdm_name = "l3s_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .main_clk = "l3s_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
@@ -965,7 +922,6 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
.class = &i2c_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
@@ -981,7 +937,6 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
.class = &i2c_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
@@ -997,7 +952,6 @@ static struct omap_hwmod am33xx_i2c3_hwmod = {
.class = &i2c_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
@@ -1207,7 +1161,6 @@ static struct omap_hwmod am33xx_rtc_hwmod = {
.name = "rtc",
.class = &am33xx_rtc_hwmod_class,
.clkdm_name = "l4_rtc_clkdm",
- .main_clk = "clk_32768_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
@@ -1242,7 +1195,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
.name = "spi0",
.class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
@@ -1257,7 +1209,6 @@ static struct omap_hwmod am33xx_spi1_hwmod = {
.name = "spi1",
.class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
@@ -1326,7 +1277,6 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
.name = "timer1",
.class = &am33xx_timer1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .main_clk = "timer1_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
@@ -1339,7 +1289,6 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
.name = "timer2",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "timer2_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
@@ -1352,7 +1301,6 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
.name = "timer3",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "timer3_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
@@ -1365,7 +1313,6 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
.name = "timer4",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "timer4_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
@@ -1378,7 +1325,6 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
.name = "timer5",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "timer5_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
@@ -1391,7 +1337,6 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
.name = "timer6",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "timer6_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
@@ -1404,7 +1349,6 @@ static struct omap_hwmod am33xx_timer7_hwmod = {
.name = "timer7",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .main_clk = "timer7_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
@@ -1514,7 +1458,6 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
.class = &uart_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
@@ -1528,7 +1471,6 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
@@ -1543,7 +1485,6 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
@@ -1557,7 +1498,6 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
@@ -1571,7 +1511,6 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
@@ -1585,7 +1524,6 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
@@ -1621,7 +1559,6 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
.class = &am33xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wdt1_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
@@ -1653,7 +1590,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
.class = &am33xx_usbotg_class,
.clkdm_name = "l3s_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "usbotg_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 43/45] ARM: dts: DRA7: link in clock DT data
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (41 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 42/45] ARM: dts: am335x: " Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 44/45] ARM: OMAP: DRA7: Enable clock init Tero Kristo
2013-08-29 13:16 ` [PATCHv6 45/45] ARM: dts: dra7: Add main and optional clock data into DT Tero Kristo
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
Clock tree DT data is now included from base dra7.dtsi file.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c01ef76..c98997b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -572,4 +572,18 @@
status = "disabled";
};
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ /include/ "dra7xx-clocks.dtsi"
+ };
+
+ clockdomains {
+ coreaon_clkdm: coreaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 44/45] ARM: OMAP: DRA7: Enable clock init
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (42 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 43/45] ARM: dts: DRA7: link in clock DT data Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
2013-08-29 13:16 ` [PATCHv6 45/45] ARM: dts: dra7: Add main and optional clock data into DT Tero Kristo
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
Initializes clock data from device tree.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/io.c | 1 +
include/linux/clk/ti.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index fd4bb71..315a148 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -682,6 +682,7 @@ void __init dra7xx_init_early(void)
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_clk_init = dra7xx_clk_init;
}
#endif
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 90cb61b..0fcd2e7 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -226,6 +226,7 @@ static inline void of_omap_clk_deny_autoidle_all(void) { }
#endif
int omap5xxx_clk_init(void);
+int dra7xx_clk_init(void);
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCHv6 45/45] ARM: dts: dra7: Add main and optional clock data into DT
2013-08-29 13:15 [PATCHv6 00/45] OMAP CCF DT conversion Tero Kristo
` (43 preceding siblings ...)
2013-08-29 13:16 ` [PATCHv6 44/45] ARM: OMAP: DRA7: Enable clock init Tero Kristo
@ 2013-08-29 13:16 ` Tero Kristo
44 siblings, 0 replies; 48+ messages in thread
From: Tero Kristo @ 2013-08-29 13:16 UTC (permalink / raw)
To: linux-omap, paul, tony, rnayak, nm, mturquette
Cc: linux-arm-kernel, devicetree
With support to parse clock data from DT, move all main and optional
clock information from hwmod to DT.
We still retain clocks in hwmod for devices which do not have a DT node.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 82 +++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 101 -----------------------------
2 files changed, 82 insertions(+), 101 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c98997b..d9d910f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -97,6 +97,8 @@
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
ti,hwmods = "counter_32k";
+ clocks = <&wkupaon_iclk_mux>;
+ clock-names = "fck";
};
dra7_pmx_core: pinmux@4a003400 {
@@ -118,6 +120,8 @@
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
};
gpio1: gpio@4ae10000 {
@@ -125,6 +129,8 @@
reg = <0x4ae10000 0x200>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio1";
+ clocks = <&wkupaon_iclk_mux>, <&gpio1_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -136,6 +142,8 @@
reg = <0x48055000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio2";
+ clocks = <&l3_iclk_div>, <&gpio2_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -147,6 +155,8 @@
reg = <0x48057000 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio3";
+ clocks = <&l3_iclk_div>, <&gpio3_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -158,6 +168,8 @@
reg = <0x48059000 0x200>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio4";
+ clocks = <&l3_iclk_div>, <&gpio4_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -169,6 +181,8 @@
reg = <0x4805b000 0x200>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio5";
+ clocks = <&l3_iclk_div>, <&gpio5_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -180,6 +194,8 @@
reg = <0x4805d000 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio6";
+ clocks = <&l3_iclk_div>, <&gpio6_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -191,6 +207,8 @@
reg = <0x48051000 0x200>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio7";
+ clocks = <&l3_iclk_div>, <&gpio7_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -202,6 +220,8 @@
reg = <0x48053000 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio8";
+ clocks = <&l3_iclk_div>, <&gpio8_dbclk>;
+ clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -213,6 +233,8 @@
reg = <0x4806a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
+ clocks = <&uart1_gfclk_mux>;
+ clock-names = "fck";
clock-frequency = <48000000>;
status = "disabled";
};
@@ -222,6 +244,8 @@
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
+ clocks = <&uart2_gfclk_mux>;
+ clock-names = "fck";
clock-frequency = <48000000>;
status = "disabled";
};
@@ -231,6 +255,8 @@
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
+ clocks = <&uart3_gfclk_mux>;
+ clock-names = "fck";
clock-frequency = <48000000>;
status = "disabled";
};
@@ -240,6 +266,8 @@
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
+ clocks = <&uart4_gfclk_mux>;
+ clock-names = "fck";
clock-frequency = <48000000>;
status = "disabled";
};
@@ -249,6 +277,8 @@
reg = <0x48066000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
+ clocks = <&uart5_gfclk_mux>;
+ clock-names = "fck";
clock-frequency = <48000000>;
status = "disabled";
};
@@ -258,6 +288,8 @@
reg = <0x48068000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
+ clocks = <&uart6_gfclk_mux>;
+ clock-names = "fck";
clock-frequency = <48000000>;
status = "disabled";
};
@@ -299,6 +331,8 @@
reg = <0x4ae18000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
+ clocks = <&timer1_gfclk_mux>;
+ clock-names = "fck";
ti,timer-alwon;
};
@@ -307,6 +341,8 @@
reg = <0x48032000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
+ clocks = <&timer2_gfclk_mux>;
+ clock-names = "fck";
};
timer3: timer@48034000 {
@@ -314,6 +350,8 @@
reg = <0x48034000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
+ clocks = <&timer3_gfclk_mux>;
+ clock-names = "fck";
};
timer4: timer@48036000 {
@@ -321,6 +359,8 @@
reg = <0x48036000 0x80>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer4";
+ clocks = <&timer4_gfclk_mux>;
+ clock-names = "fck";
};
timer5: timer@48820000 {
@@ -328,6 +368,8 @@
reg = <0x48820000 0x80>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer5";
+ clocks = <&timer5_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -336,6 +378,8 @@
reg = <0x48822000 0x80>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer6";
+ clocks = <&timer6_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
ti,timer-pwm;
};
@@ -345,6 +389,8 @@
reg = <0x48824000 0x80>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer7";
+ clocks = <&timer7_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
};
@@ -353,6 +399,8 @@
reg = <0x48826000 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
+ clocks = <&timer8_gfclk_mux>;
+ clock-names = "fck";
ti,timer-dsp;
ti,timer-pwm;
};
@@ -362,6 +410,8 @@
reg = <0x4803e000 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
+ clocks = <&timer9_gfclk_mux>;
+ clock-names = "fck";
};
timer10: timer@48086000 {
@@ -369,6 +419,8 @@
reg = <0x48086000 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
+ clocks = <&timer10_gfclk_mux>;
+ clock-names = "fck";
};
timer11: timer@48088000 {
@@ -376,6 +428,8 @@
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
+ clocks = <&timer11_gfclk_mux>;
+ clock-names = "fck";
ti,timer-pwm;
};
@@ -412,6 +466,8 @@
reg = <0x4ae14000 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
+ clocks = <&sys_32k_ck>;
+ clock-names = "fck";
};
i2c1: i2c@48070000 {
@@ -421,6 +477,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -431,6 +489,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -441,6 +501,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -451,6 +513,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -461,6 +525,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c5";
+ clocks = <&func_96m_fclk>;
+ clock-names = "fck";
status = "disabled";
};
@@ -469,6 +535,8 @@
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
+ clocks = <&mmc1_fclk_div>, <&mmc1_clk32k>;
+ clock-names = "fck", "clk32k";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma 61>, <&sdma 62>;
@@ -481,6 +549,8 @@
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
+ clocks = <&mmc2_fclk_div>, <&mmc2_clk32k>;
+ clock-names = "fck", "clk32k";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
@@ -492,6 +562,8 @@
reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
+ clocks = <&mmc3_gfclk_div>, <&mmc3_clk32k>;
+ clock-names = "fck", "clk32k";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
@@ -503,6 +575,8 @@
reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
+ clocks = <&mmc4_gfclk_div>, <&mmc4_clk32k>;
+ clock-names = "fck", "clk32k";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
dma-names = "tx", "rx";
@@ -516,6 +590,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
@@ -537,6 +613,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
@@ -553,6 +631,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>, <&sdma 16>;
dma-names = "tx0", "rx0";
@@ -566,6 +646,8 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
+ clocks = <&func_48m_fclk>;
+ clock-names = "fck";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index db32d53..2b20140 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -242,7 +242,6 @@ static struct omap_hwmod dra7xx_counter_32k_hwmod = {
.class = &dra7xx_counter_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
@@ -356,7 +355,6 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
.class = &dra7xx_dma_hwmod_class,
.clkdm_name = "dma_clkdm",
.mpu_irqs = dra7xx_dma_system_irqs,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
@@ -568,15 +566,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio1_hwmod = {
.name = "gpio1",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
- .main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
@@ -584,22 +578,16 @@ static struct omap_hwmod dra7xx_gpio1_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio2_hwmod = {
.name = "gpio2",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
@@ -607,22 +595,16 @@ static struct omap_hwmod dra7xx_gpio2_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio3_hwmod = {
.name = "gpio3",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
@@ -630,22 +612,16 @@ static struct omap_hwmod dra7xx_gpio3_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio4_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio4_hwmod = {
.name = "gpio4",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
@@ -653,22 +629,16 @@ static struct omap_hwmod dra7xx_gpio4_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio5 */
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio5_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio5_hwmod = {
.name = "gpio5",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
@@ -676,22 +646,16 @@ static struct omap_hwmod dra7xx_gpio5_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio5_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio6 */
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio6_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio6_hwmod = {
.name = "gpio6",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
@@ -699,22 +663,16 @@ static struct omap_hwmod dra7xx_gpio6_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio6_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio7 */
-static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio7_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio7_hwmod = {
.name = "gpio7",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
@@ -722,22 +680,16 @@ static struct omap_hwmod dra7xx_gpio7_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio7_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
.dev_attr = &gpio_dev_attr,
};
/* gpio8 */
-static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio8_dbclk" },
-};
static struct omap_hwmod dra7xx_gpio8_hwmod = {
.name = "gpio8",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
@@ -745,8 +697,6 @@ static struct omap_hwmod dra7xx_gpio8_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = gpio8_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
.dev_attr = &gpio_dev_attr,
};
@@ -859,7 +809,6 @@ static struct omap_hwmod dra7xx_i2c1_hwmod = {
.class = &dra7xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
@@ -876,7 +825,6 @@ static struct omap_hwmod dra7xx_i2c2_hwmod = {
.class = &dra7xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
@@ -893,7 +841,6 @@ static struct omap_hwmod dra7xx_i2c3_hwmod = {
.class = &dra7xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
@@ -910,7 +857,6 @@ static struct omap_hwmod dra7xx_i2c4_hwmod = {
.class = &dra7xx_i2c_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
@@ -927,7 +873,6 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = {
.class = &dra7xx_i2c_hwmod_class,
.clkdm_name = "ipu_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
@@ -969,7 +914,6 @@ static struct omap_hwmod dra7xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
@@ -990,7 +934,6 @@ static struct omap_hwmod dra7xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
@@ -1011,7 +954,6 @@ static struct omap_hwmod dra7xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
@@ -1032,7 +974,6 @@ static struct omap_hwmod dra7xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
@@ -1066,9 +1007,6 @@ static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
};
/* mmc1 */
-static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
- { .role = "clk32k", .clk = "mmc1_clk32k" },
-};
/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
@@ -1079,7 +1017,6 @@ static struct omap_hwmod dra7xx_mmc1_hwmod = {
.name = "mmc1",
.class = &dra7xx_mmc_hwmod_class,
.clkdm_name = "l3init_clkdm",
- .main_clk = "mmc1_fclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
@@ -1087,21 +1024,15 @@ static struct omap_hwmod dra7xx_mmc1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
.dev_attr = &mmc1_dev_attr,
};
/* mmc2 */
-static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
- { .role = "clk32k", .clk = "mmc2_clk32k" },
-};
static struct omap_hwmod dra7xx_mmc2_hwmod = {
.name = "mmc2",
.class = &dra7xx_mmc_hwmod_class,
.clkdm_name = "l3init_clkdm",
- .main_clk = "mmc2_fclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
@@ -1109,20 +1040,14 @@ static struct omap_hwmod dra7xx_mmc2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
};
/* mmc3 */
-static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
- { .role = "clk32k", .clk = "mmc3_clk32k" },
-};
static struct omap_hwmod dra7xx_mmc3_hwmod = {
.name = "mmc3",
.class = &dra7xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "mmc3_gfclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
@@ -1130,20 +1055,14 @@ static struct omap_hwmod dra7xx_mmc3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mmc3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
};
/* mmc4 */
-static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
- { .role = "clk32k", .clk = "mmc4_clk32k" },
-};
static struct omap_hwmod dra7xx_mmc4_hwmod = {
.name = "mmc4",
.class = &dra7xx_mmc_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "mmc4_gfclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
@@ -1151,8 +1070,6 @@ static struct omap_hwmod dra7xx_mmc4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = mmc4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
};
/*
@@ -1449,7 +1366,6 @@ static struct omap_hwmod dra7xx_timer1_hwmod = {
.name = "timer1",
.class = &dra7xx_timer_1ms_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
- .main_clk = "timer1_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
@@ -1464,7 +1380,6 @@ static struct omap_hwmod dra7xx_timer2_hwmod = {
.name = "timer2",
.class = &dra7xx_timer_1ms_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer2_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
@@ -1479,7 +1394,6 @@ static struct omap_hwmod dra7xx_timer3_hwmod = {
.name = "timer3",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer3_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
@@ -1494,7 +1408,6 @@ static struct omap_hwmod dra7xx_timer4_hwmod = {
.name = "timer4",
.class = &dra7xx_timer_secure_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer4_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
@@ -1509,7 +1422,6 @@ static struct omap_hwmod dra7xx_timer5_hwmod = {
.name = "timer5",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "ipu_clkdm",
- .main_clk = "timer5_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
@@ -1524,7 +1436,6 @@ static struct omap_hwmod dra7xx_timer6_hwmod = {
.name = "timer6",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "ipu_clkdm",
- .main_clk = "timer6_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
@@ -1539,7 +1450,6 @@ static struct omap_hwmod dra7xx_timer7_hwmod = {
.name = "timer7",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "ipu_clkdm",
- .main_clk = "timer7_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
@@ -1554,7 +1464,6 @@ static struct omap_hwmod dra7xx_timer8_hwmod = {
.name = "timer8",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "ipu_clkdm",
- .main_clk = "timer8_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
@@ -1569,7 +1478,6 @@ static struct omap_hwmod dra7xx_timer9_hwmod = {
.name = "timer9",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer9_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
@@ -1584,7 +1492,6 @@ static struct omap_hwmod dra7xx_timer10_hwmod = {
.name = "timer10",
.class = &dra7xx_timer_1ms_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer10_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
@@ -1599,7 +1506,6 @@ static struct omap_hwmod dra7xx_timer11_hwmod = {
.name = "timer11",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "timer11_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
@@ -1636,7 +1542,6 @@ static struct omap_hwmod dra7xx_uart1_hwmod = {
.name = "uart1",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "uart1_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
@@ -1652,7 +1557,6 @@ static struct omap_hwmod dra7xx_uart2_hwmod = {
.name = "uart2",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "uart2_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
@@ -1668,7 +1572,6 @@ static struct omap_hwmod dra7xx_uart3_hwmod = {
.name = "uart3",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "uart3_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
@@ -1684,7 +1587,6 @@ static struct omap_hwmod dra7xx_uart4_hwmod = {
.name = "uart4",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "uart4_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
@@ -1700,7 +1602,6 @@ static struct omap_hwmod dra7xx_uart5_hwmod = {
.name = "uart5",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per_clkdm",
- .main_clk = "uart5_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
@@ -1716,7 +1617,6 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
.name = "uart6",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "ipu_clkdm",
- .main_clk = "uart6_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
@@ -1873,7 +1773,6 @@ static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &dra7xx_wd_timer_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 48+ messages in thread