Re: [PATCH 1/5] clk: mvebu: Add core-divider clock

[Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>]

Hi Ezequiel

> +static int clk_corediv_enable(struct clk_hw *hwclk)
> +{
> +	struct clk_corediv *corediv = to_corediv_clk(hwclk);
> +	struct clk_corediv_desc *desc = &corediv->desc;
> +	u32 reg;
> +
> +	reg = readl(corediv->reg);
> +	reg |= (BIT(desc->fieldbit) << CORE_CLOCK_DIVIDER_ENABLE_OFFSET);
> +	writel(reg, corediv->reg);
> +	return 0;
> +}

Shouldn't there be spinlocks around these register accesses? At least
the core gate clk driver has a spinlock.

> +static long clk_corediv_round_rate(struct clk_hw *hwclk, unsigned long rate,
> +	     				          unsigned long *parent_rate)
> +{
> +	/* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
> +	u32 div;
> +
> +	div = *parent_rate / rate;
> +	if (div <= 4)
> +	   div = 4;
> +	   else if (div <= 5)
> +	   	div = 5;
> +		else if (div <= 6)
> +		     div = 6;
> +		     else
> +			div = 8;
> +
> +	return *parent_rate / div;
> +}

This looks odd. Is not the following clearer?

	div = *parent_rate / rate;
	if (div < 5)
	   div = 4;
	   else if (div > 6)
		div = 8;

The CodingStyle might require some {} here?

+   /*
+    * Wait for clocks to settle down, and then clear all the
+     * ratios request and the reload request.
+      */
+      udelay(1000);
+      reg &= ~(CORE_CLOCK_DIVIDER_RATIO_MASK | CORE_CLOCK_DIVIDER_RATIO_RELOAD);
+      writel(reg, corediv->reg);
+      udelay(1000);


Documentation/timers/timers-howto.txt says: 

       SLEEPING FOR ~USECS OR SMALL MSECS ( 10us - 20ms):
       		* Use usleep_range

	Andrew
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