From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hiroshi Doyu Subject: Re: [PATCHv3 05/19] ARM: dt: tegra114: iommu: Fix IOMMU register address Date: Thu, 31 Oct 2013 09:14:22 +0100 Message-ID: <20131031.101422.817805151215169789.hdoyu@nvidia.com> References: <1382092020-13170-1-git-send-email-hdoyu@nvidia.com><1382092020-13170-6-git-send-email-hdoyu@nvidia.com><52718315.1040307@wwwdotorg.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <52718315.1040307-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: "swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org" Cc: "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Stephen Warren , "rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org" , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" List-Id: devicetree@vger.kernel.org Stephen Warren wrote @ Wed, 30 Oct 2013 23:07:17 +0100: > On 10/18/2013 04:26 AM, Hiroshi Doyu wrote: > > Fix IOMMU register address. > > That's quite unfortunate. Why do we always have trouble getting the > IOMMU register address correct in DT; I think we had a similar issue > with the Tegra30 DT. FYI: It was the same T114, which means, this one. We just haven't had a chance to get this series in yet. > Anyway, I guess I should take this for 3.13 and stable since it's a bugfix. Thanks. It helps.