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From: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
To: Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org>
Cc: olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org,
	tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	linux-scsi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org,
	Tuan Phan <tphan-qTEPVZfXA3Y@public.gmane.org>,
	Suman Tripathi <stripathi-qTEPVZfXA3Y@public.gmane.org>
Subject: Re: [PATCH 1/3] Documentation: Add APM X-Gene SoC 6.0Gbps SATA PHY driver binding documentation
Date: Fri, 15 Nov 2013 13:35:09 +0100	[thread overview]
Message-ID: <201311151335.09577.arnd@arndb.de> (raw)
In-Reply-To: <1384457519-21335-2-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>

On Thursday 14 November 2013, Loc Ho wrote:
> +- id                   : PHY ID (0 = first, 1 = second, 2 = third)
> +- #phy-cells           : Shall be 0

Hmm, it seems like this would make more sense if you have #phy-cells=<1>
and have the PHY ID in user node as the argument.

> +- CTLE0                        : PHY override parameters for channel 0 register REG1
> +                         field CTLE_EQ. First value for Gen1, second value
> +                         for Gen2, and third value for Gen3. Default is 0x2.
> +- CTLE1                        : PHY override parameters for channel 1 register REG1
> +                         field CTLE_EQ. First value for Gen1, second value
> +                         for Gen2, and third value for Gen3. Default is 0x2.
> +- PQ0                  : PHY override parameters for channel 0 register REG125
> +                         field PQ_REG. First value for Gen1, second value
> +                         for Gen2, and third value for Gen3. Default is 0xA.
> +- PQ1                  : PHY override parameters for channel 1 register REG125
> +                         field PQ_REG. First value for Gen1, second value
> +                         for Gen2, and third value for Gen3. Default is 0xA.

As mentioned before, I don't think putting register-level information into the binding
is the right approach here.

	Arnd
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  parent reply	other threads:[~2013-11-15 12:35 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-14 19:31 [PATCH 0/3] ata: Add APM X-Gene SoC 6.0Gbps SATA PHY support Loc Ho
2013-11-14 19:31 ` [PATCH 1/3] Documentation: Add APM X-Gene SoC 6.0Gbps SATA PHY driver binding documentation Loc Ho
2013-11-14 19:31   ` [PATCH 2/3] ata: Add APM X-Gene SoC 6.0Gbps SATA PHY driver Loc Ho
2013-11-14 19:31     ` [PATCH 3/3] arm64: Add APM X-Gene SoC 6.0Gbps SATA PHY DTS entries Loc Ho
2013-11-15 12:46     ` [PATCH 2/3] ata: Add APM X-Gene SoC 6.0Gbps SATA PHY driver Arnd Bergmann
2013-11-15 16:14       ` Loc Ho
     [not found]   ` <1384457519-21335-2-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>
2013-11-15 12:35     ` Arnd Bergmann [this message]
2013-11-15 12:52       ` [PATCH 1/3] Documentation: Add APM X-Gene SoC 6.0Gbps SATA PHY driver binding documentation Arnd Bergmann
2013-11-15 16:22       ` Loc Ho
2013-11-15 19:26         ` Arnd Bergmann
2013-11-15 19:33           ` Loc Ho
2013-11-15 19:54             ` Arnd Bergmann
2013-11-15 20:00               ` Loc Ho
2013-11-15 20:19                 ` Arnd Bergmann
2013-11-15 20:52                   ` Loc Ho
2013-11-15 12:31 ` [PATCH 0/3] ata: Add APM X-Gene SoC 6.0Gbps SATA PHY support Arnd Bergmann

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