[PATCH/RFC] ARM: omap3: Split the pinmux core device

[PATCH/RFC] ARM: omap3: Split the pinmux core device

[Laurent Pinchart]

The omap3_pmx_core pinmux device in the device tree handles the system
controller module (SCM) PADCONFS fonction. Its control registers are
split in two distinct areas, with other SCM registers in-between. Those
other registers can't thus be requested by other drivers as the memory
region gets reserved by the pinmux driver.

Split the omap3_pmx_core device tree node in two for the two memory
regions.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++++++++++-------
 arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
 arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
 arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
 arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
 5 files changed, 95 insertions(+), 36 deletions(-)

While working on the OMAP3 ISP driver I've run into a failure to request a
memory region already requested by the pinctrl-single driver. This patch is an
attempt to fix the problem. An alternative approach would be to support
multiple reg values in the pinctrl-single driver, but that might not be much
cleaner. I'm open to suggestions.

diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 8d7c813..7028e6a 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -103,7 +103,7 @@
 &omap3_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
-			&hsusbb2_pins
+			&hsusb2_pins
 	>;
 
 	uart3_pins: pinmux_uart3_pins {
@@ -113,14 +113,8 @@
 		>;
 	};
 
-	hsusbb2_pins: pinmux_hsusbb2_pins {
+	hsusb2_pins: pinmux_hsusb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
-			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
-			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
-			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
-			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
-			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
 			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
 			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
 			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
@@ -131,6 +125,24 @@
 	};
 };
 
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			0x050 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			0x052 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			0x054 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			0x056 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			0x058 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			0x05a (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <2600000>;
 
@@ -152,6 +164,23 @@
 
 &i2c2 {
 	clock-frequency = <400000>;
+
+	switch@73 {
+		compatible = "nxp,pca9543";
+		reg = <0x73>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
 };
 
 &i2c3 {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9764556..d2c7322 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -85,17 +85,11 @@
 &omap3_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
-			&hsusbb2_pins
+			&hsusb2_pins
 	>;
 
-	hsusbb2_pins: pinmux_hsusbb2_pins {
+	hsusb2_pins: pinmux_hsusb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
-			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
-			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
-			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
-			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
-			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
 			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
 			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
 			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
@@ -113,6 +107,24 @@
 	};
 };
 
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			0x050 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			0x052 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			0x054 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			0x056 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			0x058 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			0x05a (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <2600000>;
 
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index d5cc792..0f77be8 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -63,7 +63,7 @@
 	};
 };
 
-&omap3_pmx_core {
+&omap3_pmx_core2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <
 		&hsusbb1_pins
@@ -71,18 +71,18 @@
 
 	hsusbb1_pins: pinmux_hsusbb1_pins {
 		pinctrl-single,pins = <
-			0x5aa (PIN_OUTPUT | MUX_MODE3)		/* etk_ctl.hsusb1_clk */
-			0x5a8 (PIN_OUTPUT | MUX_MODE3)		/* etk_clk.hsusb1_stp */
-			0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d8.hsusb1_dir */
-			0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d9.hsusb1_nxt */
-			0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d0.hsusb1_data0 */
-			0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d1.hsusb1_data1 */
-			0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d2.hsusb1_data2 */
-			0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d3.hsusb1_data7 */
-			0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d4.hsusb1_data4 */
-			0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d5.hsusb1_data5 */
-			0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d6.hsusb1_data6 */
-			0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d7.hsusb1_data3 */
+			0x03a (PIN_OUTPUT | MUX_MODE3)		/* etk_ctl.hsusb1_clk */
+			0x038 (PIN_OUTPUT | MUX_MODE3)		/* etk_clk.hsusb1_stp */
+			0x04c (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d8.hsusb1_dir */
+			0x04e (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d9.hsusb1_nxt */
+			0x03c (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d0.hsusb1_data0 */
+			0x03e (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d1.hsusb1_data1 */
+			0x040 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d2.hsusb1_data2 */
+			0x042 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d3.hsusb1_data7 */
+			0x044 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d4.hsusb1_data4 */
+			0x046 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d5.hsusb1_data5 */
+			0x048 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d6.hsusb1_data6 */
+			0x04a (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d7.hsusb1_data3 */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index 15eb9fe..a1bec6b 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -82,11 +82,6 @@
 		pinctrl-single,pins = <
 			0x168 (PIN_INPUT | MUX_MODE4)	/* mcbsp1_clkx.gpio_162 WLAN IRQ */
 			0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs1.sdmmc3_cmd */
-			0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
-			0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
-			0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
-			0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
-			0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
 		>;
 	};
 
@@ -125,6 +120,18 @@
 	};
 };
 
+&omap3_pmx_core2 {
+	mmc3_2_pins: pinmux_mmc3_2_pins {
+		pinctrl-single,pins = <
+			0x038 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
+			0x044 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
+			0x046 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
+			0x048 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
+			0x042 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
+		>;
+	};
+};
+
 &omap3_pmx_wkup {
 	wlan_host_wkup: pinmux_wlan_host_wkup_pins {
 		pinctrl-single,pins = <
@@ -187,7 +194,7 @@
 	bus-width = <4>;
 	cap-power-off-card;
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins>;
+	pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index f3a0c26..c740e28 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -110,7 +110,18 @@
 
 		omap3_pmx_core: pinmux@48002030 {
 			compatible = "ti,omap3-padconf", "pinctrl-single";
-			reg = <0x48002030 0x05cc>;
+			reg = <0x48002030 0x0238>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
+
+		omap3_pmx_core2: pinmux@480025a0 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025a0 0x005c>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#interrupt-cells = <1>;
-- 
1.8.3.2

Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Tony Lindgren]

* Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org> [131204 09:12]:
> The omap3_pmx_core pinmux device in the device tree handles the system
> controller module (SCM) PADCONFS fonction. Its control registers are
> split in two distinct areas, with other SCM registers in-between. Those
> other registers can't thus be requested by other drivers as the memory
> region gets reserved by the pinmux driver.
> 
> Split the omap3_pmx_core device tree node in two for the two memory
> regions.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> ---
>  arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++++++++++-------
>  arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
>  arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
>  arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
>  arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
>  5 files changed, 95 insertions(+), 36 deletions(-)
> 
> While working on the OMAP3 ISP driver I've run into a failure to request a
> memory region already requested by the pinctrl-single driver. This patch is an
> attempt to fix the problem. An alternative approach would be to support
> multiple reg values in the pinctrl-single driver, but that might not be much
> cleaner. I'm open to suggestions.

Makes sense to me to split it into two, we can save some memory that way too.

It should not cause problems with the wake-up interrupts either as we're
already using a single chained wake-up interrupt between core and wkup
pins.

Do you have some perl or sed script to look for and convert the core2
registers? Or do we just not have that many of them defined yet?

Regards,

Tony
 
> diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
> index 8d7c813..7028e6a 100644
> --- a/arch/arm/boot/dts/omap3-beagle-xm.dts
> +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
> @@ -103,7 +103,7 @@
>  &omap3_pmx_core {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <
> -			&hsusbb2_pins
> +			&hsusb2_pins
>  	>;
>  
>  	uart3_pins: pinmux_uart3_pins {
> @@ -113,14 +113,8 @@
>  		>;
>  	};
>  
> -	hsusbb2_pins: pinmux_hsusbb2_pins {
> +	hsusb2_pins: pinmux_hsusb2_pins {
>  		pinctrl-single,pins = <
> -			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
> -			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
> -			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
> -			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
> -			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
> -			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
>  			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
>  			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
>  			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
> @@ -131,6 +125,24 @@
>  	};
>  };
>  
> +&omap3_pmx_core2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <
> +			&hsusb2_2_pins
> +	>;
> +
> +	hsusb2_2_pins: pinmux_hsusb2_2_pins {
> +		pinctrl-single,pins = <
> +			0x050 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
> +			0x052 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
> +			0x054 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
> +			0x056 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
> +			0x058 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
> +			0x05a (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
> +		>;
> +	};
> +};
> +
>  &i2c1 {
>  	clock-frequency = <2600000>;
>  
> @@ -152,6 +164,23 @@
>  
>  &i2c2 {
>  	clock-frequency = <400000>;
> +
> +	switch@73 {
> +		compatible = "nxp,pca9543";
> +		reg = <0x73>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +		i2c@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
>  };
>  
>  &i2c3 {
> diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
> index 9764556..d2c7322 100644
> --- a/arch/arm/boot/dts/omap3-beagle.dts
> +++ b/arch/arm/boot/dts/omap3-beagle.dts
> @@ -85,17 +85,11 @@
>  &omap3_pmx_core {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <
> -			&hsusbb2_pins
> +			&hsusb2_pins
>  	>;
>  
> -	hsusbb2_pins: pinmux_hsusbb2_pins {
> +	hsusb2_pins: pinmux_hsusb2_pins {
>  		pinctrl-single,pins = <
> -			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
> -			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
> -			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
> -			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
> -			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
> -			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
>  			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
>  			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
>  			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
> @@ -113,6 +107,24 @@
>  	};
>  };
>  
> +&omap3_pmx_core2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <
> +			&hsusb2_2_pins
> +	>;
> +
> +	hsusb2_2_pins: pinmux_hsusb2_2_pins {
> +		pinctrl-single,pins = <
> +			0x050 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
> +			0x052 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
> +			0x054 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
> +			0x056 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
> +			0x058 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
> +			0x05a (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
> +		>;
> +	};
> +};
> +
>  &i2c1 {
>  	clock-frequency = <2600000>;
>  
> diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
> index d5cc792..0f77be8 100644
> --- a/arch/arm/boot/dts/omap3-igep0020.dts
> +++ b/arch/arm/boot/dts/omap3-igep0020.dts
> @@ -63,7 +63,7 @@
>  	};
>  };
>  
> -&omap3_pmx_core {
> +&omap3_pmx_core2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <
>  		&hsusbb1_pins
> @@ -71,18 +71,18 @@
>  
>  	hsusbb1_pins: pinmux_hsusbb1_pins {
>  		pinctrl-single,pins = <
> -			0x5aa (PIN_OUTPUT | MUX_MODE3)		/* etk_ctl.hsusb1_clk */
> -			0x5a8 (PIN_OUTPUT | MUX_MODE3)		/* etk_clk.hsusb1_stp */
> -			0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d8.hsusb1_dir */
> -			0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d9.hsusb1_nxt */
> -			0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d0.hsusb1_data0 */
> -			0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d1.hsusb1_data1 */
> -			0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d2.hsusb1_data2 */
> -			0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d3.hsusb1_data7 */
> -			0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d4.hsusb1_data4 */
> -			0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d5.hsusb1_data5 */
> -			0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d6.hsusb1_data6 */
> -			0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d7.hsusb1_data3 */
> +			0x03a (PIN_OUTPUT | MUX_MODE3)		/* etk_ctl.hsusb1_clk */
> +			0x038 (PIN_OUTPUT | MUX_MODE3)		/* etk_clk.hsusb1_stp */
> +			0x04c (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d8.hsusb1_dir */
> +			0x04e (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d9.hsusb1_nxt */
> +			0x03c (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d0.hsusb1_data0 */
> +			0x03e (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d1.hsusb1_data1 */
> +			0x040 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d2.hsusb1_data2 */
> +			0x042 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d3.hsusb1_data7 */
> +			0x044 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d4.hsusb1_data4 */
> +			0x046 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d5.hsusb1_data5 */
> +			0x048 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d6.hsusb1_data6 */
> +			0x04a (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d7.hsusb1_data3 */
>  		>;
>  	};
>  };
> diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
> index 15eb9fe..a1bec6b 100644
> --- a/arch/arm/boot/dts/omap3-zoom3.dts
> +++ b/arch/arm/boot/dts/omap3-zoom3.dts
> @@ -82,11 +82,6 @@
>  		pinctrl-single,pins = <
>  			0x168 (PIN_INPUT | MUX_MODE4)	/* mcbsp1_clkx.gpio_162 WLAN IRQ */
>  			0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs1.sdmmc3_cmd */
> -			0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
> -			0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
> -			0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
> -			0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
> -			0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
>  		>;
>  	};
>  
> @@ -125,6 +120,18 @@
>  	};
>  };
>  
> +&omap3_pmx_core2 {
> +	mmc3_2_pins: pinmux_mmc3_2_pins {
> +		pinctrl-single,pins = <
> +			0x038 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
> +			0x044 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
> +			0x046 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
> +			0x048 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
> +			0x042 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
> +		>;
> +	};
> +};
> +
>  &omap3_pmx_wkup {
>  	wlan_host_wkup: pinmux_wlan_host_wkup_pins {
>  		pinctrl-single,pins = <
> @@ -187,7 +194,7 @@
>  	bus-width = <4>;
>  	cap-power-off-card;
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc3_pins>;
> +	pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
>  };
>  
>  &uart1 {
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index f3a0c26..c740e28 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -110,7 +110,18 @@
>  
>  		omap3_pmx_core: pinmux@48002030 {
>  			compatible = "ti,omap3-padconf", "pinctrl-single";
> -			reg = <0x48002030 0x05cc>;
> +			reg = <0x48002030 0x0238>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-controller;
> +			pinctrl-single,register-width = <16>;
> +			pinctrl-single,function-mask = <0xff1f>;
> +		};
> +
> +		omap3_pmx_core2: pinmux@480025a0 {
> +			compatible = "ti,omap3-padconf", "pinctrl-single";
> +			reg = <0x480025a0 0x005c>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			#interrupt-cells = <1>;
> -- 
> 1.8.3.2
> 
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Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Laurent Pinchart]

Hi Tony,

On Wednesday 04 December 2013 09:28:53 Tony Lindgren wrote:
> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [131204 09:12]:
> > The omap3_pmx_core pinmux device in the device tree handles the system
> > controller module (SCM) PADCONFS fonction. Its control registers are
> > split in two distinct areas, with other SCM registers in-between. Those
> > other registers can't thus be requested by other drivers as the memory
> > region gets reserved by the pinmux driver.
> > 
> > Split the omap3_pmx_core device tree node in two for the two memory
> > regions.
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > 
> >  arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++++++------
> >  arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
> >  arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
> >  arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
> >  arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
> >  5 files changed, 95 insertions(+), 36 deletions(-)
> > 
> > While working on the OMAP3 ISP driver I've run into a failure to request a
> > memory region already requested by the pinctrl-single driver. This patch
> > is an attempt to fix the problem. An alternative approach would be to
> > support multiple reg values in the pinctrl-single driver, but that might
> > not be much cleaner. I'm open to suggestions.
> 
> Makes sense to me to split it into two, we can save some memory that way
> too.
> 
> It should not cause problems with the wake-up interrupts either as we're
> already using a single chained wake-up interrupt between core and wkup
> pins.
> 
> Do you have some perl or sed script to look for and convert the core2
> registers? Or do we just not have that many of them defined yet?

This patch should cover all the ones we have in mainline. As this is an RFC 
I've performed the conversion manually.

> > diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
> > b/arch/arm/boot/dts/omap3-beagle-xm.dts index 8d7c813..7028e6a 100644
> > --- a/arch/arm/boot/dts/omap3-beagle-xm.dts
> > +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts

[snip]

> > @@ -152,6 +164,23 @@
> > 
> >  &i2c2 {
> >  	clock-frequency = <400000>;
> > +
> > +	switch@73 {
> > +		compatible = "nxp,pca9543";
> > +		reg = <0x73>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		i2c@0 {
> > +			reg = <0>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +		};
> > +		i2c@1 {
> > +			reg = <1>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +		};
> > +	};
> >  };
> >  
> >  &i2c3 {

This should obviously not have been included. I'll submit a v2.

-- 
Regards,

Laurent Pinchart

Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Tony Lindgren]

* Laurent Pinchart <laurent.pinchart@ideasonboard.com> [131204 09:59]:
> Hi Tony,
> 
> On Wednesday 04 December 2013 09:28:53 Tony Lindgren wrote:
> > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [131204 09:12]:
> > > The omap3_pmx_core pinmux device in the device tree handles the system
> > > controller module (SCM) PADCONFS fonction. Its control registers are
> > > split in two distinct areas, with other SCM registers in-between. Those
> > > other registers can't thus be requested by other drivers as the memory
> > > region gets reserved by the pinmux driver.
> > > 
> > > Split the omap3_pmx_core device tree node in two for the two memory
> > > regions.
> > > 
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > ---
> > > 
> > >  arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++++++------
> > >  arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
> > >  arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
> > >  arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
> > >  arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
> > >  5 files changed, 95 insertions(+), 36 deletions(-)
> > > 
> > > While working on the OMAP3 ISP driver I've run into a failure to request a
> > > memory region already requested by the pinctrl-single driver. This patch
> > > is an attempt to fix the problem. An alternative approach would be to
> > > support multiple reg values in the pinctrl-single driver, but that might
> > > not be much cleaner. I'm open to suggestions.
> > 
> > Makes sense to me to split it into two, we can save some memory that way
> > too.
> > 
> > It should not cause problems with the wake-up interrupts either as we're
> > already using a single chained wake-up interrupt between core and wkup
> > pins.
> > 
> > Do you have some perl or sed script to look for and convert the core2
> > registers? Or do we just not have that many of them defined yet?
> 
> This patch should cover all the ones we have in mainline. As this is an RFC 
> I've performed the conversion manually.

OK. I wonder if we should add something like this to make it easier to
use the padconf values from the TRM:

#define OMAP_IOPAD_OFFSET(pa, offset)	((pa) & 0xffff) - (offset))

#define OMAP2_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0030) (val))
#define OMAP3_CORE1_IOPAD(pa, val)	OMAP2_CORE_IOPAD((pa), (val))
#define OMAP3_CORE2_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x05a0) (val))
#define OMAP4_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0040) (val))
#define OMAP4_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xe040) (val))
#define OMAP5_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0840) (val))
#define OMAP5_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xc850) (val))
...

Then we would have entries like:

	pinctrl-single,pins = <
		OMAP3_CORE1_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

instead of:

	pinctrl-single,pins = <
		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

Regards,

Tony

Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Laurent Pinchart]

Hi Tony,

On Wednesday 04 December 2013 10:24:37 Tony Lindgren wrote:
> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [131204 09:59]:
> > Hi Tony,
> > 
> > On Wednesday 04 December 2013 09:28:53 Tony Lindgren wrote:
> > > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [131204 09:12]:
> > > > The omap3_pmx_core pinmux device in the device tree handles the system
> > > > controller module (SCM) PADCONFS fonction. Its control registers are
> > > > split in two distinct areas, with other SCM registers in-between.
> > > > Those other registers can't thus be requested by other drivers as the
> > > > memory region gets reserved by the pinmux driver.
> > > > 
> > > > Split the omap3_pmx_core device tree node in two for the two memory
> > > > regions.
> > > > 
> > > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > > ---
> > > > 
> > > >  arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++------
> > > >  arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
> > > >  arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
> > > >  arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
> > > >  arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
> > > >  5 files changed, 95 insertions(+), 36 deletions(-)
> > > > 
> > > > While working on the OMAP3 ISP driver I've run into a failure to
> > > > request a memory region already requested by the pinctrl-single
> > > > driver. This patch is an attempt to fix the problem. An alternative
> > > > approach would be to support multiple reg values in the pinctrl-single
> > > > driver, but that might not be much cleaner. I'm open to suggestions.
> > > 
> > > Makes sense to me to split it into two, we can save some memory that way
> > > too.
> > > 
> > > It should not cause problems with the wake-up interrupts either as we're
> > > already using a single chained wake-up interrupt between core and wkup
> > > pins.
> > > 
> > > Do you have some perl or sed script to look for and convert the core2
> > > registers? Or do we just not have that many of them defined yet?
> > 
> > This patch should cover all the ones we have in mainline. As this is an
> > RFC I've performed the conversion manually.
> 
> OK. I wonder if we should add something like this to make it easier to
> use the padconf values from the TRM:
> 
> #define OMAP_IOPAD_OFFSET(pa, offset)	((pa) & 0xffff) - (offset))
> 
> #define OMAP2_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0030) (val))
> #define OMAP3_CORE1_IOPAD(pa, val)	OMAP2_CORE_IOPAD((pa), (val))
> #define OMAP3_CORE2_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x05a0) (val))
> #define OMAP4_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0040) (val))
> #define OMAP4_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xe040) (val))
> #define OMAP5_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0840) (val))
> #define OMAP5_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xc850) (val))
> ...
> 
> Then we would have entries like:
> 
> 	pinctrl-single,pins = <
> 		OMAP3_CORE1_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE0)
> 		...
> 	>;
> 
> instead of:
> 
> 	pinctrl-single,pins = <
> 		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
> 		...
> 	>;

That's a good idea, it would be much more readable. Would you like to submit a 
patch ? Should I rebase my patch on top of that, or the other way around ?

-- 
Regards,

Laurent Pinchart

Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Tony Lindgren]

* Laurent Pinchart <laurent.pinchart@ideasonboard.com> [131204 10:45]:
> On Wednesday 04 December 2013 10:24:37 Tony Lindgren wrote:
> > 
> > OK. I wonder if we should add something like this to make it easier to
> > use the padconf values from the TRM:
> > 
> > #define OMAP_IOPAD_OFFSET(pa, offset)	((pa) & 0xffff) - (offset))
> > 
> > #define OMAP2_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0030) (val))
> > #define OMAP3_CORE1_IOPAD(pa, val)	OMAP2_CORE_IOPAD((pa), (val))
> > #define OMAP3_CORE2_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x05a0) (val))
> > #define OMAP4_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0040) (val))
> > #define OMAP4_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xe040) (val))
> > #define OMAP5_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0840) (val))
> > #define OMAP5_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xc850) (val))
> > ...
> > 
> > Then we would have entries like:
> > 
> > 	pinctrl-single,pins = <
> > 		OMAP3_CORE1_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE0)
> > 		...
> > 	>;
> > 
> > instead of:
> > 
> > 	pinctrl-single,pins = <
> > 		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
> > 		...
> > 	>;
> 
> That's a good idea, it would be much more readable. Would you like to submit a 
> patch ? Should I rebase my patch on top of that, or the other way around ?

OK I'll do a patch for that later on today, then you can use that. Might
cut down the churn a little that way.

Regards,

Tony

Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [131204 10:54]:
> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [131204 10:45]:
> > On Wednesday 04 December 2013 10:24:37 Tony Lindgren wrote:
> > > 
> > > OK. I wonder if we should add something like this to make it easier to
> > > use the padconf values from the TRM:
> > > 
> > > #define OMAP_IOPAD_OFFSET(pa, offset)	((pa) & 0xffff) - (offset))
> > > 
> > > #define OMAP2_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0030) (val))
> > > #define OMAP3_CORE1_IOPAD(pa, val)	OMAP2_CORE_IOPAD((pa), (val))
> > > #define OMAP3_CORE2_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x05a0) (val))
> > > #define OMAP4_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0040) (val))
> > > #define OMAP4_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xe040) (val))
> > > #define OMAP5_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0840) (val))
> > > #define OMAP5_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xc850) (val))
> > > ...
> > > 
> > > Then we would have entries like:
> > > 
> > > 	pinctrl-single,pins = <
> > > 		OMAP3_CORE1_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE0)
> > > 		...
> > > 	>;
> > > 
> > > instead of:
> > > 
> > > 	pinctrl-single,pins = <
> > > 		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
> > > 		...
> > > 	>;
> > 
> > That's a good idea, it would be much more readable. Would you like to submit a 
> > patch ? Should I rebase my patch on top of that, or the other way around ?
> 
> OK I'll do a patch for that later on today, then you can use that. Might
> cut down the churn a little that way.

Here's the patch for it, needs some checks and testing as I got several
things wrong in the example above :)

Regards,

Tony

8< ----------------------------

From: Tony Lindgren <tony@atomide.com>
Date: Wed, 4 Dec 2013 13:03:58 -0800
Subject: [PATCH] ARM: dts: Add omap specific pinctrl defines to use padconf addresses

As we have one to three pinctrl-single instances for each SoC it is
a bit confusing to configure the padconf register offset from the
base of the padconf register base.

Let's add macros that allow using the physical address of the
padconf register directly, or in most cases, just the last 16-bits
of the address as they are shown in the documentation.

Note that most documentation shows two padconf registers for each
32-bit address, so adding 2 to the documentation address is needed for
the second padconf register as we treat them as 16-bit registers
for omap3+.

For example, omap36xx documentation shows sdmmc2_clk at 0x48002158,
so we can just use the last 16-bits of that value:

	pinctrl-single,pins = <
		OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

And we don't need to separately calculate the offset from the 0x2030
base:

	pinctrl-single,pins = <
		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

Naturally both ways of defining the registers can be used, and I'm
not saying we should replace all the existing defines. But it may
be handy to use these macros for new entries and when doing other
related .dts file clean-up.

Signed-off-by: Tony Lindgren <tony@atomide.com>

--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -49,5 +49,24 @@
 #define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
 #define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
 
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0030) (val))
+#define OMAP2430_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x2030) (val))
+#define OMAP3_CORE1_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x2030) (val))
+#define OMAP3_CORE2_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x25a0) (val))
+#define OMAP3_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x2a00) (val))
+#define AM33XX_IOPAD(pa, val)		(OMAP_IOPAD_OFFSET((pa), 0x0800) (val))
+#define OMAP4_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x0040) (val))
+#define OMAP4_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xe040) (val))
+#define AM4372_IOPAD(pa, val)		(OMAP_IOPAD_OFFSET((pa), 0x0800) (val))
+#define OMAP5_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x2840) (val))
+#define OMAP5_WKUP_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0xc840) (val))
+#define DRA7XX_CORE_IOPAD(pa, val)	(OMAP_IOPAD_OFFSET((pa), 0x3400) (val))
+
 #endif
 

Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Sebastian Reichel]

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On Wed, Dec 04, 2013 at 06:11:50PM +0100, Laurent Pinchart wrote:
> The omap3_pmx_core pinmux device in the device tree handles the system
> controller module (SCM) PADCONFS fonction. Its control registers are
> split in two distinct areas, with other SCM registers in-between. Those
> other registers can't thus be requested by other drivers as the memory
> region gets reserved by the pinmux driver.
> 
> Split the omap3_pmx_core device tree node in two for the two memory
> regions.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
>  arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++++++++++-------
>  arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
>  arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
>  arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
>  arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
>  5 files changed, 95 insertions(+), 36 deletions(-)
> 
> While working on the OMAP3 ISP driver I've run into a failure to request a
> memory region already requested by the pinctrl-single driver. This patch is an
> attempt to fix the problem. An alternative approach would be to support
> multiple reg values in the pinctrl-single driver, but that might not be much
> cleaner. I'm open to suggestions.

Acked-By: Sebastian Reichel <sre@debian.org>

I haven't checked the board dts files, but the change in omap3.dtsi is
needed to "fix a external abort on non-linefetch" when doing

cat /sys/kernel/debug/pinctrl/.../pins

on my Nokia N900.

-- Sebastian

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Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Tony Lindgren]

* Sebastian Reichel <sre@ring0.de> [131219 09:19]:
> On Wed, Dec 04, 2013 at 06:11:50PM +0100, Laurent Pinchart wrote:
> > The omap3_pmx_core pinmux device in the device tree handles the system
> > controller module (SCM) PADCONFS fonction. Its control registers are
> > split in two distinct areas, with other SCM registers in-between. Those
> > other registers can't thus be requested by other drivers as the memory
> > region gets reserved by the pinmux driver.
> > 
> > Split the omap3_pmx_core device tree node in two for the two memory
> > regions.
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> >  arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++++++++++-------
> >  arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
> >  arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
> >  arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
> >  arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
> >  5 files changed, 95 insertions(+), 36 deletions(-)
> > 
> > While working on the OMAP3 ISP driver I've run into a failure to request a
> > memory region already requested by the pinctrl-single driver. This patch is an
> > attempt to fix the problem. An alternative approach would be to support
> > multiple reg values in the pinctrl-single driver, but that might not be much
> > cleaner. I'm open to suggestions.
> 
> Acked-By: Sebastian Reichel <sre@debian.org>
> 
> I haven't checked the board dts files, but the change in omap3.dtsi is
> needed to "fix a external abort on non-linefetch" when doing
> 
> cat /sys/kernel/debug/pinctrl/.../pins
> 
> on my Nokia N900.

OK, that should be mentioned in the patch. Laurent, care to update the patch
for that?

We should also check that the register ranges match with Nishant's similar
patch "[PATCH] ARM: dts: omap3: split pinctrl for core into two parts".

Regards,

Tony

Re: [PATCH/RFC] ARM: omap3: Split the pinmux core device

[Laurent Pinchart]

Hi Tony,

On Thursday 19 December 2013 10:30:03 Tony Lindgren wrote:
> * Sebastian Reichel <sre@ring0.de> [131219 09:19]:
> > On Wed, Dec 04, 2013 at 06:11:50PM +0100, Laurent Pinchart wrote:
> > > The omap3_pmx_core pinmux device in the device tree handles the system
> > > controller module (SCM) PADCONFS fonction. Its control registers are
> > > split in two distinct areas, with other SCM registers in-between. Those
> > > other registers can't thus be requested by other drivers as the memory
> > > region gets reserved by the pinmux driver.
> > > 
> > > Split the omap3_pmx_core device tree node in two for the two memory
> > > regions.
> > > 
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > ---
> > > 
> > >  arch/arm/boot/dts/omap3-beagle-xm.dts | 45 ++++++++++++++++++++++------
> > >  arch/arm/boot/dts/omap3-beagle.dts    | 28 +++++++++++++++-------
> > >  arch/arm/boot/dts/omap3-igep0020.dts  | 26 ++++++++++----------
> > >  arch/arm/boot/dts/omap3-zoom3.dts     | 19 ++++++++++-----
> > >  arch/arm/boot/dts/omap3.dtsi          | 13 +++++++++-
> > >  5 files changed, 95 insertions(+), 36 deletions(-)
> > > 
> > > While working on the OMAP3 ISP driver I've run into a failure to request
> > > a memory region already requested by the pinctrl-single driver. This
> > > patch is an attempt to fix the problem. An alternative approach would be
> > > to support multiple reg values in the pinctrl-single driver, but that
> > > might not be much cleaner. I'm open to suggestions.
> > 
> > Acked-By: Sebastian Reichel <sre@debian.org>
> > 
> > I haven't checked the board dts files, but the change in omap3.dtsi is
> > needed to "fix a external abort on non-linefetch" when doing
> > 
> > cat /sys/kernel/debug/pinctrl/.../pins
> > 
> > on my Nokia N900.
> 
> OK, that should be mentioned in the patch. Laurent, care to update the patch
> for that?

Done.

> We should also check that the register ranges match with Nishant's similar
> patch "[PATCH] ARM: dts: omap3: split pinctrl for core into two parts".

I've checked Nishanth's patch and updated mine as I had forgotten the LED pins 
on the IGEP boards. Reviewing the two patches side by side wouldn't hurt of 
course.

-- 
Regards,

Laurent Pinchart