[PATCH v4 10/15] usb: phy: msm: Add device tree support and binding information

[PATCH v4 10/15] usb: phy: msm: Add device tree support and binding information

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov@mm-sol.com>

Allows MSM OTG controller to be specified via device tree.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Cc: devicetree@vger.kernel.org
---
 .../devicetree/bindings/usb/msm-hsusb.txt          |   57 +++++++++++++-
 drivers/usb/phy/phy-msm-usb.c                      |   79 +++++++++++++++++---
 2 files changed, 124 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 0a85eba..f1045e3 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -30,4 +30,59 @@ Required properties:
 		dr_mode = "peripheral";
 		interrupts = <0 134 0>;
 		usb-phy = <&usb_otg>;
-	};
\ No newline at end of file
+	};
+
+USB PHY with optional OTG:
+
+Required properties:
+- compatible:	should contain "qcom,usb-otg-ci" for chipsets with
+				Chipidea 45nm PHY or "qcom,usb-otg-snps" for chipsets
+				with Synopsys 28nm PHY
+- regs:			offset and length of the register set in the memory map
+- interrupts:	interrupt-specifier for the OTG interrupt.
+
+- clocks:		A list of phandle + clock-specifier pairs for the
+				clocks listed in clock-names
+- clock-names:	Should contain the following:
+  "phy"			USB PHY reference clock
+  "core"		Protocol engine clock
+  "iface"		Interface bus clock
+  "alt_core"	Optional: Protocol engine clock for targets with asynchronous
+				reset methodology.
+
+- dr_mode:		One of "host", "peripheral" or "otg". Defaults to "otg"
+
+- vdccx-supply:	phandle to the regulator for the vdd supply for
+				digital circuit operation.
+- v1p8-supply:	phandle to the regulator for the 1.8V supply
+- v3p3-supply:	phandle to the regulator for the 3.3V supply
+
+- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
+				1 - PHY control
+				2 - PMIC control
+				3 - User control (via debugfs)
+
+Optional properties:
+- qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
+				terminate with -1
+
+Example HSUSB OTG controller device node:
+
+	usb@f9a55000 {
+		compatible = "qcom,usb-otg-snps";
+		reg = <0xf9a55000 0x400>;
+		interrupts = <0 134 0>;;
+		dr_mode = "peripheral";
+
+		clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
+				<&gcc GCC_USB_HS_AHB_CLK>;
+
+		clock-names = "phy", "core", "iface";
+
+		vddcx-supply = <&pm8841_s2_corner>;
+		v1p8-supply = <&pm8941_l6>;
+		v3p3-supply = <&pm8941_l24>;
+
+		qcom,otg-control = <1>;
+		qcom,phy-init-sequence = <0x01 0x90 0xffffffff>;
+	};
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index fa8e672d..cc230c8 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -30,9 +30,12 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <linux/usb.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/of.h>
 #include <linux/usb/ulpi.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/hcd.h>
@@ -1343,25 +1346,75 @@ static void msm_otg_debugfs_cleanup(void)
 	debugfs_remove(msm_otg_dbg_root);
 }
 
+static struct of_device_id msm_otg_dt_match[] = {
+	{
+		.compatible = "qcom,usb-otg-ci",
+		.data = (void *) CI_45NM_INTEGRATED_PHY
+	}, {
+		.compatible = "qcom,usb-otg-snps",
+		.data = (void *) SNPS_28NM_INTEGRATED_PHY
+	}, {}
+};
+
+static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
+{
+	struct msm_otg_platform_data *pdata;
+	const struct of_device_id *id;
+	struct device_node *node = pdev->dev.of_node;
+	int len = 0;
+	u32 val;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	motg->pdata = pdata;
+
+	id = of_match_device(msm_otg_dt_match, &pdev->dev);
+	pdata->phy_type = (int) id->data;
+
+	pdata->mode = of_usb_get_dr_mode(node);
+	if (pdata->mode == USB_DR_MODE_UNKNOWN)
+		pdata->mode = USB_DR_MODE_OTG;
+
+	pdata->otg_control = OTG_PHY_CONTROL;
+	if (!of_property_read_u32(node, "qcom,otg-control", &val))
+		pdata->otg_control = val;
+
+	if (!of_get_property(node, "qcom,phy-init-sequence", &len) || !len)
+		return 0;
+
+	pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+	if (!pdata->phy_init_seq)
+		return 0;
+
+	of_property_read_u32_array(node, "qcom,phy-init-sequence",
+				   pdata->phy_init_seq,
+				   len / sizeof(*pdata->phy_init_seq));
+	return 0;
+}
+
 static int __init msm_otg_probe(struct platform_device *pdev)
 {
 	int ret = 0;
+	struct device_node *np = pdev->dev.of_node;
+	struct msm_otg_platform_data *pdata;
 	struct resource *res;
 	struct msm_otg *motg;
 	struct usb_phy *phy;
 
-	dev_info(&pdev->dev, "msm_otg probe\n");
-	if (!dev_get_platdata(&pdev->dev)) {
-		dev_err(&pdev->dev, "No platform data given. Bailing out\n");
-		return -ENODEV;
-	}
-
 	motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
 	if (!motg) {
 		dev_err(&pdev->dev, "unable to allocate msm_otg\n");
 		return -ENOMEM;
 	}
 
+	pdata = dev_get_platdata(&pdev->dev);
+	if (!pdata)
+		ret = msm_otg_read_dt(pdev, motg);
+		if (ret)
+			return ret;
+
 	motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
 				     GFP_KERNEL);
 	if (!motg->phy.otg) {
@@ -1369,17 +1422,17 @@ static int __init msm_otg_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	motg->pdata = dev_get_platdata(&pdev->dev);
 	phy = &motg->phy;
 	phy->dev = &pdev->dev;
 
-	motg->phy_reset_clk = devm_clk_get(&pdev->dev, "usb_phy_clk");
+	motg->phy_reset_clk = devm_clk_get(&pdev->dev,
+					   np ? "phy" : "usb_phy_clk");
 	if (IS_ERR(motg->phy_reset_clk)) {
 		dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
 		return PTR_ERR(motg->phy_reset_clk);
 	}
 
-	motg->clk = devm_clk_get(&pdev->dev, "usb_hs_clk");
+	motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
 	if (IS_ERR(motg->clk)) {
 		dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
 		return PTR_ERR(motg->clk);
@@ -1391,7 +1444,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
 	 * operation and USB core cannot tolerate frequency changes on
 	 * CORE CLK.
 	 */
-	motg->pclk = devm_clk_get(&pdev->dev, "usb_hs_pclk");
+	motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
 	if (IS_ERR(motg->pclk)) {
 		dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
 		return PTR_ERR(motg->pclk);
@@ -1402,7 +1455,8 @@ static int __init msm_otg_probe(struct platform_device *pdev)
 	 * clock is introduced to remove the dependency on AXI
 	 * bus frequency.
 	 */
-	motg->core_clk = devm_clk_get(&pdev->dev, "usb_hs_core_clk");
+	motg->core_clk = devm_clk_get(&pdev->dev,
+				      np ? "alt_core" : "usb_hs_core_clk");
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
@@ -1639,6 +1693,8 @@ static const struct dev_pm_ops msm_otg_dev_pm_ops = {
 };
 #endif
 
+MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
+
 static struct platform_driver msm_otg_driver = {
 	.probe = msm_otg_probe,
 	.remove = msm_otg_remove,
@@ -1648,6 +1704,7 @@ static struct platform_driver msm_otg_driver = {
 #ifdef CONFIG_PM
 		.pm = &msm_otg_dev_pm_ops,
 #endif
+		.of_match_table = msm_otg_dt_match,
 	},
 };
 
-- 
1.7.9.5

[PATCH v4 11/15] usb: phy: msm: Use reset framework for LINK and PHY resets

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov@mm-sol.com>

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Cc: devicetree@vger.kernel.org
---
 .../devicetree/bindings/usb/msm-hsusb.txt          |    9 ++++++
 drivers/usb/phy/phy-msm-usb.c                      |   30 ++++++++++++++------
 include/linux/usb/msm_hsusb.h                      |    3 ++
 3 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index f1045e3..3f21204 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -57,6 +57,12 @@ Required properties:
 - v1p8-supply:	phandle to the regulator for the 1.8V supply
 - v3p3-supply:	phandle to the regulator for the 3.3V supply
 
+- resets:		A list of phandle + reset-specifier pairs for the
+				resets listed in reset-names
+- reset-names:	Should contain the following:
+  "phy"			USB PHY controller reset
+  "link"		USB LINK controller reset
+
 - qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
 				1 - PHY control
 				2 - PMIC control
@@ -83,6 +89,9 @@ Example HSUSB OTG controller device node:
 		v1p8-supply = <&pm8941_l6>;
 		v3p3-supply = <&pm8941_l24>;
 
+		resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
+		reset-names = "phy", "link";
+
 		qcom,otg-control = <1>;
 		qcom,phy-init-sequence = <0x01 0x90 0xffffffff>;
 	};
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index cc230c8..53fc645 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -32,6 +32,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/reset.h>
 
 #include <linux/usb.h>
 #include <linux/usb/otg.h>
@@ -260,12 +261,16 @@ static void ulpi_init(struct msm_otg *motg)
 
 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 {
-	int ret = 0;
+	int ret;
 
-	if (!motg->pdata->link_clk_reset)
-		return ret;
+	if (motg->pdata->link_clk_reset)
+		ret = motg->pdata->link_clk_reset(motg->clk, assert);
+	else
+		if (assert)
+			ret = reset_control_assert(motg->link_rst);
+		else
+			ret = reset_control_deassert(motg->link_rst);
 
-	ret = motg->pdata->link_clk_reset(motg->clk, assert);
 	if (ret)
 		dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 			assert ? "assert" : "deassert");
@@ -275,12 +280,13 @@ static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 
 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 {
-	int ret = 0;
+	int ret;
 
-	if (!motg->pdata->phy_clk_reset)
-		return ret;
+	if (motg->pdata->phy_clk_reset)
+		ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
+	else
+		ret = reset_control_reset(motg->phy_rst);
 
-	ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
 	if (ret)
 		dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 
@@ -1373,6 +1379,14 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
 	id = of_match_device(msm_otg_dt_match, &pdev->dev);
 	pdata->phy_type = (int) id->data;
 
+	motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
+	if (IS_ERR(motg->link_rst))
+		return PTR_ERR(motg->link_rst);
+
+	motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
+	if (IS_ERR(motg->phy_rst))
+		return PTR_ERR(motg->phy_rst);
+
 	pdata->mode = of_usb_get_dr_mode(node);
 	if (pdata->mode == USB_DR_MODE_UNKNOWN)
 		pdata->mode = USB_DR_MODE_OTG;
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 262ed80..9bf8943 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -163,6 +163,9 @@ struct msm_otg {
 	struct regulator *v3p3;
 	struct regulator *v1p8;
 	struct regulator *vddcx;
+
+	struct reset_control *phy_rst;
+	struct reset_control *link_rst;
 };
 
 #endif
-- 
1.7.9.5

[PATCH v4 12/15] usb: phy: msm: Add support for secondary PHY control

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>

Allow support to use 2nd HSPHY with USB2 Core.
Some platforms may have configuration to allow USB controller
work with any of the two HSPHYs present. By default driver
configures USB core to use primary HSPHY. Add support to allow
user select 2nd HSPHY using DT parameter.

Signed-off-by: Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
Cc: Manu Gautam <mgautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 .../devicetree/bindings/usb/msm-hsusb.txt          |    6 +++++
 drivers/usb/phy/phy-msm-usb.c                      |   24 ++++++++++++++++++--
 include/linux/usb/msm_hsusb.h                      |    1 +
 include/linux/usb/msm_hsusb_hw.h                   |    1 +
 4 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 3f21204..d105ba9 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -72,6 +72,12 @@ Optional properties:
 - qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
 				terminate with -1
 
+- qcom,phy-num:	Select number of pyco-phy to use, can be one of
+				0 - PHY one, default
+				1 - Second PHY
+				Some platforms may have configuration to allow USB
+				controller work with any of the two HSPHYs present.
+
 Example HSUSB OTG controller device node:
 
 	usb@f9a55000 {
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 53fc645..01b571ff 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -340,6 +340,9 @@ static int msm_otg_phy_reset(struct msm_otg *motg)
 	if (!retries)
 		return -ETIMEDOUT;
 
+	if (motg->phy_number)
+		writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
+
 	dev_info(motg->phy.dev, "phy_reset: success\n");
 	return 0;
 }
@@ -394,6 +397,9 @@ static int msm_otg_reset(struct usb_phy *phy)
 		ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 	}
 
+	if (motg->phy_number)
+		writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
+
 	return 0;
 }
 
@@ -406,6 +412,7 @@ static int msm_otg_suspend(struct msm_otg *motg)
 	struct usb_phy *phy = &motg->phy;
 	struct usb_bus *bus = phy->otg->host;
 	struct msm_otg_platform_data *pdata = motg->pdata;
+	void __iomem *addr;
 	int cnt = 0;
 
 	if (atomic_read(&motg->in_lpm))
@@ -465,9 +472,13 @@ static int msm_otg_suspend(struct msm_otg *motg)
 	 */
 	writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 
+	addr = USB_PHY_CTRL;
+	if (motg->phy_number)
+		addr = USB_PHY_CTRL2;
+
 	if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 			motg->pdata->otg_control == OTG_PMIC_CONTROL)
-		writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
+		writel(readl(addr) | PHY_RETEN, addr);
 
 	clk_disable_unprepare(motg->pclk);
 	clk_disable_unprepare(motg->clk);
@@ -497,6 +508,7 @@ static int msm_otg_resume(struct msm_otg *motg)
 {
 	struct usb_phy *phy = &motg->phy;
 	struct usb_bus *bus = phy->otg->host;
+	void __iomem *addr;
 	int cnt = 0;
 	unsigned temp;
 
@@ -510,9 +522,14 @@ static int msm_otg_resume(struct msm_otg *motg)
 
 	if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 			motg->pdata->otg_control == OTG_PMIC_CONTROL) {
+
+		addr = USB_PHY_CTRL;
+		if (motg->phy_number)
+			addr = USB_PHY_CTRL2;
+
 		msm_hsusb_ldo_set_mode(motg, 1);
 		msm_hsusb_config_vddcx(motg, 1);
-		writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
+		writel(readl(addr) & ~PHY_RETEN, addr);
 	}
 
 	temp = readl(USB_USBCMD);
@@ -1395,6 +1412,9 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
 	if (!of_property_read_u32(node, "qcom,otg-control", &val))
 		pdata->otg_control = val;
 
+	if (!of_property_read_u32(node, "qcom,phy-num", &val))
+		motg->phy_number = val;
+
 	if (!of_get_property(node, "qcom,phy-init-sequence", &len) || !len)
 		return 0;
 
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 9bf8943..da3a974 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -156,6 +156,7 @@ struct msm_otg {
 	atomic_t in_lpm;
 	int async_int;
 	unsigned cur_power;
+	int phy_number;
 	struct delayed_work chg_work;
 	enum usb_chg_state chg_state;
 	enum usb_chg_type chg_type;
diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h
index 6e97a2d..e6d7035 100644
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -25,6 +25,7 @@
 #define USB_OTGSC            (MSM_USB_BASE + 0x01A4)
 #define USB_USBMODE          (MSM_USB_BASE + 0x01A8)
 #define USB_PHY_CTRL         (MSM_USB_BASE + 0x0240)
+#define USB_PHY_CTRL2        (MSM_USB_BASE + 0x0278)
 
 #define USBCMD_RESET   2
 #define USB_USBINTR          (MSM_USB_BASE + 0x0148)
-- 
1.7.9.5

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[PATCH v4 15/15] usb: phy: msm: Vote for corner of VDD CX instead of voltage of VDD CX

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov@mm-sol.com>

New platform uses RBCPR hardware feature, with that voting for
absolute voltage of VDD CX is not required. Hence vote for corner of
VDD CX which uses nominal corner voltage on VDD CX.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Cc: Mayank Rana <mrana@codeaurora.org>
Cc: devicetree@vger.kernel.org
---
 .../devicetree/bindings/usb/msm-hsusb.txt          |    6 ++++
 drivers/usb/phy/phy-msm-usb.c                      |   35 +++++++++++++++-----
 include/linux/usb/msm_hsusb.h                      |    1 +
 3 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index d105ba9..7b46395 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -78,6 +78,11 @@ Optional properties:
 				Some platforms may have configuration to allow USB
 				controller work with any of the two HSPHYs present.
 
+- qcom,vdd-levels: This property must be a list of three integer
+				values (no, min, max) where each value represents
+				either a voltage in microvolts or a value corresponding
+				to voltage corner.
+
 Example HSUSB OTG controller device node:
 
 	usb@f9a55000 {
@@ -100,4 +105,5 @@ Example HSUSB OTG controller device node:
 
 		qcom,otg-control = <1>;
 		qcom,phy-init-sequence = <0x01 0x90 0xffffffff>;
+		qcom,vdd-levels = <1 5 7>;
 	};
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 970f96b..b6e18b6 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -62,6 +62,13 @@
 
 #define USB_PHY_VDD_DIG_VOL_MIN	1000000 /* uV */
 #define USB_PHY_VDD_DIG_VOL_MAX	1320000 /* uV */
+#define USB_PHY_SUSP_DIG_VOL	500000  /* uV */
+
+enum vdd_levels {
+	VDD_LEVEL_NONE = 0,
+	VDD_LEVEL_MIN,
+	VDD_LEVEL_MAX,
+};
 
 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
 {
@@ -69,8 +76,8 @@ static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
 
 	if (init) {
 		ret = regulator_set_voltage(motg->vddcx,
-				USB_PHY_VDD_DIG_VOL_MIN,
-				USB_PHY_VDD_DIG_VOL_MAX);
+				motg->vdd_levels[VDD_LEVEL_MIN],
+				motg->vdd_levels[VDD_LEVEL_MAX]);
 		if (ret) {
 			dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 			return ret;
@@ -81,7 +88,7 @@ static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
 			dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
 	} else {
 		ret = regulator_set_voltage(motg->vddcx, 0,
-			USB_PHY_VDD_DIG_VOL_MAX);
+				motg->vdd_levels[VDD_LEVEL_MAX]);
 		if (ret)
 			dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 		ret = regulator_disable(motg->vddcx);
@@ -131,17 +138,16 @@ exit:
 }
 
 #ifdef CONFIG_PM_SLEEP
-#define USB_PHY_SUSP_DIG_VOL  500000
 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 {
-	int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+	int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
 	int min_vol;
 	int ret;
 
 	if (high)
-		min_vol = USB_PHY_VDD_DIG_VOL_MIN;
+		min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
 	else
-		min_vol = USB_PHY_SUSP_DIG_VOL;
+		min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
 
 	ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 	if (ret) {
@@ -1437,7 +1443,7 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
 	const struct of_device_id *id;
 	struct device_node *node = pdev->dev.of_node;
 	int len = 0;
-	u32 val;
+	u32 val, tmp[3];
 
 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 	if (!pdata)
@@ -1467,6 +1473,19 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
 	if (!of_property_read_u32(node, "qcom,phy-num", &val))
 		motg->phy_number = val;
 
+	motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
+	motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
+	motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
+
+	if (of_get_property(node, "qcom,vdd-levels", &len) &&
+	    len == sizeof(tmp)) {
+		of_property_read_u32_array(node, "qcom,vdd-levels",
+					   tmp, len / sizeof(*tmp));
+		motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
+		motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
+		motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
+	}
+
 	if (!of_get_property(node, "qcom,phy-init-sequence", &len) || !len)
 		return 0;
 
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index da3a974..f612cb9 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -167,6 +167,7 @@ struct msm_otg {
 
 	struct reset_control *phy_rst;
 	struct reset_control *link_rst;
+	int vdd_levels[3];
 };
 
 #endif
-- 
1.7.9.5

Re: [PATCH v4 10/15] usb: phy: msm: Add device tree support and binding information

[Mark Rutland]

On Tue, Nov 12, 2013 at 02:51:45PM +0000, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> 
> Allows MSM OTG controller to be specified via device tree.
> 
> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> Cc: devicetree@vger.kernel.org
> ---
>  .../devicetree/bindings/usb/msm-hsusb.txt          |   57 +++++++++++++-
>  drivers/usb/phy/phy-msm-usb.c                      |   79 +++++++++++++++++---
>  2 files changed, 124 insertions(+), 12 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> index 0a85eba..f1045e3 100644
> --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> @@ -30,4 +30,59 @@ Required properties:
>  		dr_mode = "peripheral";
>  		interrupts = <0 134 0>;
>  		usb-phy = <&usb_otg>;
> -	};
> \ No newline at end of file
> +	};
> +
> +USB PHY with optional OTG:
> +
> +Required properties:
> +- compatible:	should contain "qcom,usb-otg-ci" for chipsets with
> +				Chipidea 45nm PHY or "qcom,usb-otg-snps" for chipsets
> +				with Synopsys 28nm PHY

To make this easier to read and extend in future, I'd reorganise this
like so:

compatible: should contain:
 * "qcom,usb-otg-ci" for chipsets with Chipidea 45nm PHY
 * "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY

> +- regs:			offset and length of the register set in the memory map
> +- interrupts:	interrupt-specifier for the OTG interrupt.
> +
> +- clocks:		A list of phandle + clock-specifier pairs for the
> +				clocks listed in clock-names
> +- clock-names:	Should contain the following:
> +  "phy"			USB PHY reference clock
> +  "core"		Protocol engine clock
> +  "iface"		Interface bus clock
> +  "alt_core"	Optional: Protocol engine clock for targets with asynchronous
> +				reset methodology.

I'd rearrange that last entry:

"alt_core": Protocol engine clock for targets with asynchronous
            reset methodology. (optional)

> +
> +- dr_mode:		One of "host", "peripheral" or "otg". Defaults to "otg"

If this has a default and thus isn't required, it should be listed as
optional.

> +
> +- vdccx-supply:	phandle to the regulator for the vdd supply for
> +				digital circuit operation.
> +- v1p8-supply:	phandle to the regulator for the 1.8V supply
> +- v3p3-supply:	phandle to the regulator for the 3.3V supply
> +
> +- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
> +				1 - PHY control
> +				2 - PMIC control
> +				3 - User control (via debugfs)

NAK. This does not seem like a description of the hardware, and given
the debugfs comment is fundamentally tied to the way Linux functions
today.

> +
> +Optional properties:
> +- qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
> +				terminate with -1

What is this? I'm really not keen on having arbitrary register/memory
poking sequences in the dt.

Why does it need to be terminated? Surely the size of the property tells
you that it's terminated.

> +
> +Example HSUSB OTG controller device node:
> +
> +	usb@f9a55000 {
> +		compatible = "qcom,usb-otg-snps";
> +		reg = <0xf9a55000 0x400>;
> +		interrupts = <0 134 0>;;

s/;;/;/

> +		dr_mode = "peripheral";
> +
> +		clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
> +				<&gcc GCC_USB_HS_AHB_CLK>;
> +
> +		clock-names = "phy", "core", "iface";
> +
> +		vddcx-supply = <&pm8841_s2_corner>;
> +		v1p8-supply = <&pm8941_l6>;
> +		v3p3-supply = <&pm8941_l24>;
> +
> +		qcom,otg-control = <1>;
> +		qcom,phy-init-sequence = <0x01 0x90 0xffffffff>;

I believe modern dtc versions can handle negative numbers directly.

[...]

> +static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
> +{
> +	struct msm_otg_platform_data *pdata;
> +	const struct of_device_id *id;
> +	struct device_node *node = pdev->dev.of_node;
> +	int len = 0;
> +	u32 val;
> +
> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	motg->pdata = pdata;
> +
> +	id = of_match_device(msm_otg_dt_match, &pdev->dev);
> +	pdata->phy_type = (int) id->data;
> +
> +	pdata->mode = of_usb_get_dr_mode(node);
> +	if (pdata->mode == USB_DR_MODE_UNKNOWN)
> +		pdata->mode = USB_DR_MODE_OTG;
> +
> +	pdata->otg_control = OTG_PHY_CONTROL;
> +	if (!of_property_read_u32(node, "qcom,otg-control", &val))
> +		pdata->otg_control = val;

Is this validated elsewhere?

Thanks,
Mark.

Re: [PATCH v4 12/15] usb: phy: msm: Add support for secondary PHY control

[Mark Rutland]

On Tue, Nov 12, 2013 at 02:51:47PM +0000, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> 
> Allow support to use 2nd HSPHY with USB2 Core.
> Some platforms may have configuration to allow USB controller
> work with any of the two HSPHYs present. By default driver
> configures USB core to use primary HSPHY. Add support to allow
> user select 2nd HSPHY using DT parameter.
> 
> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> Cc: Manu Gautam <mgautam@codeaurora.org>
> Cc: devicetree@vger.kernel.org
> ---
>  .../devicetree/bindings/usb/msm-hsusb.txt          |    6 +++++
>  drivers/usb/phy/phy-msm-usb.c                      |   24 ++++++++++++++++++--
>  include/linux/usb/msm_hsusb.h                      |    1 +
>  include/linux/usb/msm_hsusb_hw.h                   |    1 +
>  4 files changed, 30 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> index 3f21204..d105ba9 100644
> --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> @@ -72,6 +72,12 @@ Optional properties:
>  - qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
>  				terminate with -1
>  
> +- qcom,phy-num:	Select number of pyco-phy to use, can be one of
> +				0 - PHY one, default
> +				1 - Second PHY
> +				Some platforms may have configuration to allow USB
> +				controller work with any of the two HSPHYs present.
> +

Only one can be used at a time?

[...]

> @@ -1395,6 +1412,9 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
>  	if (!of_property_read_u32(node, "qcom,otg-control", &val))
>  		pdata->otg_control = val;
>  
> +	if (!of_property_read_u32(node, "qcom,phy-num", &val))
> +		motg->phy_number = val;

No sanity checking? If not all of your tests on the value of
motg->phy_number are the same form, you may get undepected results...

Mark.

Re: [PATCH v4 10/15] usb: phy: msm: Add device tree support and binding information

[Ivan T. Ivanov]

Hi Mark, 

On Fri, 2013-11-15 at 16:38 +0000, Mark Rutland wrote: 
> On Tue, Nov 12, 2013 at 02:51:45PM +0000, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > 
> > Allows MSM OTG controller to be specified via device tree.
> > 
> > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > Cc: devicetree@vger.kernel.org
> > ---
> >  .../devicetree/bindings/usb/msm-hsusb.txt          |   57 +++++++++++++-
> >  drivers/usb/phy/phy-msm-usb.c                      |   79 +++++++++++++++++---
> >  2 files changed, 124 insertions(+), 12 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > index 0a85eba..f1045e3 100644
> > --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > @@ -30,4 +30,59 @@ Required properties:
> >  		dr_mode = "peripheral";
> >  		interrupts = <0 134 0>;
> >  		usb-phy = <&usb_otg>;
> > -	};
> > \ No newline at end of file
> > +	};
> > +
> > +USB PHY with optional OTG:
> > +
> > +Required properties:
> > +- compatible:	should contain "qcom,usb-otg-ci" for chipsets with
> > +				Chipidea 45nm PHY or "qcom,usb-otg-snps" for chipsets
> > +				with Synopsys 28nm PHY
> 
> To make this easier to read and extend in future, I'd reorganise this
> like so:
> 
> compatible: should contain:
>  * "qcom,usb-otg-ci" for chipsets with Chipidea 45nm PHY
>  * "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY


Ok.

> 
> > +- regs:			offset and length of the register set in the memory map
> > +- interrupts:	interrupt-specifier for the OTG interrupt.
> > +
> > +- clocks:		A list of phandle + clock-specifier pairs for the
> > +				clocks listed in clock-names
> > +- clock-names:	Should contain the following:
> > +  "phy"			USB PHY reference clock
> > +  "core"		Protocol engine clock
> > +  "iface"		Interface bus clock
> > +  "alt_core"	Optional: Protocol engine clock for targets with asynchronous
> > +				reset methodology.
> 
> I'd rearrange that last entry:
> 
> "alt_core": Protocol engine clock for targets with asynchronous
>             reset methodology. (optional)

ok.

> 
> > +
> > +- dr_mode:		One of "host", "peripheral" or "otg". Defaults to "otg"
> 
> If this has a default and thus isn't required, it should be listed as
> optional.

This is part of the standard USB bindings, Perhaps I could just
refer to:  Documentation/devicetree/bindings/usb/generic.txt


> 
> > +
> > +- vdccx-supply:	phandle to the regulator for the vdd supply for
> > +				digital circuit operation.
> > +- v1p8-supply:	phandle to the regulator for the 1.8V supply
> > +- v3p3-supply:	phandle to the regulator for the 3.3V supply
> > +
> > +- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
> > +				1 - PHY control
> > +				2 - PMIC control
> > +				3 - User control (via debugfs)
> 
> NAK. This does not seem like a description of the hardware, and given
> the debugfs comment is fundamentally tied to the way Linux functions
> today.

I will remove option 3, but rest are really property of the chipset. 

> 
> > +
> > +Optional properties:
> > +- qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
> > +				terminate with -1
> 
> What is this? I'm really not keen on having arbitrary register/memory
> poking sequences in the dt.

This is related Device Mode Eye Diagram test and values used could be
different between chipsets.

> 
> Why does it need to be terminated? Surely the size of the property tells
> you that it's terminated.

Yes. -1 termination could be done in driver.

> 
> > +
> > +Example HSUSB OTG controller device node:
> > +
> > +	usb@f9a55000 {
> > +		compatible = "qcom,usb-otg-snps";
> > +		reg = <0xf9a55000 0x400>;
> > +		interrupts = <0 134 0>;;
> 
> s/;;/;/

thanks

> 
> > +		dr_mode = "peripheral";
> > +
> > +		clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
> > +				<&gcc GCC_USB_HS_AHB_CLK>;
> > +
> > +		clock-names = "phy", "core", "iface";
> > +
> > +		vddcx-supply = <&pm8841_s2_corner>;
> > +		v1p8-supply = <&pm8941_l6>;
> > +		v3p3-supply = <&pm8941_l24>;
> > +
> > +		qcom,otg-control = <1>;
> > +		qcom,phy-init-sequence = <0x01 0x90 0xffffffff>;
> 
> I believe modern dtc versions can handle negative numbers directly.
> 
> [...]
> 
> > +static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
> > +{
> > +	struct msm_otg_platform_data *pdata;
> > +	const struct of_device_id *id;
> > +	struct device_node *node = pdev->dev.of_node;
> > +	int len = 0;
> > +	u32 val;
> > +
> > +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> > +	if (!pdata)
> > +		return -ENOMEM;
> > +
> > +	motg->pdata = pdata;
> > +
> > +	id = of_match_device(msm_otg_dt_match, &pdev->dev);
> > +	pdata->phy_type = (int) id->data;
> > +
> > +	pdata->mode = of_usb_get_dr_mode(node);
> > +	if (pdata->mode == USB_DR_MODE_UNKNOWN)
> > +		pdata->mode = USB_DR_MODE_OTG;
> > +
> > +	pdata->otg_control = OTG_PHY_CONTROL;
> > +	if (!of_property_read_u32(node, "qcom,otg-control", &val))
> > +		pdata->otg_control = val;
> 
> Is this validated elsewhere?

No. I will add check.

Thanks.
Ivan

> 
> Thanks,
> Mark.

Re: [PATCH v4 12/15] usb: phy: msm: Add support for secondary PHY control

[Ivan T. Ivanov]

Hi Mark,

On Fri, 2013-11-15 at 16:42 +0000, Mark Rutland wrote: 
> On Tue, Nov 12, 2013 at 02:51:47PM +0000, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > 
> > Allow support to use 2nd HSPHY with USB2 Core.
> > Some platforms may have configuration to allow USB controller
> > work with any of the two HSPHYs present. By default driver
> > configures USB core to use primary HSPHY. Add support to allow
> > user select 2nd HSPHY using DT parameter.
> > 
> > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > Cc: Manu Gautam <mgautam@codeaurora.org>
> > Cc: devicetree@vger.kernel.org
> > ---
> >  .../devicetree/bindings/usb/msm-hsusb.txt          |    6 +++++
> >  drivers/usb/phy/phy-msm-usb.c                      |   24 ++++++++++++++++++--
> >  include/linux/usb/msm_hsusb.h                      |    1 +
> >  include/linux/usb/msm_hsusb_hw.h                   |    1 +
> >  4 files changed, 30 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > index 3f21204..d105ba9 100644
> > --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > @@ -72,6 +72,12 @@ Optional properties:
> >  - qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
> >  				terminate with -1
> >  
> > +- qcom,phy-num:	Select number of pyco-phy to use, can be one of
> > +				0 - PHY one, default
> > +				1 - Second PHY
> > +				Some platforms may have configuration to allow USB
> > +				controller work with any of the two HSPHYs present.
> > +
> 
> Only one can be used at a time?

Yes only one of them. Selected at driver init time. 

> 
> [...]
> 
> > @@ -1395,6 +1412,9 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
> >  	if (!of_property_read_u32(node, "qcom,otg-control", &val))
> >  		pdata->otg_control = val;
> >  
> > +	if (!of_property_read_u32(node, "qcom,phy-num", &val))
> > +		motg->phy_number = val;
> 
> No sanity checking? If not all of your tests on the value of
> motg->phy_number are the same form, you may get undepected results...


All checks are the same, but will add explicit check.

Thanks, 
Ivan 

> 
> Mark.

Re: [PATCH v4 10/15] usb: phy: msm: Add device tree support and binding information

[Mark Rutland]

On Mon, Nov 18, 2013 at 12:54:37PM +0000, Ivan T. Ivanov wrote:
> Hi Mark, 
> 
> On Fri, 2013-11-15 at 16:38 +0000, Mark Rutland wrote: 
> > On Tue, Nov 12, 2013 at 02:51:45PM +0000, Ivan T. Ivanov wrote:
> > > From: "Ivan T. Ivanov" <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
> > > 
> > > Allows MSM OTG controller to be specified via device tree.
> > > 
> > > Signed-off-by: Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
> > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > > ---
> > >  .../devicetree/bindings/usb/msm-hsusb.txt          |   57 +++++++++++++-
> > >  drivers/usb/phy/phy-msm-usb.c                      |   79 +++++++++++++++++---
> > >  2 files changed, 124 insertions(+), 12 deletions(-)

[...]

> > > +
> > > +- dr_mode:		One of "host", "peripheral" or "otg". Defaults to "otg"
> > 
> > If this has a default and thus isn't required, it should be listed as
> > optional.
> 
> This is part of the standard USB bindings, Perhaps I could just
> refer to:  Documentation/devicetree/bindings/usb/generic.txt

That would be fine, but it should also be moved to the optional
properties section.

> 
> 
> > 
> > > +
> > > +- vdccx-supply:	phandle to the regulator for the vdd supply for
> > > +				digital circuit operation.
> > > +- v1p8-supply:	phandle to the regulator for the 1.8V supply
> > > +- v3p3-supply:	phandle to the regulator for the 3.3V supply
> > > +
> > > +- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
> > > +				1 - PHY control
> > > +				2 - PMIC control
> > > +				3 - User control (via debugfs)
> > 
> > NAK. This does not seem like a description of the hardware, and given
> > the debugfs comment is fundamentally tied to the way Linux functions
> > today.
> 
> I will remove option 3, but rest are really property of the chipset. 

Can you elaborate on the diffence please?

> 
> > 
> > > +
> > > +Optional properties:
> > > +- qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
> > > +				terminate with -1
> > 
> > What is this? I'm really not keen on having arbitrary register/memory
> > poking sequences in the dt.
> 
> This is related Device Mode Eye Diagram test and values used could be
> different between chipsets.

Ok. Then we should encode the tuning data rather than adding a mechanism
to allow for writes to arbitrary addresses.

> 
> > 
> > Why does it need to be terminated? Surely the size of the property tells
> > you that it's terminated.
> 
> Yes. -1 termination could be done in driver.

Please do. There's no need for it to be in the DT.

Cheers,
Mark.
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Re: [PATCH v4 12/15] usb: phy: msm: Add support for secondary PHY control

[Mark Rutland]

On Mon, Nov 18, 2013 at 12:57:42PM +0000, Ivan T. Ivanov wrote:
> 
> Hi Mark,
> 
> On Fri, 2013-11-15 at 16:42 +0000, Mark Rutland wrote: 
> > On Tue, Nov 12, 2013 at 02:51:47PM +0000, Ivan T. Ivanov wrote:
> > > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > > 
> > > Allow support to use 2nd HSPHY with USB2 Core.
> > > Some platforms may have configuration to allow USB controller
> > > work with any of the two HSPHYs present. By default driver
> > > configures USB core to use primary HSPHY. Add support to allow
> > > user select 2nd HSPHY using DT parameter.
> > > 
> > > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > > Cc: Manu Gautam <mgautam@codeaurora.org>
> > > Cc: devicetree@vger.kernel.org
> > > ---
> > >  .../devicetree/bindings/usb/msm-hsusb.txt          |    6 +++++
> > >  drivers/usb/phy/phy-msm-usb.c                      |   24 ++++++++++++++++++--
> > >  include/linux/usb/msm_hsusb.h                      |    1 +
> > >  include/linux/usb/msm_hsusb_hw.h                   |    1 +
> > >  4 files changed, 30 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > > index 3f21204..d105ba9 100644
> > > --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > > +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > > @@ -72,6 +72,12 @@ Optional properties:
> > >  - qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
> > >  				terminate with -1
> > >  
> > > +- qcom,phy-num:	Select number of pyco-phy to use, can be one of
> > > +				0 - PHY one, default
> > > +				1 - Second PHY
> > > +				Some platforms may have configuration to allow USB
> > > +				controller work with any of the two HSPHYs present.
> > > +
> > 
> > Only one can be used at a time?
> 
> Yes only one of them. Selected at driver init time. 

Ok. For a given platform, is it likely that both are wired up and
_possibly_ usable?

Thanks
Mark.

Re: [PATCH v4 12/15] usb: phy: msm: Add support for secondary PHY control

[Ivan T. Ivanov]

Hi, 

On Thu, 2013-12-05 at 10:42 +0000, Mark Rutland wrote: 
> On Mon, Nov 18, 2013 at 12:57:42PM +0000, Ivan T. Ivanov wrote:
> > 
> > Hi Mark,
> > 
> > On Fri, 2013-11-15 at 16:42 +0000, Mark Rutland wrote: 
> > > On Tue, Nov 12, 2013 at 02:51:47PM +0000, Ivan T. Ivanov wrote:
> > > > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > > > 
> > > > Allow support to use 2nd HSPHY with USB2 Core.
> > > > Some platforms may have configuration to allow USB controller
> > > > work with any of the two HSPHYs present. By default driver
> > > > configures USB core to use primary HSPHY. Add support to allow
> > > > user select 2nd HSPHY using DT parameter.
> > > > 
> > > > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > > > Cc: Manu Gautam <mgautam@codeaurora.org>
> > > > Cc: devicetree@vger.kernel.org
> > > > ---
> > > >  .../devicetree/bindings/usb/msm-hsusb.txt          |    6 +++++
> > > >  drivers/usb/phy/phy-msm-usb.c                      |   24 ++++++++++++++++++--
> > > >  include/linux/usb/msm_hsusb.h                      |    1 +
> > > >  include/linux/usb/msm_hsusb_hw.h                   |    1 +
> > > >  4 files changed, 30 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > > > index 3f21204..d105ba9 100644
> > > > --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > > > +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
> > > > @@ -72,6 +72,12 @@ Optional properties:
> > > >  - qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
> > > >  				terminate with -1
> > > >  
> > > > +- qcom,phy-num:	Select number of pyco-phy to use, can be one of
> > > > +				0 - PHY one, default
> > > > +				1 - Second PHY
> > > > +				Some platforms may have configuration to allow USB
> > > > +				controller work with any of the two HSPHYs present.
> > > > +
> > > 
> > > Only one can be used at a time?
> > 
> > Yes only one of them. Selected at driver init time. 
> 
> Ok. For a given platform, is it likely that both are wired up and
> _possibly_ usable?


My guess is that this is possible :-) Regards. Ivan

> 
> Thanks
> Mark.

Re: [PATCH v4 10/15] usb: phy: msm: Add device tree support and binding information

[Ivan T. Ivanov]

Hi, 

On Thu, 2013-12-05 at 10:41 +0000, Mark Rutland wrote: 
> On Mon, Nov 18, 2013 at 12:54:37PM +0000, Ivan T. Ivanov wrote:
> > Hi Mark, 
> > 
> > On Fri, 2013-11-15 at 16:38 +0000, Mark Rutland wrote: 
> > > On Tue, Nov 12, 2013 at 02:51:45PM +0000, Ivan T. Ivanov wrote:
> > > > From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
> > > > 
> > > > Allows MSM OTG controller to be specified via device tree.
> > > > 
> > > > Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
> > > > Cc: devicetree@vger.kernel.org
> > > > ---
> > > >  .../devicetree/bindings/usb/msm-hsusb.txt          |   57 +++++++++++++-
> > > >  drivers/usb/phy/phy-msm-usb.c                      |   79 +++++++++++++++++---
> > > >  2 files changed, 124 insertions(+), 12 deletions(-)
> 
> [...]
> 
> > > > +
> > > > +- dr_mode:		One of "host", "peripheral" or "otg". Defaults to "otg"
> > > 
> > > If this has a default and thus isn't required, it should be listed as
> > > optional.
> > 
> > This is part of the standard USB bindings, Perhaps I could just
> > refer to:  Documentation/devicetree/bindings/usb/generic.txt
> 
> That would be fine, but it should also be moved to the optional
> properties section.

Ok.

> 
> > 
> > 
> > > 
> > > > +
> > > > +- vdccx-supply:	phandle to the regulator for the vdd supply for
> > > > +				digital circuit operation.
> > > > +- v1p8-supply:	phandle to the regulator for the 1.8V supply
> > > > +- v3p3-supply:	phandle to the regulator for the 3.3V supply
> > > > +
> > > > +- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
> > > > +				1 - PHY control
> > > > +				2 - PMIC control
> > > > +				3 - User control (via debugfs)
> > > 
> > > NAK. This does not seem like a description of the hardware, and given
> > > the debugfs comment is fundamentally tied to the way Linux functions
> > > today.
> > 
> > I will remove option 3, but rest are really property of the chipset. 
> 
> Can you elaborate on the diffence please?

Difference is how VBUS, ID changes, Accessory and Charger
detection is handled. In older chips-sets they are handled
by PHY controller, while now they are handled by external
PMIC logic.

> 
> > 
> > > 
> > > > +
> > > > +Optional properties:
> > > > +- qcom,phy-init-sequence: PHY configuration sequence. val, reg pairs
> > > > +				terminate with -1
> > > 
> > > What is this? I'm really not keen on having arbitrary register/memory
> > > poking sequences in the dt.
> > 
> > This is related Device Mode Eye Diagram test and values used could be
> > different between chipsets.
> 
> Ok. Then we should encode the tuning data rather than adding a mechanism
> to allow for writes to arbitrary addresses.

Currently: 

for msm8226 sequence is < 0x44 0x80 0x68 0x81 0x24 0x82 0x13 0x83 >
for msm8974 sequence is < 0x63 0x81 >

I could reserve -1 as "do not program" value and document that 
values in this array will be written to ULPI interface with
ULPI_EXT_VENDOR_SPECIFIC as base address.

for msm8974 sequence will be < -1 0x63 >

> 
> > 
> > > 
> > > Why does it need to be terminated? Surely the size of the property tells
> > > you that it's terminated.
> > 
> > Yes. -1 termination could be done in driver.
> 
> Please do. There's no need for it to be in the DT.


Thanks. Ivan

> 
> Cheers,
> Mark.
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