[PATCH 1/4] Phy: DT binding documentation for Marvell MVEBU SATA phy.

[PATCH 1/4] Phy: DT binding documentation for Marvell MVEBU SATA phy.

[Andrew Lunn]

Describe the binding for the Marvell MVEBU SATA phy. This driver
can be used at least with Kirkwood, Dove and maybe others.
Additionally, update the SATA binding with the properties to link
to the phy nodes.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v1->v2:
Correct #phy-cells
Correct number after @ to match first reg address.
Rename to phy-mvebu.txt

v2->v3:
Renamed to mvebu-phy.txt
Use "port0", "port1" instead of "0", "1"
---
 Documentation/devicetree/bindings/ata/marvell.txt  |  6 ++++++
 .../devicetree/bindings/phy/mvebu-phy.txt          | 22 ++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mvebu-phy.txt

diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
index b5cdd20cde9c..4c5447f1068d 100644
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -6,11 +6,17 @@ Required Properties:
 - interrupts    : Interrupt controller is using
 - nr-ports      : Number of SATA ports in use.
 
+Optional Properties:
+- phys		: List of phandles to sata phys
+- phy-names	: Should be "port0", "port1", etc, one per phandle
+
 Example:
 
 	sata@80000 {
 		compatible = "marvell,orion-sata";
 		reg = <0x80000 0x5000>;
 		interrupts = <21>;
+		phys = <&sata_phy0>, <&sata_phy1>;
+		phy-names = "port0", "port1";
 		nr-ports = <2>;
 	}
diff --git a/Documentation/devicetree/bindings/phy/mvebu-phy.txt b/Documentation/devicetree/bindings/phy/mvebu-phy.txt
new file mode 100644
index 000000000000..6cb3364aeafb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mvebu-phy.txt
@@ -0,0 +1,22 @@
+* Marvell MVEBU SATA PHY
+
+Power control for the SATA phy found on Marvell MVEBU SoCs.
+
+This document extends the binding described in phy-bindings.txt
+
+Required properties :
+
+ - reg		   : Offset and length of the register set for the SATA device
+ - compatible	   : Should be "marvell,mvebu-sata-phy"
+ - clocks	   : phandle of clock and specifier that supplies the device
+ - clock-names	   : Should be "sata"
+
+Example:
+		sata-phy@84000 {
+			compatible = "marvell,mvebu-sata-phy";
+			reg = <0x84000 0x0334>;
+			clocks = <&gate_clk 15>;
+			clock-names = "sata";
+			#phy-cells = <0>;
+			status = "ok";
+		};
-- 
1.8.5.1

[PATCH 2/4] Phy: Add a PHY driver for Marvell MVEBU SATA PHY.

[Andrew Lunn]

Kirkwood and Dove can turn the SATA phy on and off. Add a PHY driver
to control this.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v1->v2:
Use #defines instead of magic values
select GENERIC_PHY in Kconfig.
---
 drivers/phy/Kconfig          |   6 ++
 drivers/phy/Makefile         |   1 +
 drivers/phy/phy-mvebu-sata.c | 137 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 144 insertions(+)
 create mode 100644 drivers/phy/phy-mvebu-sata.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d52361..7464d31fcbd1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -21,6 +21,12 @@ config PHY_EXYNOS_MIPI_VIDEO
 	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
 	  and EXYNOS SoCs.
 
+config PHY_MVEBU_SATA
+	def_bool y
+	depends on ARCH_KIRKWOOD || ARCH_DOVE
+	depends on OF
+	select GENERIC_PHY
+
 config OMAP_USB2
 	tristate "OMAP USB2 PHY Driver"
 	depends on ARCH_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9cfb83..4e4adc96f753 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,5 +5,6 @@
 obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
diff --git a/drivers/phy/phy-mvebu-sata.c b/drivers/phy/phy-mvebu-sata.c
new file mode 100644
index 000000000000..d43786f62437
--- /dev/null
+++ b/drivers/phy/phy-mvebu-sata.c
@@ -0,0 +1,137 @@
+/*
+ *	phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
+ *
+ *	Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+struct priv {
+	struct clk	*clk;
+	void __iomem	*base;
+};
+
+#define SATA_PHY_MODE_2	0x0330
+#define  MODE_2_FORCE_PU_TX	BIT(0)
+#define  MODE_2_FORCE_PU_RX	BIT(1)
+#define  MODE_2_PU_PLL		BIT(2)
+#define  MODE_2_PU_IVREF	BIT(3)
+#define SATA_IF_CTRL	0x0050
+#define  CTRL_PHY_SHUTDOWN	BIT(9)
+
+static int phy_mvebu_sata_power_on(struct phy *phy)
+{
+	struct priv *priv = phy_get_drvdata(phy);
+	u32 reg;
+
+	clk_prepare_enable(priv->clk);
+
+	/* Enable PLL and IVREF */
+	reg = readl(priv->base + SATA_PHY_MODE_2);
+	reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
+		MODE_2_PU_PLL | MODE_2_PU_IVREF);
+	writel(reg , priv->base + SATA_PHY_MODE_2);
+
+	/* Enable PHY */
+	reg = readl(priv->base + SATA_IF_CTRL);
+	reg &= ~CTRL_PHY_SHUTDOWN;
+	writel(reg, priv->base + SATA_IF_CTRL);
+
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static int phy_mvebu_sata_power_off(struct phy *phy)
+{
+	struct priv *priv = phy_get_drvdata(phy);
+	u32 reg;
+
+	clk_prepare_enable(priv->clk);
+
+	/* Disable PLL and IVREF */
+	reg = readl(priv->base + SATA_PHY_MODE_2);
+	reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
+		 MODE_2_PU_PLL | MODE_2_PU_IVREF);
+	writel(reg, priv->base + SATA_PHY_MODE_2);
+
+	/* Disable PHY */
+	reg = readl(priv->base + SATA_IF_CTRL);
+	reg |= CTRL_PHY_SHUTDOWN;
+	writel(reg, priv->base + SATA_IF_CTRL);
+
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static struct phy_ops phy_mvebu_sata_ops = {
+	.power_on	= phy_mvebu_sata_power_on,
+	.power_off	= phy_mvebu_sata_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int phy_mvebu_sata_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct resource *res;
+	struct priv *priv;
+	struct phy *phy;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->clk = devm_clk_get(&pdev->dev, "sata");
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
+	phy_provider = devm_of_phy_provider_register(&pdev->dev,
+						     of_phy_simple_xlate);
+	if (IS_ERR(phy_provider))
+		return PTR_ERR(phy_provider);
+
+	phy = devm_phy_create(&pdev->dev, &phy_mvebu_sata_ops, NULL);
+	if (IS_ERR(phy))
+		return PTR_ERR(phy);
+
+	phy_set_drvdata(phy, priv);
+
+	/* The boot loader may of left it on. Turn it off. */
+	phy_mvebu_sata_power_off(phy);
+
+	return 0;
+}
+
+static const struct of_device_id phy_mvebu_sata_of_match[] = {
+	{ .compatible = "marvell,mvebu-sata-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, phy_mvebu_sata_of_match);
+
+static struct platform_driver phy_mvebu_sata_driver = {
+	.probe	= phy_mvebu_sata_probe,
+	.driver = {
+		.name	= "phy-mvebu-sata",
+		.owner	= THIS_MODULE,
+		.of_match_table	= phy_mvebu_sata_of_match,
+	}
+};
+module_platform_driver(phy_mvebu_sata_driver);
+
+MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
+MODULE_DESCRIPTION("Marvell MVEBU SATA PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.5.1

[PATCH 3/4] SATA: MV: Add support for the optional PHYs

[Andrew Lunn]

Some Marvell SoCs have a SATA PHY which can be powered off, in order
to save power. Make use of the generic phy framework to control these
phys.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v2->v3
Look for phys using name "port0", "port1", etc.
---
 drivers/ata/sata_mv.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 56be31819897..896725bb5e34 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -60,6 +60,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
 #include <linux/clk.h>
+#include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/mbus.h>
@@ -563,6 +564,12 @@ struct mv_host_priv {
 	struct clk		*clk;
 	struct clk              **port_clks;
 	/*
+	 * Some devices have a SATA PHY which can be enabled/disabled
+	 * in order to save power. These are optional: if the platform
+	 * devices does not have any phy, they won't be used.
+	 */
+	struct phy		**port_phys;
+	/*
 	 * These consistent DMA memory pools give us guaranteed
 	 * alignment for hardware-accessed data structures,
 	 * and less memory waste in accomplishing the alignment.
@@ -4076,6 +4083,11 @@ static int mv_platform_probe(struct platform_device *pdev)
 					GFP_KERNEL);
 	if (!hpriv->port_clks)
 		return -ENOMEM;
+	hpriv->port_phys = devm_kzalloc(&pdev->dev,
+					sizeof(struct phy *) * n_ports,
+					GFP_KERNEL);
+	if (!hpriv->port_phys)
+		return -ENOMEM;
 	host->private_data = hpriv;
 	hpriv->n_ports = n_ports;
 	hpriv->board_idx = chip_soc;
@@ -4097,6 +4109,10 @@ static int mv_platform_probe(struct platform_device *pdev)
 		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
 		if (!IS_ERR(hpriv->port_clks[port]))
 			clk_prepare_enable(hpriv->port_clks[port]);
+		sprintf(port_number, "port%d", port);
+		hpriv->port_phys[port] = devm_phy_get(&pdev->dev, port_number);
+		if (!IS_ERR(hpriv->port_phys[port]))
+			phy_power_on(hpriv->port_phys[port]);
 	}
 
 	/*
@@ -4132,6 +4148,8 @@ err:
 			clk_disable_unprepare(hpriv->port_clks[port]);
 			clk_put(hpriv->port_clks[port]);
 		}
+		if (!IS_ERR(hpriv->port_phys[port]))
+			phy_power_off(hpriv->port_phys[port]);
 	}
 
 	return rc;
@@ -4161,6 +4179,8 @@ static int mv_platform_remove(struct platform_device *pdev)
 			clk_disable_unprepare(hpriv->port_clks[port]);
 			clk_put(hpriv->port_clks[port]);
 		}
+		if (!IS_ERR(hpriv->port_phys[port]))
+			phy_power_off(hpriv->port_phys[port]);
 	}
 	return 0;
 }
-- 
1.8.5.1

[PATCH 4/4] Phy: Add DT nodes on kirkwood and Dove for the SATA PHY

[Andrew Lunn]

Add nodes for the two SATA PHYs on kirkwood.
Add node for the one SATA PHY on Dove.
Add pHandles to the PHYs in the sata nodes.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v1->v2:
sata_phy@... ->sata-phy@
value after '@' matching the first address in the reg.

v2->v3:
"0" -> "port0", etc.
kirkewood -> kirkwood
---
 arch/arm/boot/dts/dove.dtsi          | 11 +++++++++++
 arch/arm/boot/dts/kirkwood-6281.dtsi |  2 ++
 arch/arm/boot/dts/kirkwood-6282.dtsi |  2 ++
 arch/arm/boot/dts/kirkwood.dtsi      | 18 ++++++++++++++++++
 4 files changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 113a8bc7bee7..198d03625832 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -490,10 +490,21 @@
 				reg = <0xa0000 0x2400>;
 				interrupts = <62>;
 				clocks = <&gate_clk 3>;
+				phys = <&sata_phy0>;
+				phy-names = "port0";
 				nr-ports = <1>;
 				status = "disabled";
 			};
 
+			sata_phy0: sata-phy@a2000 {
+				compatible = "marvell,mvebu-sata-phy";
+				reg = <0xa2000 0x0334>;
+				clocks = <&gate_clk 3>;
+				clock-names = "sata";
+				#phy-cells = <0>;
+				status = "ok";
+			};
+
 			rtc: real-time-clock@d8500 {
 				compatible = "marvell,orion-rtc";
 				reg = <0xd8500 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 650ef30e1856..18400e74e0de 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -89,6 +89,8 @@
 			interrupts = <21>;
 			clocks = <&gate_clk 14>, <&gate_clk 15>;
 			clock-names = "0", "1";
+			phys = <&sata_phy0>, <&sata_phy1>;
+			phy-names = "port0", "port1";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 3933a331ddc2..69c622bbbfb5 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -117,6 +117,8 @@
 			interrupts = <21>;
 			clocks = <&gate_clk 14>, <&gate_clk 15>;
 			clock-names = "0", "1";
+			phys = <&sata_phy0>, <&sata_phy1>;
+			phy-names = "port0", "port1";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 8b73c80f1dad..ee06951721c4 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -282,5 +282,23 @@
 				/* set phy-handle property in board file */
 			};
 		};
+
+		sata_phy0: sata-phy@82000 {
+			compatible = "marvell,mvebu-sata-phy";
+			reg = <0x82000 0x0334>;
+			clocks = <&gate_clk 14>;
+			clock-names = "sata";
+			#phy-cells = <0>;
+			status = "ok";
+		};
+
+		sata_phy1: sata-phy@84000 {
+			compatible = "marvell,mvebu-sata-phy";
+			reg = <0x84000 0x0334>;
+			clocks = <&gate_clk 15>;
+			clock-names = "sata";
+			#phy-cells = <0>;
+			status = "ok";
+		};
 	};
 };
-- 
1.8.5.1

Re: [PATCH 1/4] Phy: DT binding documentation for Marvell MVEBU SATA phy.

[Andrew Lunn]

Hi Folks

Sorry, forgot the --subject. This is version 3 of the patchset.

       Andrew


On Tue, Dec 17, 2013 at 09:21:49PM +0100, Andrew Lunn wrote:
> Describe the binding for the Marvell MVEBU SATA phy. This driver
> can be used at least with Kirkwood, Dove and maybe others.
> Additionally, update the SATA binding with the properties to link
> to the phy nodes.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> v1->v2:
> Correct #phy-cells
> Correct number after @ to match first reg address.
> Rename to phy-mvebu.txt
> 
> v2->v3:
> Renamed to mvebu-phy.txt
> Use "port0", "port1" instead of "0", "1"
> ---
>  Documentation/devicetree/bindings/ata/marvell.txt  |  6 ++++++
>  .../devicetree/bindings/phy/mvebu-phy.txt          | 22 ++++++++++++++++++++++
>  2 files changed, 28 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/mvebu-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
> index b5cdd20cde9c..4c5447f1068d 100644
> --- a/Documentation/devicetree/bindings/ata/marvell.txt
> +++ b/Documentation/devicetree/bindings/ata/marvell.txt
> @@ -6,11 +6,17 @@ Required Properties:
>  - interrupts    : Interrupt controller is using
>  - nr-ports      : Number of SATA ports in use.
>  
> +Optional Properties:
> +- phys		: List of phandles to sata phys
> +- phy-names	: Should be "port0", "port1", etc, one per phandle
> +
>  Example:
>  
>  	sata@80000 {
>  		compatible = "marvell,orion-sata";
>  		reg = <0x80000 0x5000>;
>  		interrupts = <21>;
> +		phys = <&sata_phy0>, <&sata_phy1>;
> +		phy-names = "port0", "port1";
>  		nr-ports = <2>;
>  	}
> diff --git a/Documentation/devicetree/bindings/phy/mvebu-phy.txt b/Documentation/devicetree/bindings/phy/mvebu-phy.txt
> new file mode 100644
> index 000000000000..6cb3364aeafb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mvebu-phy.txt
> @@ -0,0 +1,22 @@
> +* Marvell MVEBU SATA PHY
> +
> +Power control for the SATA phy found on Marvell MVEBU SoCs.
> +
> +This document extends the binding described in phy-bindings.txt
> +
> +Required properties :
> +
> + - reg		   : Offset and length of the register set for the SATA device
> + - compatible	   : Should be "marvell,mvebu-sata-phy"
> + - clocks	   : phandle of clock and specifier that supplies the device
> + - clock-names	   : Should be "sata"
> +
> +Example:
> +		sata-phy@84000 {
> +			compatible = "marvell,mvebu-sata-phy";
> +			reg = <0x84000 0x0334>;
> +			clocks = <&gate_clk 15>;
> +			clock-names = "sata";
> +			#phy-cells = <0>;
> +			status = "ok";
> +		};
> -- 
> 1.8.5.1
> 

Re: [PATCH 3/4] SATA: MV: Add support for the optional PHYs

[Kishon Vijay Abraham I]

Hi Tejun,

On Wednesday 18 December 2013 01:51 AM, Andrew Lunn wrote:
> Some Marvell SoCs have a SATA PHY which can be powered off, in order
> to save power. Make use of the generic phy framework to control these
> phys.

I can queue this patch along with the other patches in this series if you don't
expect any merge issues. If you want to take this patch by yourself, you can add my
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Either ways let me know.

Cheers
Kishon

> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> v2->v3
> Look for phys using name "port0", "port1", etc.
> ---
>  drivers/ata/sata_mv.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
> index 56be31819897..896725bb5e34 100644
> --- a/drivers/ata/sata_mv.c
> +++ b/drivers/ata/sata_mv.c
> @@ -60,6 +60,7 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/device.h>
>  #include <linux/clk.h>
> +#include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/ata_platform.h>
>  #include <linux/mbus.h>
> @@ -563,6 +564,12 @@ struct mv_host_priv {
>  	struct clk		*clk;
>  	struct clk              **port_clks;
>  	/*
> +	 * Some devices have a SATA PHY which can be enabled/disabled
> +	 * in order to save power. These are optional: if the platform
> +	 * devices does not have any phy, they won't be used.
> +	 */
> +	struct phy		**port_phys;
> +	/*
>  	 * These consistent DMA memory pools give us guaranteed
>  	 * alignment for hardware-accessed data structures,
>  	 * and less memory waste in accomplishing the alignment.
> @@ -4076,6 +4083,11 @@ static int mv_platform_probe(struct platform_device *pdev)
>  					GFP_KERNEL);
>  	if (!hpriv->port_clks)
>  		return -ENOMEM;
> +	hpriv->port_phys = devm_kzalloc(&pdev->dev,
> +					sizeof(struct phy *) * n_ports,
> +					GFP_KERNEL);
> +	if (!hpriv->port_phys)
> +		return -ENOMEM;
>  	host->private_data = hpriv;
>  	hpriv->n_ports = n_ports;
>  	hpriv->board_idx = chip_soc;
> @@ -4097,6 +4109,10 @@ static int mv_platform_probe(struct platform_device *pdev)
>  		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
>  		if (!IS_ERR(hpriv->port_clks[port]))
>  			clk_prepare_enable(hpriv->port_clks[port]);
> +		sprintf(port_number, "port%d", port);
> +		hpriv->port_phys[port] = devm_phy_get(&pdev->dev, port_number);
> +		if (!IS_ERR(hpriv->port_phys[port]))
> +			phy_power_on(hpriv->port_phys[port]);
>  	}
>  
>  	/*
> @@ -4132,6 +4148,8 @@ err:
>  			clk_disable_unprepare(hpriv->port_clks[port]);
>  			clk_put(hpriv->port_clks[port]);
>  		}
> +		if (!IS_ERR(hpriv->port_phys[port]))
> +			phy_power_off(hpriv->port_phys[port]);
>  	}
>  
>  	return rc;
> @@ -4161,6 +4179,8 @@ static int mv_platform_remove(struct platform_device *pdev)
>  			clk_disable_unprepare(hpriv->port_clks[port]);
>  			clk_put(hpriv->port_clks[port]);
>  		}
> +		if (!IS_ERR(hpriv->port_phys[port]))
> +			phy_power_off(hpriv->port_phys[port]);
>  	}
>  	return 0;
>  }
> 

Re: [PATCH 4/4] Phy: Add DT nodes on kirkwood and Dove for the SATA PHY

[Kishon Vijay Abraham I]

On Wednesday 18 December 2013 01:51 AM, Andrew Lunn wrote:
> Add nodes for the two SATA PHYs on kirkwood.
> Add node for the one SATA PHY on Dove.
> Add pHandles to the PHYs in the sata nodes.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> v1->v2:
> sata_phy@... ->sata-phy@
> value after '@' matching the first address in the reg.
> 
> v2->v3:
> "0" -> "port0", etc.
> kirkewood -> kirkwood
> ---
>  arch/arm/boot/dts/dove.dtsi          | 11 +++++++++++
>  arch/arm/boot/dts/kirkwood-6281.dtsi |  2 ++
>  arch/arm/boot/dts/kirkwood-6282.dtsi |  2 ++
>  arch/arm/boot/dts/kirkwood.dtsi      | 18 ++++++++++++++++++
>  4 files changed, 33 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
> index 113a8bc7bee7..198d03625832 100644
> --- a/arch/arm/boot/dts/dove.dtsi
> +++ b/arch/arm/boot/dts/dove.dtsi
> @@ -490,10 +490,21 @@
>  				reg = <0xa0000 0x2400>;
>  				interrupts = <62>;
>  				clocks = <&gate_clk 3>;
> +				phys = <&sata_phy0>;
> +				phy-names = "port0";
>  				nr-ports = <1>;
>  				status = "disabled";
>  			};
>  
> +			sata_phy0: sata-phy@a2000 {
> +				compatible = "marvell,mvebu-sata-phy";
> +				reg = <0xa2000 0x0334>;
> +				clocks = <&gate_clk 3>;
> +				clock-names = "sata";
> +				#phy-cells = <0>;
> +				status = "ok";
> +			};
> +
>  			rtc: real-time-clock@d8500 {
>  				compatible = "marvell,orion-rtc";
>  				reg = <0xd8500 0x20>;
> diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
> index 650ef30e1856..18400e74e0de 100644
> --- a/arch/arm/boot/dts/kirkwood-6281.dtsi
> +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
> @@ -89,6 +89,8 @@
>  			interrupts = <21>;
>  			clocks = <&gate_clk 14>, <&gate_clk 15>;
>  			clock-names = "0", "1";
> +			phys = <&sata_phy0>, <&sata_phy1>;
> +			phy-names = "port0", "port1";
>  			status = "disabled";
>  		};
>  
> diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
> index 3933a331ddc2..69c622bbbfb5 100644
> --- a/arch/arm/boot/dts/kirkwood-6282.dtsi
> +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
> @@ -117,6 +117,8 @@
>  			interrupts = <21>;
>  			clocks = <&gate_clk 14>, <&gate_clk 15>;
>  			clock-names = "0", "1";
> +			phys = <&sata_phy0>, <&sata_phy1>;
> +			phy-names = "port0", "port1";
>  			status = "disabled";
>  		};
>  
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index 8b73c80f1dad..ee06951721c4 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -282,5 +282,23 @@
>  				/* set phy-handle property in board file */
>  			};
>  		};
> +
> +		sata_phy0: sata-phy@82000 {
> +			compatible = "marvell,mvebu-sata-phy";
> +			reg = <0x82000 0x0334>;
> +			clocks = <&gate_clk 14>;
> +			clock-names = "sata";
> +			#phy-cells = <0>;
> +			status = "ok";
> +		};
> +
> +		sata_phy1: sata-phy@84000 {
> +			compatible = "marvell,mvebu-sata-phy";
> +			reg = <0x84000 0x0334>;
> +			clocks = <&gate_clk 15>;
> +			clock-names = "sata";
> +			#phy-cells = <0>;
> +			status = "ok";
> +		};
>  	};
>  };
> 

Re: [PATCH 3/4] SATA: MV: Add support for the optional PHYs

[Tejun Heo]

Hello,

On Wed, Dec 18, 2013 at 12:00:10PM +0530, Kishon Vijay Abraham I wrote:
> > @@ -4097,6 +4109,10 @@ static int mv_platform_probe(struct platform_device *pdev)
> >  		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
> >  		if (!IS_ERR(hpriv->port_clks[port]))
> >  			clk_prepare_enable(hpriv->port_clks[port]);
> > +		sprintf(port_number, "port%d", port);
> > +		hpriv->port_phys[port] = devm_phy_get(&pdev->dev, port_number);
> > +		if (!IS_ERR(hpriv->port_phys[port]))
> > +			phy_power_on(hpriv->port_phys[port]);

Shouldn't it distinguish between failures and at least produce
warning?  ie. phy not available and phy init failed due to memory
pressure or whatnot shouldn't be handled the same.

> > @@ -4132,6 +4148,8 @@ err:
> >  			clk_disable_unprepare(hpriv->port_clks[port]);
> >  			clk_put(hpriv->port_clks[port]);
> >  		}
> > +		if (!IS_ERR(hpriv->port_phys[port]))
> > +			phy_power_off(hpriv->port_phys[port]);

And I'd much prefer the array holds either NULL or valid pointer.

Thanks.

-- 
tejun

Re: [PATCH 2/4] Phy: Add a PHY driver for Marvell MVEBU SATA PHY.

[Kishon Vijay Abraham I]

Hi,

On Wednesday 18 December 2013 01:51 AM, Andrew Lunn wrote:
> Kirkwood and Dove can turn the SATA phy on and off. Add a PHY driver
> to control this.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> v1->v2:
> Use #defines instead of magic values
> select GENERIC_PHY in Kconfig.
> ---
>  drivers/phy/Kconfig          |   6 ++
>  drivers/phy/Makefile         |   1 +
>  drivers/phy/phy-mvebu-sata.c | 137 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 144 insertions(+)
>  create mode 100644 drivers/phy/phy-mvebu-sata.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index a344f3d52361..7464d31fcbd1 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -21,6 +21,12 @@ config PHY_EXYNOS_MIPI_VIDEO
>  	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
>  	  and EXYNOS SoCs.
>  
> +config PHY_MVEBU_SATA
> +	def_bool y
> +	depends on ARCH_KIRKWOOD || ARCH_DOVE
> +	depends on OF
> +	select GENERIC_PHY
> +
>  config OMAP_USB2
>  	tristate "OMAP USB2 PHY Driver"
>  	depends on ARCH_OMAP2PLUS
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index d0caae9cfb83..4e4adc96f753 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -5,5 +5,6 @@
>  obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
>  obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
>  obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
> +obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> diff --git a/drivers/phy/phy-mvebu-sata.c b/drivers/phy/phy-mvebu-sata.c
> new file mode 100644
> index 000000000000..d43786f62437
> --- /dev/null
> +++ b/drivers/phy/phy-mvebu-sata.c
> @@ -0,0 +1,137 @@
> +/*
> + *	phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
> + *
> + *	Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
> + *
> + *	This program is free software; you can redistribute it and/or
> + *	modify it under the terms of the GNU General Public License
> + *	as published by the Free Software Foundation; either version
> + *	2 of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +struct priv {
> +	struct clk	*clk;
> +	void __iomem	*base;
> +};
> +
> +#define SATA_PHY_MODE_2	0x0330
> +#define  MODE_2_FORCE_PU_TX	BIT(0)
> +#define  MODE_2_FORCE_PU_RX	BIT(1)
> +#define  MODE_2_PU_PLL		BIT(2)
> +#define  MODE_2_PU_IVREF	BIT(3)
> +#define SATA_IF_CTRL	0x0050
> +#define  CTRL_PHY_SHUTDOWN	BIT(9)
> +
> +static int phy_mvebu_sata_power_on(struct phy *phy)
> +{
> +	struct priv *priv = phy_get_drvdata(phy);
> +	u32 reg;
> +
> +	clk_prepare_enable(priv->clk);
> +
> +	/* Enable PLL and IVREF */
> +	reg = readl(priv->base + SATA_PHY_MODE_2);
> +	reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
> +		MODE_2_PU_PLL | MODE_2_PU_IVREF);
> +	writel(reg , priv->base + SATA_PHY_MODE_2);
> +
> +	/* Enable PHY */
> +	reg = readl(priv->base + SATA_IF_CTRL);
> +	reg &= ~CTRL_PHY_SHUTDOWN;
> +	writel(reg, priv->base + SATA_IF_CTRL);
> +
> +	clk_disable_unprepare(priv->clk);
> +
> +	return 0;
> +}
> +
> +static int phy_mvebu_sata_power_off(struct phy *phy)
> +{
> +	struct priv *priv = phy_get_drvdata(phy);
> +	u32 reg;
> +
> +	clk_prepare_enable(priv->clk);
> +
> +	/* Disable PLL and IVREF */
> +	reg = readl(priv->base + SATA_PHY_MODE_2);
> +	reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
> +		 MODE_2_PU_PLL | MODE_2_PU_IVREF);
> +	writel(reg, priv->base + SATA_PHY_MODE_2);
> +
> +	/* Disable PHY */
> +	reg = readl(priv->base + SATA_IF_CTRL);
> +	reg |= CTRL_PHY_SHUTDOWN;
> +	writel(reg, priv->base + SATA_IF_CTRL);
> +
> +	clk_disable_unprepare(priv->clk);
> +
> +	return 0;
> +}
> +
> +static struct phy_ops phy_mvebu_sata_ops = {
> +	.power_on	= phy_mvebu_sata_power_on,
> +	.power_off	= phy_mvebu_sata_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int phy_mvebu_sata_probe(struct platform_device *pdev)
> +{
> +	struct phy_provider *phy_provider;
> +	struct resource *res;
> +	struct priv *priv;
> +	struct phy *phy;
> +
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	priv->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	priv->clk = devm_clk_get(&pdev->dev, "sata");
> +	if (IS_ERR(priv->clk))
> +		return PTR_ERR(priv->clk);
> +
> +	phy_provider = devm_of_phy_provider_register(&pdev->dev,
> +						     of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider))
> +		return PTR_ERR(phy_provider);
> +
> +	phy = devm_phy_create(&pdev->dev, &phy_mvebu_sata_ops, NULL);
> +	if (IS_ERR(phy))
> +		return PTR_ERR(phy);
> +
> +	phy_set_drvdata(phy, priv);

recently Felipe found a bug and phy_provider should be registered as the last
step. If you can fix that up, I can queue it.

Thanks
Kishon
> +
> +	/* The boot loader may of left it on. Turn it off. */
> +	phy_mvebu_sata_power_off(phy);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id phy_mvebu_sata_of_match[] = {
> +	{ .compatible = "marvell,mvebu-sata-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, phy_mvebu_sata_of_match);
> +
> +static struct platform_driver phy_mvebu_sata_driver = {
> +	.probe	= phy_mvebu_sata_probe,
> +	.driver = {
> +		.name	= "phy-mvebu-sata",
> +		.owner	= THIS_MODULE,
> +		.of_match_table	= phy_mvebu_sata_of_match,
> +	}
> +};
> +module_platform_driver(phy_mvebu_sata_driver);
> +
> +MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
> +MODULE_DESCRIPTION("Marvell MVEBU SATA PHY driver");
> +MODULE_LICENSE("GPL v2");
> 

Re: [PATCH 3/4] SATA: MV: Add support for the optional PHYs

[Andrew Lunn]

On Wed, Dec 18, 2013 at 12:00:10PM +0530, Kishon Vijay Abraham I wrote:
> Hi Tejun,
> 
> On Wednesday 18 December 2013 01:51 AM, Andrew Lunn wrote:
> > Some Marvell SoCs have a SATA PHY which can be powered off, in order
> > to save power. Make use of the generic phy framework to control these
> > phys.
> 
> I can queue this patch along with the other patches in this series if you don't
> expect any merge issues.

Hi Kishon

I expect merge issues with the DT and the DT binding documentation. It
would be best if Jason took those parts.

      Andrew
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Re: [PATCH 3/4] SATA: MV: Add support for the optional PHYs

[Andrew Lunn]

On Wed, Dec 18, 2013 at 07:13:13AM -0500, Tejun Heo wrote:
> Hello,
> 
> On Wed, Dec 18, 2013 at 12:00:10PM +0530, Kishon Vijay Abraham I wrote:
> > > @@ -4097,6 +4109,10 @@ static int mv_platform_probe(struct platform_device *pdev)
> > >  		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
> > >  		if (!IS_ERR(hpriv->port_clks[port]))
> > >  			clk_prepare_enable(hpriv->port_clks[port]);
> > > +		sprintf(port_number, "port%d", port);
> > > +		hpriv->port_phys[port] = devm_phy_get(&pdev->dev, port_number);
> > > +		if (!IS_ERR(hpriv->port_phys[port]))
> > > +			phy_power_on(hpriv->port_phys[port]);
> 
> Shouldn't it distinguish between failures and at least produce
> warning?  ie. phy not available and phy init failed due to memory
> pressure or whatnot shouldn't be handled the same.

Phy not available is not an error, since not all variants of the SATA
IP block have the ability to control the phy. I can however add a
warning for real errors.

> > > @@ -4132,6 +4148,8 @@ err:
> > >  			clk_disable_unprepare(hpriv->port_clks[port]);
> > >  			clk_put(hpriv->port_clks[port]);
> > >  		}
> > > +		if (!IS_ERR(hpriv->port_phys[port]))
> > > +			phy_power_off(hpriv->port_phys[port]);
> 
> And I'd much prefer the array holds either NULL or valid pointer.

I was trying to keep the code similar to the clk handling. However now
that it is diverging more and more from how clk is handled, i can add
yet more divergence and overwrite the error with a NULL.

    Andrew

Re: [PATCH 3/4] SATA: MV: Add support for the optional PHYs

[Tejun Heo]

Hello,

On Thu, Dec 19, 2013 at 08:10:27PM +0100, Andrew Lunn wrote:
> > Shouldn't it distinguish between failures and at least produce
> > warning?  ie. phy not available and phy init failed due to memory
> > pressure or whatnot shouldn't be handled the same.
> 
> Phy not available is not an error, since not all variants of the SATA
                          ^
			 always

> IP block have the ability to control the phy. I can however add a
> warning for real errors.

Yes, please.

> > > > @@ -4132,6 +4148,8 @@ err:
> > > >  			clk_disable_unprepare(hpriv->port_clks[port]);
> > > >  			clk_put(hpriv->port_clks[port]);
> > > >  		}
> > > > +		if (!IS_ERR(hpriv->port_phys[port]))
> > > > +			phy_power_off(hpriv->port_phys[port]);
> > 
> > And I'd much prefer the array holds either NULL or valid pointer.
> 
> I was trying to keep the code similar to the clk handling. However now
> that it is diverging more and more from how clk is handled, i can add
> yet more divergence and overwrite the error with a NULL.

Thanks.

-- 
tejun

Re: [PATCH 1/4] Phy: DT binding documentation for Marvell MVEBU SATA phy.

[Jason Cooper]

On Tue, Dec 17, 2013 at 09:21:49PM +0100, Andrew Lunn wrote:
> Describe the binding for the Marvell MVEBU SATA phy. This driver
> can be used at least with Kirkwood, Dove and maybe others.
> Additionally, update the SATA binding with the properties to link
> to the phy nodes.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> v1->v2:
> Correct #phy-cells
> Correct number after @ to match first reg address.
> Rename to phy-mvebu.txt
> 
> v2->v3:
> Renamed to mvebu-phy.txt
> Use "port0", "port1" instead of "0", "1"
> ---
>  Documentation/devicetree/bindings/ata/marvell.txt  |  6 ++++++
>  .../devicetree/bindings/phy/mvebu-phy.txt          | 22 ++++++++++++++++++++++
>  2 files changed, 28 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/mvebu-phy.txt

Acked-by: Jason Cooper <jason@lakedaemon.net>

thx,

Jason.

Re: [PATCH 3/4] SATA: MV: Add support for the optional PHYs

[Jason Cooper]

On Thu, Dec 19, 2013 at 08:03:29PM +0100, Andrew Lunn wrote:
> On Wed, Dec 18, 2013 at 12:00:10PM +0530, Kishon Vijay Abraham I wrote:
> > Hi Tejun,
> > 
> > On Wednesday 18 December 2013 01:51 AM, Andrew Lunn wrote:
> > > Some Marvell SoCs have a SATA PHY which can be powered off, in order
> > > to save power. Make use of the generic phy framework to control these
> > > phys.
> > 
> > I can queue this patch along with the other patches in this series if you don't
> > expect any merge issues.
> 
> Hi Kishon
> 
> I expect merge issues with the DT and the DT binding documentation. It
> would be best if Jason took those parts.

I'd prefer to keep the DT binding docs with the driver patches.

thx,

Jason.

Re: [PATCH 4/4] Phy: Add DT nodes on kirkwood and Dove for the SATA PHY

[Jason Cooper]

On Tue, Dec 17, 2013 at 09:21:52PM +0100, Andrew Lunn wrote:
> Add nodes for the two SATA PHYs on kirkwood.
> Add node for the one SATA PHY on Dove.
> Add pHandles to the PHYs in the sata nodes.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> v1->v2:
> sata_phy@... ->sata-phy@
> value after '@' matching the first address in the reg.
> 
> v2->v3:
> "0" -> "port0", etc.
> kirkewood -> kirkwood
> ---
>  arch/arm/boot/dts/dove.dtsi          | 11 +++++++++++
>  arch/arm/boot/dts/kirkwood-6281.dtsi |  2 ++
>  arch/arm/boot/dts/kirkwood-6282.dtsi |  2 ++
>  arch/arm/boot/dts/kirkwood.dtsi      | 18 ++++++++++++++++++
>  4 files changed, 33 insertions(+)

Applied to mvebu/dt with Kishon's Ack.

Please double check me, I had to shuffle dove.dtsi since I recently
sorted the nodes under the ocp bus.

thx,

Jason.

[PATCH v4 0/4] PHY Driver for Marvell SATA

[Andrew Lunn]

This version adds the requested checking of return values
in sata_mv.c. The other patches are unchanged.

Andrew Lunn (4):
  Phy: DT binding documentation for Marvell MVEBU SATA phy.
  Phy: Add a PHY driver for Marvell MVEBU SATA PHY.
  SATA: MV: Add support for the optional PHYs
  Phy: Add DT nodes on kirkwood and Dove for the SATA PHY

 Documentation/devicetree/bindings/ata/marvell.txt  |    6 +
 .../devicetree/bindings/phy/mvebu-phy.txt          |   22 ++++
 arch/arm/boot/dts/dove.dtsi                        |   11 ++
 arch/arm/boot/dts/kirkwood-6281.dtsi               |    2 +
 arch/arm/boot/dts/kirkwood-6282.dtsi               |    2 +
 arch/arm/boot/dts/kirkwood.dtsi                    |   18 +++
 drivers/ata/sata_mv.c                              |   27 ++++
 drivers/phy/Kconfig                                |    6 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-mvebu-sata.c                       |  137 ++++++++++++++++++++
 10 files changed, 232 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mvebu-phy.txt
 create mode 100644 drivers/phy/phy-mvebu-sata.c

-- 
1.7.10.4

[PATCH v4 1/4] Phy: DT binding documentation for Marvell MVEBU SATA phy.

[Andrew Lunn]

Describe the binding for the Marvell MVEBU SATA phy. This driver
can be used at least with Kirkwood, Dove and maybe others.
Additionally, update the SATA binding with the properties to link
to the phy nodes.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v1->v2:
Correct #phy-cells
Correct number after @ to match first reg address.
Rename to phy-mvebu.txt

v2->v3:
Renamed to mvebu-phy.txt
Use "port0", "port1" instead of "0", "1"
---
 Documentation/devicetree/bindings/ata/marvell.txt  |    6 ++++++
 .../devicetree/bindings/phy/mvebu-phy.txt          |   22 ++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mvebu-phy.txt

diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
index b5cdd20..4c5447f 100644
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -6,11 +6,17 @@ Required Properties:
 - interrupts    : Interrupt controller is using
 - nr-ports      : Number of SATA ports in use.
 
+Optional Properties:
+- phys		: List of phandles to sata phys
+- phy-names	: Should be "port0", "port1", etc, one per phandle
+
 Example:
 
 	sata@80000 {
 		compatible = "marvell,orion-sata";
 		reg = <0x80000 0x5000>;
 		interrupts = <21>;
+		phys = <&sata_phy0>, <&sata_phy1>;
+		phy-names = "port0", "port1";
 		nr-ports = <2>;
 	}
diff --git a/Documentation/devicetree/bindings/phy/mvebu-phy.txt b/Documentation/devicetree/bindings/phy/mvebu-phy.txt
new file mode 100644
index 0000000..6cb3364
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mvebu-phy.txt
@@ -0,0 +1,22 @@
+* Marvell MVEBU SATA PHY
+
+Power control for the SATA phy found on Marvell MVEBU SoCs.
+
+This document extends the binding described in phy-bindings.txt
+
+Required properties :
+
+ - reg		   : Offset and length of the register set for the SATA device
+ - compatible	   : Should be "marvell,mvebu-sata-phy"
+ - clocks	   : phandle of clock and specifier that supplies the device
+ - clock-names	   : Should be "sata"
+
+Example:
+		sata-phy@84000 {
+			compatible = "marvell,mvebu-sata-phy";
+			reg = <0x84000 0x0334>;
+			clocks = <&gate_clk 15>;
+			clock-names = "sata";
+			#phy-cells = <0>;
+			status = "ok";
+		};
-- 
1.7.10.4

[PATCH v4 2/4] Phy: Add a PHY driver for Marvell MVEBU SATA PHY.

[Andrew Lunn]

Kirkwood and Dove can turn the SATA phy on and off. Add a PHY driver
to control this.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v1->v2:
Use #defines instead of magic values
select GENERIC_PHY in Kconfig.

v3->v4

Register phy_provider as the last step.
---
 drivers/phy/Kconfig          |    6 ++
 drivers/phy/Makefile         |    1 +
 drivers/phy/phy-mvebu-sata.c |  137 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 144 insertions(+)
 create mode 100644 drivers/phy/phy-mvebu-sata.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..7464d31 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -21,6 +21,12 @@ config PHY_EXYNOS_MIPI_VIDEO
 	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
 	  and EXYNOS SoCs.
 
+config PHY_MVEBU_SATA
+	def_bool y
+	depends on ARCH_KIRKWOOD || ARCH_DOVE
+	depends on OF
+	select GENERIC_PHY
+
 config OMAP_USB2
 	tristate "OMAP USB2 PHY Driver"
 	depends on ARCH_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..4e4adc9 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,5 +5,6 @@
 obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
diff --git a/drivers/phy/phy-mvebu-sata.c b/drivers/phy/phy-mvebu-sata.c
new file mode 100644
index 0000000..d70ecd6
--- /dev/null
+++ b/drivers/phy/phy-mvebu-sata.c
@@ -0,0 +1,137 @@
+/*
+ *	phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
+ *
+ *	Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+struct priv {
+	struct clk	*clk;
+	void __iomem	*base;
+};
+
+#define SATA_PHY_MODE_2	0x0330
+#define  MODE_2_FORCE_PU_TX	BIT(0)
+#define  MODE_2_FORCE_PU_RX	BIT(1)
+#define  MODE_2_PU_PLL		BIT(2)
+#define  MODE_2_PU_IVREF	BIT(3)
+#define SATA_IF_CTRL	0x0050
+#define  CTRL_PHY_SHUTDOWN	BIT(9)
+
+static int phy_mvebu_sata_power_on(struct phy *phy)
+{
+	struct priv *priv = phy_get_drvdata(phy);
+	u32 reg;
+
+	clk_prepare_enable(priv->clk);
+
+	/* Enable PLL and IVREF */
+	reg = readl(priv->base + SATA_PHY_MODE_2);
+	reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
+		MODE_2_PU_PLL | MODE_2_PU_IVREF);
+	writel(reg , priv->base + SATA_PHY_MODE_2);
+
+	/* Enable PHY */
+	reg = readl(priv->base + SATA_IF_CTRL);
+	reg &= ~CTRL_PHY_SHUTDOWN;
+	writel(reg, priv->base + SATA_IF_CTRL);
+
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static int phy_mvebu_sata_power_off(struct phy *phy)
+{
+	struct priv *priv = phy_get_drvdata(phy);
+	u32 reg;
+
+	clk_prepare_enable(priv->clk);
+
+	/* Disable PLL and IVREF */
+	reg = readl(priv->base + SATA_PHY_MODE_2);
+	reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
+		 MODE_2_PU_PLL | MODE_2_PU_IVREF);
+	writel(reg, priv->base + SATA_PHY_MODE_2);
+
+	/* Disable PHY */
+	reg = readl(priv->base + SATA_IF_CTRL);
+	reg |= CTRL_PHY_SHUTDOWN;
+	writel(reg, priv->base + SATA_IF_CTRL);
+
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static struct phy_ops phy_mvebu_sata_ops = {
+	.power_on	= phy_mvebu_sata_power_on,
+	.power_off	= phy_mvebu_sata_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int phy_mvebu_sata_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct resource *res;
+	struct priv *priv;
+	struct phy *phy;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->clk = devm_clk_get(&pdev->dev, "sata");
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
+	phy = devm_phy_create(&pdev->dev, &phy_mvebu_sata_ops, NULL);
+	if (IS_ERR(phy))
+		return PTR_ERR(phy);
+
+	phy_set_drvdata(phy, priv);
+
+	phy_provider = devm_of_phy_provider_register(&pdev->dev,
+						     of_phy_simple_xlate);
+	if (IS_ERR(phy_provider))
+		return PTR_ERR(phy_provider);
+
+	/* The boot loader may of left it on. Turn it off. */
+	phy_mvebu_sata_power_off(phy);
+
+	return 0;
+}
+
+static const struct of_device_id phy_mvebu_sata_of_match[] = {
+	{ .compatible = "marvell,mvebu-sata-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, phy_mvebu_sata_of_match);
+
+static struct platform_driver phy_mvebu_sata_driver = {
+	.probe	= phy_mvebu_sata_probe,
+	.driver = {
+		.name	= "phy-mvebu-sata",
+		.owner	= THIS_MODULE,
+		.of_match_table	= phy_mvebu_sata_of_match,
+	}
+};
+module_platform_driver(phy_mvebu_sata_driver);
+
+MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
+MODULE_DESCRIPTION("Marvell MVEBU SATA PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4

[PATCH v4 3/4] SATA: MV: Add support for the optional PHYs

[Andrew Lunn]

Some Marvell SoCs have a SATA PHY which can be powered off, in order
to save power. Make use of the generic phy framework to control these
phys.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v2->v3
Look for phys using name "port0", "port1", etc.

v3->v4
Warn when devm_phy_get() returns a fatal error.
hpriv->port_phys[port] contains NULL or phy, never error code.
---
 drivers/ata/sata_mv.c |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 56be318..eaa21ed 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -60,6 +60,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
 #include <linux/clk.h>
+#include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/mbus.h>
@@ -563,6 +564,12 @@ struct mv_host_priv {
 	struct clk		*clk;
 	struct clk              **port_clks;
 	/*
+	 * Some devices have a SATA PHY which can be enabled/disabled
+	 * in order to save power. These are optional: if the platform
+	 * devices does not have any phy, they won't be used.
+	 */
+	struct phy		**port_phys;
+	/*
 	 * These consistent DMA memory pools give us guaranteed
 	 * alignment for hardware-accessed data structures,
 	 * and less memory waste in accomplishing the alignment.
@@ -4076,6 +4083,11 @@ static int mv_platform_probe(struct platform_device *pdev)
 					GFP_KERNEL);
 	if (!hpriv->port_clks)
 		return -ENOMEM;
+	hpriv->port_phys = devm_kzalloc(&pdev->dev,
+					sizeof(struct phy *) * n_ports,
+					GFP_KERNEL);
+	if (!hpriv->port_phys)
+		return -ENOMEM;
 	host->private_data = hpriv;
 	hpriv->n_ports = n_ports;
 	hpriv->board_idx = chip_soc;
@@ -4097,6 +4109,17 @@ static int mv_platform_probe(struct platform_device *pdev)
 		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
 		if (!IS_ERR(hpriv->port_clks[port]))
 			clk_prepare_enable(hpriv->port_clks[port]);
+
+		sprintf(port_number, "port%d", port);
+		hpriv->port_phys[port] = devm_phy_get(&pdev->dev, port_number);
+		if (IS_ERR(hpriv->port_phys[port])) {
+			rc = PTR_ERR(hpriv->port_phys[port]);
+			hpriv->port_phys[port] = NULL;
+			if ((rc != -EPROBE_DEFER) && (rc != -ENODEV))
+				dev_warn(&pdev->dev, "error getting phy");
+			goto err;
+		} else
+			phy_power_on(hpriv->port_phys[port]);
 	}
 
 	/*
@@ -4132,6 +4155,8 @@ err:
 			clk_disable_unprepare(hpriv->port_clks[port]);
 			clk_put(hpriv->port_clks[port]);
 		}
+		if (hpriv->port_phys[port])
+			phy_power_off(hpriv->port_phys[port]);
 	}
 
 	return rc;
@@ -4161,6 +4186,8 @@ static int mv_platform_remove(struct platform_device *pdev)
 			clk_disable_unprepare(hpriv->port_clks[port]);
 			clk_put(hpriv->port_clks[port]);
 		}
+		if (hpriv->port_phys[port])
+			phy_power_off(hpriv->port_phys[port]);
 	}
 	return 0;
 }
-- 
1.7.10.4

[PATCH v4 4/4] Phy: Add DT nodes on kirkwood and Dove for the SATA PHY

[Andrew Lunn]

Add nodes for the two SATA PHYs on kirkwood.
Add node for the one SATA PHY on Dove.
Add pHandles to the PHYs in the sata nodes.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
v1->v2:
sata_phy@... ->sata-phy@
value after '@' matching the first address in the reg.

v2->v3:
"0" -> "port0", etc.
kirkewood -> kirkwood
---
 arch/arm/boot/dts/dove.dtsi          |   11 +++++++++++
 arch/arm/boot/dts/kirkwood-6281.dtsi |    2 ++
 arch/arm/boot/dts/kirkwood-6282.dtsi |    2 ++
 arch/arm/boot/dts/kirkwood.dtsi      |   18 ++++++++++++++++++
 4 files changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 113a8bc..198d036 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -490,10 +490,21 @@
 				reg = <0xa0000 0x2400>;
 				interrupts = <62>;
 				clocks = <&gate_clk 3>;
+				phys = <&sata_phy0>;
+				phy-names = "port0";
 				nr-ports = <1>;
 				status = "disabled";
 			};
 
+			sata_phy0: sata-phy@a2000 {
+				compatible = "marvell,mvebu-sata-phy";
+				reg = <0xa2000 0x0334>;
+				clocks = <&gate_clk 3>;
+				clock-names = "sata";
+				#phy-cells = <0>;
+				status = "ok";
+			};
+
 			rtc: real-time-clock@d8500 {
 				compatible = "marvell,orion-rtc";
 				reg = <0xd8500 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 650ef30..18400e7 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -89,6 +89,8 @@
 			interrupts = <21>;
 			clocks = <&gate_clk 14>, <&gate_clk 15>;
 			clock-names = "0", "1";
+			phys = <&sata_phy0>, <&sata_phy1>;
+			phy-names = "port0", "port1";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 3933a33..69c622b 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -117,6 +117,8 @@
 			interrupts = <21>;
 			clocks = <&gate_clk 14>, <&gate_clk 15>;
 			clock-names = "0", "1";
+			phys = <&sata_phy0>, <&sata_phy1>;
+			phy-names = "port0", "port1";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 8b73c80..ee06951 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -282,5 +282,23 @@
 				/* set phy-handle property in board file */
 			};
 		};
+
+		sata_phy0: sata-phy@82000 {
+			compatible = "marvell,mvebu-sata-phy";
+			reg = <0x82000 0x0334>;
+			clocks = <&gate_clk 14>;
+			clock-names = "sata";
+			#phy-cells = <0>;
+			status = "ok";
+		};
+
+		sata_phy1: sata-phy@84000 {
+			compatible = "marvell,mvebu-sata-phy";
+			reg = <0x84000 0x0334>;
+			clocks = <&gate_clk 15>;
+			clock-names = "sata";
+			#phy-cells = <0>;
+			status = "ok";
+		};
 	};
 };
-- 
1.7.10.4

Re: [PATCH v4 2/4] Phy: Add a PHY driver for Marvell MVEBU SATA PHY.

[Kishon Vijay Abraham I]

Hi,

On Thursday 26 December 2013 10:55 PM, Andrew Lunn wrote:
> Kirkwood and Dove can turn the SATA phy on and off. Add a PHY driver
> to control this.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> v1->v2:
> Use #defines instead of magic values
> select GENERIC_PHY in Kconfig.
>
> v3->v4
>
> Register phy_provider as the last step.

The previous version is already sent to be merged. We can have the new 
change merged in the rc cycle.

Cheers
Kishon

> ---
>   drivers/phy/Kconfig          |    6 ++
>   drivers/phy/Makefile         |    1 +
>   drivers/phy/phy-mvebu-sata.c |  137 ++++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 144 insertions(+)
>   create mode 100644 drivers/phy/phy-mvebu-sata.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index a344f3d..7464d31 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -21,6 +21,12 @@ config PHY_EXYNOS_MIPI_VIDEO
>   	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
>   	  and EXYNOS SoCs.
>
> +config PHY_MVEBU_SATA
> +	def_bool y
> +	depends on ARCH_KIRKWOOD || ARCH_DOVE
> +	depends on OF
> +	select GENERIC_PHY
> +
>   config OMAP_USB2
>   	tristate "OMAP USB2 PHY Driver"
>   	depends on ARCH_OMAP2PLUS
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index d0caae9..4e4adc9 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -5,5 +5,6 @@
>   obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
>   obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
>   obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
> +obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>   obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>   obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> diff --git a/drivers/phy/phy-mvebu-sata.c b/drivers/phy/phy-mvebu-sata.c
> new file mode 100644
> index 0000000..d70ecd6
> --- /dev/null
> +++ b/drivers/phy/phy-mvebu-sata.c
> @@ -0,0 +1,137 @@
> +/*
> + *	phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
> + *
> + *	Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
> + *
> + *	This program is free software; you can redistribute it and/or
> + *	modify it under the terms of the GNU General Public License
> + *	as published by the Free Software Foundation; either version
> + *	2 of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +struct priv {
> +	struct clk	*clk;
> +	void __iomem	*base;
> +};
> +
> +#define SATA_PHY_MODE_2	0x0330
> +#define  MODE_2_FORCE_PU_TX	BIT(0)
> +#define  MODE_2_FORCE_PU_RX	BIT(1)
> +#define  MODE_2_PU_PLL		BIT(2)
> +#define  MODE_2_PU_IVREF	BIT(3)
> +#define SATA_IF_CTRL	0x0050
> +#define  CTRL_PHY_SHUTDOWN	BIT(9)
> +
> +static int phy_mvebu_sata_power_on(struct phy *phy)
> +{
> +	struct priv *priv = phy_get_drvdata(phy);
> +	u32 reg;
> +
> +	clk_prepare_enable(priv->clk);
> +
> +	/* Enable PLL and IVREF */
> +	reg = readl(priv->base + SATA_PHY_MODE_2);
> +	reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
> +		MODE_2_PU_PLL | MODE_2_PU_IVREF);
> +	writel(reg , priv->base + SATA_PHY_MODE_2);
> +
> +	/* Enable PHY */
> +	reg = readl(priv->base + SATA_IF_CTRL);
> +	reg &= ~CTRL_PHY_SHUTDOWN;
> +	writel(reg, priv->base + SATA_IF_CTRL);
> +
> +	clk_disable_unprepare(priv->clk);
> +
> +	return 0;
> +}
> +
> +static int phy_mvebu_sata_power_off(struct phy *phy)
> +{
> +	struct priv *priv = phy_get_drvdata(phy);
> +	u32 reg;
> +
> +	clk_prepare_enable(priv->clk);
> +
> +	/* Disable PLL and IVREF */
> +	reg = readl(priv->base + SATA_PHY_MODE_2);
> +	reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
> +		 MODE_2_PU_PLL | MODE_2_PU_IVREF);
> +	writel(reg, priv->base + SATA_PHY_MODE_2);
> +
> +	/* Disable PHY */
> +	reg = readl(priv->base + SATA_IF_CTRL);
> +	reg |= CTRL_PHY_SHUTDOWN;
> +	writel(reg, priv->base + SATA_IF_CTRL);
> +
> +	clk_disable_unprepare(priv->clk);
> +
> +	return 0;
> +}
> +
> +static struct phy_ops phy_mvebu_sata_ops = {
> +	.power_on	= phy_mvebu_sata_power_on,
> +	.power_off	= phy_mvebu_sata_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int phy_mvebu_sata_probe(struct platform_device *pdev)
> +{
> +	struct phy_provider *phy_provider;
> +	struct resource *res;
> +	struct priv *priv;
> +	struct phy *phy;
> +
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	priv->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	priv->clk = devm_clk_get(&pdev->dev, "sata");
> +	if (IS_ERR(priv->clk))
> +		return PTR_ERR(priv->clk);
> +
> +	phy = devm_phy_create(&pdev->dev, &phy_mvebu_sata_ops, NULL);
> +	if (IS_ERR(phy))
> +		return PTR_ERR(phy);
> +
> +	phy_set_drvdata(phy, priv);
> +
> +	phy_provider = devm_of_phy_provider_register(&pdev->dev,
> +						     of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider))
> +		return PTR_ERR(phy_provider);
> +
> +	/* The boot loader may of left it on. Turn it off. */
> +	phy_mvebu_sata_power_off(phy);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id phy_mvebu_sata_of_match[] = {
> +	{ .compatible = "marvell,mvebu-sata-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, phy_mvebu_sata_of_match);
> +
> +static struct platform_driver phy_mvebu_sata_driver = {
> +	.probe	= phy_mvebu_sata_probe,
> +	.driver = {
> +		.name	= "phy-mvebu-sata",
> +		.owner	= THIS_MODULE,
> +		.of_match_table	= phy_mvebu_sata_of_match,
> +	}
> +};
> +module_platform_driver(phy_mvebu_sata_driver);
> +
> +MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
> +MODULE_DESCRIPTION("Marvell MVEBU SATA PHY driver");
> +MODULE_LICENSE("GPL v2");
>

Re: [PATCH v4 2/4] Phy: Add a PHY driver for Marvell MVEBU SATA PHY.

[Jason Cooper]

On Fri, Dec 27, 2013 at 10:03:22PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 26 December 2013 10:55 PM, Andrew Lunn wrote:
> >Kirkwood and Dove can turn the SATA phy on and off. Add a PHY driver
> >to control this.
> >
> >Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> >---
> >v1->v2:
> >Use #defines instead of magic values
> >select GENERIC_PHY in Kconfig.
> >
> >v3->v4
> >
> >Register phy_provider as the last step.
> 
> The previous version is already sent to be merged. We can have the
> new change merged in the rc cycle.

Kishon,

Looking at the patch dependencies, we'd like to keep the sata change in
the same branch as the phy changes.  Would you mind picking that one up
and placing it in the same branch as the ones you already took?  I have
the DT changes, as they don't cause problems out on their own.

Tijon,

If you're ok with this, would you mind Acking the sata patch for Kishon?

thx,

Jason.

> >---
> >  drivers/phy/Kconfig          |    6 ++
> >  drivers/phy/Makefile         |    1 +
> >  drivers/phy/phy-mvebu-sata.c |  137 ++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 144 insertions(+)
> >  create mode 100644 drivers/phy/phy-mvebu-sata.c
> >
> >diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> >index a344f3d..7464d31 100644
> >--- a/drivers/phy/Kconfig
> >+++ b/drivers/phy/Kconfig
> >@@ -21,6 +21,12 @@ config PHY_EXYNOS_MIPI_VIDEO
> >  	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
> >  	  and EXYNOS SoCs.
> >
> >+config PHY_MVEBU_SATA
> >+	def_bool y
> >+	depends on ARCH_KIRKWOOD || ARCH_DOVE
> >+	depends on OF
> >+	select GENERIC_PHY
> >+
> >  config OMAP_USB2
> >  	tristate "OMAP USB2 PHY Driver"
> >  	depends on ARCH_OMAP2PLUS
> >diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> >index d0caae9..4e4adc9 100644
> >--- a/drivers/phy/Makefile
> >+++ b/drivers/phy/Makefile
> >@@ -5,5 +5,6 @@
> >  obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
> >  obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
> >  obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
> >+obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
> >  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
> >  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> >diff --git a/drivers/phy/phy-mvebu-sata.c b/drivers/phy/phy-mvebu-sata.c
> >new file mode 100644
> >index 0000000..d70ecd6
> >--- /dev/null
> >+++ b/drivers/phy/phy-mvebu-sata.c
> >@@ -0,0 +1,137 @@
> >+/*
> >+ *	phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
> >+ *
> >+ *	Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
> >+ *
> >+ *	This program is free software; you can redistribute it and/or
> >+ *	modify it under the terms of the GNU General Public License
> >+ *	as published by the Free Software Foundation; either version
> >+ *	2 of the License, or (at your option) any later version.
> >+ */
> >+
> >+#include <linux/kernel.h>
> >+#include <linux/module.h>
> >+#include <linux/clk.h>
> >+#include <linux/phy/phy.h>
> >+#include <linux/io.h>
> >+#include <linux/platform_device.h>
> >+
> >+struct priv {
> >+	struct clk	*clk;
> >+	void __iomem	*base;
> >+};
> >+
> >+#define SATA_PHY_MODE_2	0x0330
> >+#define  MODE_2_FORCE_PU_TX	BIT(0)
> >+#define  MODE_2_FORCE_PU_RX	BIT(1)
> >+#define  MODE_2_PU_PLL		BIT(2)
> >+#define  MODE_2_PU_IVREF	BIT(3)
> >+#define SATA_IF_CTRL	0x0050
> >+#define  CTRL_PHY_SHUTDOWN	BIT(9)
> >+
> >+static int phy_mvebu_sata_power_on(struct phy *phy)
> >+{
> >+	struct priv *priv = phy_get_drvdata(phy);
> >+	u32 reg;
> >+
> >+	clk_prepare_enable(priv->clk);
> >+
> >+	/* Enable PLL and IVREF */
> >+	reg = readl(priv->base + SATA_PHY_MODE_2);
> >+	reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
> >+		MODE_2_PU_PLL | MODE_2_PU_IVREF);
> >+	writel(reg , priv->base + SATA_PHY_MODE_2);
> >+
> >+	/* Enable PHY */
> >+	reg = readl(priv->base + SATA_IF_CTRL);
> >+	reg &= ~CTRL_PHY_SHUTDOWN;
> >+	writel(reg, priv->base + SATA_IF_CTRL);
> >+
> >+	clk_disable_unprepare(priv->clk);
> >+
> >+	return 0;
> >+}
> >+
> >+static int phy_mvebu_sata_power_off(struct phy *phy)
> >+{
> >+	struct priv *priv = phy_get_drvdata(phy);
> >+	u32 reg;
> >+
> >+	clk_prepare_enable(priv->clk);
> >+
> >+	/* Disable PLL and IVREF */
> >+	reg = readl(priv->base + SATA_PHY_MODE_2);
> >+	reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
> >+		 MODE_2_PU_PLL | MODE_2_PU_IVREF);
> >+	writel(reg, priv->base + SATA_PHY_MODE_2);
> >+
> >+	/* Disable PHY */
> >+	reg = readl(priv->base + SATA_IF_CTRL);
> >+	reg |= CTRL_PHY_SHUTDOWN;
> >+	writel(reg, priv->base + SATA_IF_CTRL);
> >+
> >+	clk_disable_unprepare(priv->clk);
> >+
> >+	return 0;
> >+}
> >+
> >+static struct phy_ops phy_mvebu_sata_ops = {
> >+	.power_on	= phy_mvebu_sata_power_on,
> >+	.power_off	= phy_mvebu_sata_power_off,
> >+	.owner		= THIS_MODULE,
> >+};
> >+
> >+static int phy_mvebu_sata_probe(struct platform_device *pdev)
> >+{
> >+	struct phy_provider *phy_provider;
> >+	struct resource *res;
> >+	struct priv *priv;
> >+	struct phy *phy;
> >+
> >+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> >+
> >+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >+	priv->base = devm_ioremap_resource(&pdev->dev, res);
> >+	if (IS_ERR(priv->base))
> >+		return PTR_ERR(priv->base);
> >+
> >+	priv->clk = devm_clk_get(&pdev->dev, "sata");
> >+	if (IS_ERR(priv->clk))
> >+		return PTR_ERR(priv->clk);
> >+
> >+	phy = devm_phy_create(&pdev->dev, &phy_mvebu_sata_ops, NULL);
> >+	if (IS_ERR(phy))
> >+		return PTR_ERR(phy);
> >+
> >+	phy_set_drvdata(phy, priv);
> >+
> >+	phy_provider = devm_of_phy_provider_register(&pdev->dev,
> >+						     of_phy_simple_xlate);
> >+	if (IS_ERR(phy_provider))
> >+		return PTR_ERR(phy_provider);
> >+
> >+	/* The boot loader may of left it on. Turn it off. */
> >+	phy_mvebu_sata_power_off(phy);
> >+
> >+	return 0;
> >+}
> >+
> >+static const struct of_device_id phy_mvebu_sata_of_match[] = {
> >+	{ .compatible = "marvell,mvebu-sata-phy" },
> >+	{ },
> >+};
> >+MODULE_DEVICE_TABLE(of, phy_mvebu_sata_of_match);
> >+
> >+static struct platform_driver phy_mvebu_sata_driver = {
> >+	.probe	= phy_mvebu_sata_probe,
> >+	.driver = {
> >+		.name	= "phy-mvebu-sata",
> >+		.owner	= THIS_MODULE,
> >+		.of_match_table	= phy_mvebu_sata_of_match,
> >+	}
> >+};
> >+module_platform_driver(phy_mvebu_sata_driver);
> >+
> >+MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
> >+MODULE_DESCRIPTION("Marvell MVEBU SATA PHY driver");
> >+MODULE_LICENSE("GPL v2");
> >
> 

Re: [PATCH v4 2/4] Phy: Add a PHY driver for Marvell MVEBU SATA PHY.

[Kishon Vijay Abraham I]

Hi Jason,

On Saturday 11 January 2014 01:01 AM, Jason Cooper wrote:
> On Fri, Dec 27, 2013 at 10:03:22PM +0530, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 26 December 2013 10:55 PM, Andrew Lunn wrote:
>>> Kirkwood and Dove can turn the SATA phy on and off. Add a PHY driver
>>> to control this.
>>>
>>> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
>>> ---
>>> v1->v2:
>>> Use #defines instead of magic values
>>> select GENERIC_PHY in Kconfig.
>>>
>>> v3->v4
>>>
>>> Register phy_provider as the last step.
>>
>> The previous version is already sent to be merged. We can have the
>> new change merged in the rc cycle.
>
> Kishon,
>
> Looking at the patch dependencies, we'd like to keep the sata change in
> the same branch as the phy changes.  Would you mind picking that one up
> and placing it in the same branch as the ones you already took?  I have

PHY changes go in Greg's tree and he generally closes it ~2 weeks before 
the start of merge window. So it's too late to go in PHY tree for this 
merge window. Sorry.

Thanks
Kishon

Re: [PATCH v4 3/4] SATA: MV: Add support for the optional PHYs

[Tejun Heo]

On Thu, Dec 26, 2013 at 06:25:41PM +0100, Andrew Lunn wrote:
> Some Marvell SoCs have a SATA PHY which can be powered off, in order
> to save power. Make use of the generic phy framework to control these
> phys.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>

Applied to libata/for-3.14.  It's late but not applying this patch
would reportedly lead to boot failures in certain configurations.

Thanks.

-- 
tejun