From mboxrd@z Thu Jan 1 00:00:00 1970 From: Markus Pargmann Subject: Re: [PATCH v3 5/6] ASoC: tlv320aic32x4: Support for master clock Date: Tue, 28 Jan 2014 11:01:47 +0100 Message-ID: <20140128100147.GE32009@pengutronix.de> References: <1390824190-18376-1-git-send-email-mpa@pengutronix.de> <1390824190-18376-6-git-send-email-mpa@pengutronix.de> <20140127181707.GD11841@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20140127181707.GD11841@sirena.org.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: Mark Brown Cc: Mark Rutland , devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Lars-Peter Clausen , Pawel Moll , Ian Campbell , Liam Girdwood , Rob Herring , kernel@pengutronix.de, Kumar Gala List-Id: devicetree@vger.kernel.org On Mon, Jan 27, 2014 at 06:17:07PM +0000, Mark Brown wrote: > On Mon, Jan 27, 2014 at 01:03:09PM +0100, Markus Pargmann wrote: > > > case SND_SOC_BIAS_STANDBY: > > + /* Switch off master clock */ > > + if (!IS_ERR(aic32x4->mclk)) > > + clk_disable_unprepare(aic32x4->mclk); > > + > > /* Switch off PLL */ > > snd_soc_update_bits(codec, AIC32X4_PLLPR, > > AIC32X4_PLLEN, 0); > > This looks like it's disabling the MCLK before disabling the PLL - if > the two are being disabled together I would expect to see the other way > around. Yes right, should be the other way round, although it doesn't make a difference. I will change it for v4. Thanks, Markus -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |