From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Turquette Subject: Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk" Date: Wed, 05 Feb 2014 08:03:50 -0800 Message-ID: <20140205160350.22158.37384@quantum> References: <1389303079-19808-1-git-send-email-dinguyen@altera.com> <1389303079-19808-2-git-send-email-dinguyen@altera.com> <52CF6D67.1000803@samsung.com> <52D680E4.6090608@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <52D680E4.6090608@gmail.com> Sender: linux-mmc-owner@vger.kernel.org To: Dinh Nguyen , Jaehoon Chung , dinguyen@altera.com, arnd@arndb.de, cjb@laptop.org, tgih.jun@samsung.com, heiko@sntech.de, dianders@chromium.org, alim.akhtar@samsung.com, bzhao@marvell.com Cc: zhangfei.gao@linaro.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org Quoting Dinh Nguyen (2014-01-15 04:36:52) > Hi Mike, > > Can you apply this to your clk tree? The patch looks good to me, but I think it depends on your pending pull request. Can you add this to that pull request and rebase it to 3.14-rc1? Thanks, Mike > > Thanks, > Dinh >