From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sergei Shtylyov Subject: [PATCH 2/2] ARM: shmobile: lager: add Ether DT support Date: Fri, 7 Feb 2014 00:58:30 +0300 Message-ID: <201402070058.31405.sergei.shtylyov@cogentembedded.com> References: <201402070054.39989.sergei.shtylyov@cogentembedded.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <201402070054.39989.sergei.shtylyov@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org To: horms@verge.net.au, linux-sh@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Define the Lager board dependent part of the Ether device node. Signed-off-by: Sergei Shtylyov --- arch/arm/boot/dts/r8a7790-lager.dts | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) Index: renesas/arch/arm/boot/dts/r8a7790-lager.dts =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7790-lager.dts +++ renesas/arch/arm/boot/dts/r8a7790-lager.dts @@ -1,7 +1,8 @@ /* * Device Tree Source for the Lager board * - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -76,12 +77,40 @@ renesas,function = "scif1"; }; + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq0"; + renesas,function = "intc"; + }; + mmc1_pins: mmc1 { renesas,groups = "mmc1_data8", "mmc1_ctrl"; renesas,function = "mmc1"; }; }; +ðer { + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "ok"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&phy1_pins>; + pinctrl-names = "default"; + }; +}; + &mmcif1 { pinctrl-0 = <&mmc1_pins>; pinctrl-names = "default";