Re: [PATCH v3 2/5] clk: sunxi: Add USB clock register defintions

[Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>]

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Hi,

On Fri, Feb 07, 2014 at 03:32:30PM +0100, Hans de Goede wrote:
> From: Roman Byshko <rbyshko-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> 
> Add register definitions for the usb-clk register found on sun4i, sun5i and
> sun7i SoCs.
> 
> Signed-off-by: Roman Byshko <rbyshko-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  5 +++++
>  drivers/clk/sunxi/clk-sunxi.c                     | 12 ++++++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 27f19f1..e368a86c 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -38,6 +38,8 @@ Required properties:
>  	"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
>  	"allwinner,sun7i-a20-out-clk" - for the external output clocks
>  	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
> +	"allwinner,sun4i-usb-clk" - for usb gates + resets on A10 / A20

I know I asked you otherwise, but since we're moving to sun4i-a10-*
compatibles, can you do it here too ? :)

Thanks!
Maxime

> +	"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
>  
>  Required properties for all clocks:
>  - reg : shall be the control register address for the clock.
> @@ -54,6 +56,9 @@ Required properties for all clocks:
>  For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
>  dummy clocks at 25 MHz and 125 MHz, respectively. See example.
>  
> +And "allwinner,*-usb-clk" clocks also require:
> +- reset-cells : shall be set to 1
> +
>  Clock consumers should specify the desired clocks they use with a
>  "clocks" phandle cell. Consumers that are using a gated clock should
>  provide an additional ID in their clock property. This ID is the
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 1e15e4c..3ba1402 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -910,6 +910,16 @@ static const struct gates_data sun4i_ahb_gates_data __initconst = {
>  	.mask = {0x7F77FFF, 0x14FB3F},
>  };
>  
> +static const struct gates_data sun4i_usb_gates_data __initconst = {
> +	.mask = {0x1C0},
> +	.reset_mask = 0x07,
> +};
> +
> +static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
> +	.mask = {0x140},
> +	.reset_mask = 0x03,
> +};
> +
>  static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
>  	.mask = {0x147667e7, 0x185915},
>  };
> @@ -1257,6 +1267,8 @@ static const struct of_device_id clk_gates_match[] __initconst = {
>  	{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
>  	{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
>  	{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
> +	{.compatible = "allwinner,sun4i-usb-clk", .data = &sun4i_usb_gates_data,},
> +	{.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
>  	{}
>  };
>  
> -- 
> 1.8.4.2
> 

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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