From mboxrd@z Thu Jan 1 00:00:00 1970 From: David =?utf-8?q?Lanzend=C3=B6rfer?= Subject: [PATCH v7 2/8] clk: sunxi: Implement MMC phase control Date: Mon, 17 Feb 2014 11:02:21 +0100 Message-ID: <20140217100221.15040.47203.stgit@pagira.o2s.ch> References: <20140217095907.15040.81893.stgit@pagira.o2s.ch> Reply-To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20140217095907.15040.81893.stgit-pgFh0Jf6HD9Xzn/AsuzBOg@public.gmane.org> List-Post: , List-Help: , List-Archive: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Subscribe: , List-Unsubscribe: , To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ulf Hansson , Laurent Pinchart , Mike Turquette , Simon Baatz , Hans de Goede , Emilio =?utf-8?b?TMOzcGV6?= , linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Chris Ball , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, H Hartley Sweeten , linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Tejun Heo , Maxime Ripard , Guennadi Liakhovetski , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org From: Emilio L=C3=B3pez Signed-off-by: Emilio L=C3=B3pez --- drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5a..33b9977 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 p= arent_rate, =20 =20 /** + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control + */ + +void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output) +{ + #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) + #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) + + struct clk_composite *composite =3D to_clk_composite(hw); + struct clk_hw *rate_hw =3D composite->rate_hw; + struct clk_factors *factors =3D to_clk_factors(rate_hw); + unsigned long flags =3D 0; + u32 reg; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + + reg =3D readl(factors->reg); + + /* set sample clock phase control */ + reg &=3D ~(0x7 << 20); + reg |=3D ((sample & 0x7) << 20); + + /* set output clock phase control */ + reg &=3D ~(0x7 << 8); + reg |=3D ((output & 0x7) << 8); + + writel(reg, factors->reg); + + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); +} + + +/** * sunxi_factors_clk_setup() - Setup function for factor clocks */ =20 --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/groups/opt_out.