[PATCH V6 00/12]PCI:Add SPEAr13xx PCie support

[PATCH V6 00/12]PCI:Add SPEAr13xx PCie support

[Mohit Kumar]

Patch# 1 and 2: Improvement and fixes for SPEAr13xx support.
Patch# 3,5 and 8: Add DT bindings for miphy40lp, misc and pcie node
Patch# 4,6 and 7: Add miphy40lp skelten driver and support for spear1310/40 
miphy wrapper.
Patch# 9-11: Add SPEAr13xx PCIe driver and dt support.

These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <balajitk-l0cyMroinI0@public.gmane.org>
Date:   Mon Jan 20 16:41:27 2014 +0200

    ata: ahci_platform: Manage SATA PHY

Tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Modifications for SATA are tested with SPEAr1340-evb board

Changes since v5:
- Split DT bindings for misc, miphy-40lp and pcie node into sepearte patches
- Merge config options PCIE_SPEAR13XX and PCI_MSI into defconfig patch 
- Incorporated other minor comments
Changes since v4:
- Uses per device function pointers passed from .data field to
  the of_device_id instead of of_device_is_compatible.
- Incorporated other minor comments from v4

Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3

Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
  the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall() 
 
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
 pcie designware driver improvements,fixes for IO translation bug, PCIe dw
 driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
 platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.

PCIe driver support for SPEAr1310/40 platform board is added.

These patches are tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

Mohit Kumar (2):
  SPEAr13xx: defconfig: Update
  MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

Pratyush Anand (10):
  clk: SPEAr13XX: Fix pcie clock name
  SPEAr13XX: Fix static mapping table
  phy: st-miphy40lp: Add binding information
  phy: st-miphy40lp: Add skeleton driver
  SPEAr: misc: Add binding information
  SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  SPEAr13xx: Add binding information for PCIe controller
  SPEAr13XX: dts: Add PCIe node information
  pcie: SPEAr13xx: Add designware wrapper support

 .../devicetree/bindings/arm/spear-misc.txt         |    9 +
 .../devicetree/bindings/pci/spear13xx-pcie.txt     |   14 +
 .../devicetree/bindings/phy/st-miphy40lp.txt       |   18 +
 MAINTAINERS                                        |    6 +
 arch/arm/boot/dts/spear1310-evb.dts                |    4 +
 arch/arm/boot/dts/spear1310.dtsi                   |   93 ++++-
 arch/arm/boot/dts/spear1340-evb.dts                |    4 +
 arch/arm/boot/dts/spear1340.dtsi                   |   31 ++-
 arch/arm/boot/dts/spear13xx.dtsi                   |    9 +-
 arch/arm/configs/spear13xx_defconfig               |   16 +
 arch/arm/mach-spear/Kconfig                        |    3 +
 arch/arm/mach-spear/include/mach/spear.h           |    4 +-
 arch/arm/mach-spear/spear1340.c                    |  127 +-----
 arch/arm/mach-spear/spear13xx.c                    |    2 +-
 drivers/clk/spear/spear1310_clock.c                |    6 +-
 drivers/clk/spear/spear1340_clock.c                |    2 +-
 drivers/pci/host/Kconfig                           |    8 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pcie-spear13xx.c                  |  414 +++++++++++++++
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-miphy40lp.c                        |  543 ++++++++++++++++++++
 22 files changed, 1183 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
 create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
 create mode 100644 drivers/pci/host/pcie-spear13xx.c
 create mode 100644 drivers/phy/phy-miphy40lp.c

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[PATCH V6 03/12] phy: st-miphy40lp: Add binding information

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>

ST miphy40lp can be used with PCIe, SATA and Super Speed USB
controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.

Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 .../devicetree/bindings/phy/st-miphy40lp.txt       |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt

diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
new file mode 100644
index 0000000..1c8d04c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
@@ -0,0 +1,18 @@
+ST miphy40lp DT detail
+===================================
+
+miphy40lp is a phy controller from ST Microelectronics which supports PCIe,
+SATA and Super Speed USB host and devices. It has been used in SPEAr13xx SOCs.
+
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+	Other supported soc specific compatible:
+		"st,spear1310-miphy"
+		"st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+	- 1st cell: phandle to the phy node.
+	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+	  and 2 for Super Speed USB.
-- 
1.7.0.1

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[PATCH V6 05/12] SPEAr: misc: Add binding information

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>

SPEAr SOCs have some miscellaneous registers which are used to configure
few properties of different peripheral controllers.

Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 .../devicetree/bindings/arm/spear-misc.txt         |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt

diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..ab324e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,9 @@
+SPEAr Misc configuration
+===========================
+SPEAr SOCs have some miscellaneous registers which are used to configure
+few properties of different peripheral controllers.
+
+misc node required properties:
+
+- compatible Should be	"st,spear1340-misc", "syscon".
+- reg: Address range of misc space
-- 
1.7.0.1

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[PATCH V6 08/12] SPEAr13xx: Add binding information for PCIe controller

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>

SPEAr13XX uses designware PCIe controller. This patch adds information
for the binding properties which are specific to SPEAr13XX SoC series.

Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 .../devicetree/bindings/pci/spear13xx-pcie.txt     |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
new file mode 100644
index 0000000..700e43e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
@@ -0,0 +1,14 @@
+SPEAr13xx PCIe DT detail:
+================================
+
+SPEAr13xx uses synopsis designware PCIe controller and ST MiPHY40lp as phy
+controller.
+
+Required properties:
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys		    : phandle to phy node associated with pcie controller
+- phy-names	    : must be "pcie-phy"
+- All other definitions as per generic PCI bindings
+
+ Optional properties:
+- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
-- 
1.7.0.1

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Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information

[Mark Rutland]

On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> 
> ST miphy40lp can be used with PCIe, SATA and Super Speed USB
> controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  .../devicetree/bindings/phy/st-miphy40lp.txt       |   18 ++++++++++++++++++
>  1 files changed, 18 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> new file mode 100644
> index 0000000..1c8d04c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> @@ -0,0 +1,18 @@
> +ST miphy40lp DT detail
> +===================================
> +
> +miphy40lp is a phy controller from ST Microelectronics which supports PCIe,
> +SATA and Super Speed USB host and devices. It has been used in SPEAr13xx SOCs.
> +
> +Required properties:
> +- compatible : should be "st,miphy40lp-phy"
> +	Other supported soc specific compatible:
> +		"st,spear1310-miphy"
> +		"st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers

This is very vague. What is this used for?

> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> +	- 1st cell: phandle to the phy node.
> +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> +	  and 2 for Super Speed USB.

One cell or two?

Thanks,
Mark.
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Re: [PATCH V6 05/12] SPEAr: misc: Add binding information

[Mark Rutland]

On Tue, Feb 11, 2014 at 09:30:01AM +0000, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> 
> SPEAr SOCs have some miscellaneous registers which are used to configure
> few properties of different peripheral controllers.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  .../devicetree/bindings/arm/spear-misc.txt         |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
> new file mode 100644
> index 0000000..ab324e1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
> @@ -0,0 +1,9 @@
> +SPEAr Misc configuration
> +===========================
> +SPEAr SOCs have some miscellaneous registers which are used to configure
> +few properties of different peripheral controllers.
> +
> +misc node required properties:
> +
> +- compatible Should be	"st,spear1340-misc", "syscon".
> +- reg: Address range of misc space

Is there no better name than misc?

How big is this expected to be?

Mark.
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RE: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information

[Mohit KUMAR DCG]

Hello Mark,

> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland-5wv7dgnIgG8@public.gmane.org]
> Sent: Wednesday, February 12, 2014 11:50 PM
> To: Mohit KUMAR DCG
> Cc: arnd-r2nGTMty4D4@public.gmane.org; Pratyush ANAND; Viresh Kumar; Kishon Vijay Abraham I;
> spear-devel; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information
> 
> On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> >
> > ST miphy40lp can be used with PCIe, SATA and Super Speed USB
> > controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> > Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> > Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> > Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > ---
> >  .../devicetree/bindings/phy/st-miphy40lp.txt       |   18
> ++++++++++++++++++
> >  1 files changed, 18 insertions(+), 0 deletions(-)  create mode 100644
> > Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > new file mode 100644
> > index 0000000..1c8d04c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > @@ -0,0 +1,18 @@
> > +ST miphy40lp DT detail
> > +===================================
> > +
> > +miphy40lp is a phy controller from ST Microelectronics which supports
> > +PCIe, SATA and Super Speed USB host and devices. It has been used in
> SPEAr13xx SOCs.
> > +
> > +Required properties:
> > +- compatible : should be "st,miphy40lp-phy"
> > +	Other supported soc specific compatible:
> > +		"st,spear1310-miphy"
> > +		"st,spear1340-miphy"
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> 
> This is very vague. What is this used for?

- These are Spear SoC specific miscellaneous registers. Here these are used for
to configure sata/pcie  aux clock.
> 
> > +- phy-id: Instance id of the phy.
> > +- #phy-cells : from the generic PHY bindings, must be 1.
> > +	- 1st cell: phandle to the phy node.
> > +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > +	  and 2 for Super Speed USB.
> 
> One cell or two?

- No of cells are two, is this the question?

Thanks
Mohit
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RE: [PATCH V6 05/12] SPEAr: misc: Add binding information

[Mohit KUMAR DCG]

Hello Mark,

> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland-5wv7dgnIgG8@public.gmane.org]
> Sent: Wednesday, February 12, 2014 11:51 PM
> To: Mohit KUMAR DCG
> Cc: arnd-r2nGTMty4D4@public.gmane.org; Pratyush ANAND; Viresh Kumar; spear-devel;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Subject: Re: [PATCH V6 05/12] SPEAr: misc: Add binding information
> 
> On Tue, Feb 11, 2014 at 09:30:01AM +0000, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> >
> > SPEAr SOCs have some miscellaneous registers which are used to
> > configure few properties of different peripheral controllers.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> > Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> > Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > ---
> >  .../devicetree/bindings/arm/spear-misc.txt         |    9 +++++++++
> >  1 files changed, 9 insertions(+), 0 deletions(-)  create mode 100644
> > Documentation/devicetree/bindings/arm/spear-misc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt
> > b/Documentation/devicetree/bindings/arm/spear-misc.txt
> > new file mode 100644
> > index 0000000..ab324e1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
> > @@ -0,0 +1,9 @@
> > +SPEAr Misc configuration
> > +===========================
> > +SPEAr SOCs have some miscellaneous registers which are used to
> > +configure few properties of different peripheral controllers.
> > +
> > +misc node required properties:
> > +
> > +- compatible Should be	"st,spear1340-misc", "syscon".
> > +- reg: Address range of misc space
> 
> Is there no better name than misc?

- We followed the convention used in SoC for these Miscellaneous (system
 configuration) registers.

> How big is this expected to be?

- 8K, we will mention it in reg property also.

Thanks
Mohit
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Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information

[Mark Rutland]

On Thu, Feb 13, 2014 at 05:19:11AM +0000, Mohit KUMAR DCG wrote:
> Hello Mark,
> 
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland-5wv7dgnIgG8@public.gmane.org]
> > Sent: Wednesday, February 12, 2014 11:50 PM
> > To: Mohit KUMAR DCG
> > Cc: arnd-r2nGTMty4D4@public.gmane.org; Pratyush ANAND; Viresh Kumar; Kishon Vijay Abraham I;
> > spear-devel; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information
> > 
> > On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote:
> > > From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > >
> > > ST miphy40lp can be used with PCIe, SATA and Super Speed USB
> > > controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.
> > >
> > > Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > > Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> > > Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> > > Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > > Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> > > Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > > ---
> > >  .../devicetree/bindings/phy/st-miphy40lp.txt       |   18
> > ++++++++++++++++++
> > >  1 files changed, 18 insertions(+), 0 deletions(-)  create mode 100644
> > > Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > > b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > > new file mode 100644
> > > index 0000000..1c8d04c
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > > @@ -0,0 +1,18 @@
> > > +ST miphy40lp DT detail
> > > +===================================
> > > +
> > > +miphy40lp is a phy controller from ST Microelectronics which supports
> > > +PCIe, SATA and Super Speed USB host and devices. It has been used in
> > SPEAr13xx SOCs.
> > > +
> > > +Required properties:
> > > +- compatible : should be "st,miphy40lp-phy"
> > > +	Other supported soc specific compatible:
> > > +		"st,spear1310-miphy"
> > > +		"st,spear1340-miphy"
> > > +- reg : offset and length of the PHY register set.
> > > +- misc: phandle for the syscon node to access misc registers
> > 
> > This is very vague. What is this used for?
> 
> - These are Spear SoC specific miscellaneous registers. Here these are used for
> to configure sata/pcie  aux clock.
> > 
> > > +- phy-id: Instance id of the phy.
> > > +- #phy-cells : from the generic PHY bindings, must be 1.
> > > +	- 1st cell: phandle to the phy node.
> > > +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > > +	  and 2 for Super Speed USB.
> > 
> > One cell or two?
> 
> - No of cells are two, is this the question?

The description of #phy-cells says it must be 1. Presumably it must be
2.

Thanks,
Mark
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Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information

[Arnd Bergmann]

On Tuesday 18 February 2014, Mark Rutland wrote:
> > 
> > - These are Spear SoC specific miscellaneous registers. Here these are used for
> > to configure sata/pcie  aux clock.
> > > 
> > > > +- phy-id: Instance id of the phy.
> > > > +- #phy-cells : from the generic PHY bindings, must be 1.
> > > > + - 1st cell: phandle to the phy node.
> > > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > > > +   and 2 for Super Speed USB.
> > > 
> > > One cell or two?
> > 
> > - No of cells are two, is this the question?
> 
> The description of #phy-cells says it must be 1. Presumably it must be 2.

The description here is counting the phandle, while we normally only
count the arguments following the phandle. #phy-cells=<1> is correct
here, but the description should be written a bit clearer.

	Arnd
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Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information

[Mark Rutland]

On Tue, Feb 18, 2014 at 02:58:14PM +0000, Arnd Bergmann wrote:
> On Tuesday 18 February 2014, Mark Rutland wrote:
> > > 
> > > - These are Spear SoC specific miscellaneous registers. Here these are used for
> > > to configure sata/pcie  aux clock.
> > > > 
> > > > > +- phy-id: Instance id of the phy.
> > > > > +- #phy-cells : from the generic PHY bindings, must be 1.
> > > > > + - 1st cell: phandle to the phy node.
> > > > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > > > > +   and 2 for Super Speed USB.
> > > > 
> > > > One cell or two?
> > > 
> > > - No of cells are two, is this the question?
> > 
> > The description of #phy-cells says it must be 1. Presumably it must be 2.
> 
> The description here is counting the phandle, while we normally only
> count the arguments following the phandle. #phy-cells=<1> is correct
> here, but the description should be written a bit clearer.

Ah, yes. I clearly hadn't read thoroughly enough.

We could just drop mention of the phandle under the #phy-cells
description; it's not relevant to the meaning of the single phy-specific
cell, and per the phy binding it's obviously required in clients.

Cheers,
Mark.
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