Re: [PATCH v5 2/2] i2c: New bus driver for the Qualcomm QUP I2C controller

[Josh Cartwright <joshc-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]

On Thu, Mar 13, 2014 at 07:07:43PM -0700, Bjorn Andersson wrote:
> This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs.
> The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path
> engine with input/output FIFOs and an embedded i2c mini-core. The driver
> supports FIFO mode (for low bandwidth applications) and block mode (interrupt
> generated for each block-size data transfer).
> 
> Cc: Andy Gross <agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Signed-off-by: Ivan T. Ivanov <iivanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson-/MT0OVThwyLZJqsBc5GL+g@public.gmane.org>
> +++ b/drivers/i2c/busses/i2c-qup.c
[..]
> +static int qup_i2c_xfer(struct i2c_adapter *adap,
> +			struct i2c_msg msgs[],
> +			int num)
> +{
> +	struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
> +	int ret, idx;
> +
> +	ret = pm_runtime_get_sync(qup->dev);
> +	if (IS_ERR_VALUE(ret))
> +		goto out;

General i2c question: is there a reason why the core isn't responsible
for ensuring a device is not suspended before invoking ->master_xfer
(and smbus_xfer)?

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