From mboxrd@z Thu Jan  1 00:00:00 1970
From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Subject: Re: [PATCH v6 0/3] ARM: sun7i/sun6i: irqchip: Irqchip
 driver for NMI controller
Date: Wed, 19 Mar 2014 13:32:41 +0100
Message-ID: <20140319123241.GI27873@lukather>
References: <1394890861-18347-1-git-send-email-carlo@caione.org>
 <alpine.DEB.2.02.1403191213240.18573@ionos.tec.linutronix.de>
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To: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
Cc: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
List-Id: devicetree@vger.kernel.org


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On Wed, Mar 19, 2014 at 12:13:56PM +0100, Thomas Gleixner wrote:
> On Sat, 15 Mar 2014, Carlo Caione wrote:
>=20
> > Allwinner A20/A31 SoCs have a special interrupt controller for managing=
 NMI.
> > Three register are present to (un)mask, control and acknowledge NMI.
> > These two patches add a new irqchip driver in cascade with GIC.
>=20
> If I get an ack for the DT parts, I'll pick it up.

I had some comments on it, so Carlo will probably resubmit it.

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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