[PATCH v2 0/3] Add support for Cavium Thunder ARMv8 platform

[PATCH v2 0/3] Add support for Cavium Thunder ARMv8 platform

[mohun106-Re5JQEeQqe8AvxtiuMwx3w]

From: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>

This patch series adds preliminary support for Cavium's Thunder SoC
which is based on ARMv8 core.

This patchset depends on following. They need to be applied before
working.

1) Boot time configuration of IPA
http://www.spinics.net/lists/arm-kernel/msg313723.html

2) GICv3 driver from Marc Zyngier
http://www.spinics.net/lists/kvm-arm/msg08544.html

3) GICv3 devicetree bindings from Marc Zyngier
http://www.spinics.net/lists/kvm-arm/msg08545.html

Changes from v1:
---------------
- Added documentation for the devicetree bindings used.
- Changed the Thunder device tree as per documentation.

Radha Mohan Chintakuntla (3):
  arm64: Add Kconfig option for Cavium Thunder SoC Family
  arm64: dts: Add initial dts for Cavium Thunder SoC
  Documentation: add devicetree bindings for Cavium Thunder SoC

 .../devicetree/bindings/arm/cavium-thunder.txt     |    9 +
 Documentation/devicetree/bindings/arm/cpus.txt     |    1 +
 arch/arm64/Kconfig                                 |    5 +
 arch/arm64/boot/dts/Makefile                       |    1 +
 arch/arm64/boot/dts/thunder.dts                    |  160 ++++++++++++++++++++
 5 files changed, 176 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder.txt
 create mode 100644 arch/arm64/boot/dts/thunder.dts

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[PATCH v2 1/3] arm64: Add Kconfig option for Cavium Thunder SoC Family

[mohun106-Re5JQEeQqe8AvxtiuMwx3w]

From: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>

This patch adds support in Kconfig to select Cavium Thunder platform.

Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/Kconfig |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a3c40d6..e899a7d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -113,6 +113,11 @@ source "kernel/Kconfig.freezer"
 
 menu "Platform selection"
 
+config ARCH_THUNDER
+	bool "Cavium Inc. Thunder SoC Family"
+	help
+	  This enables support for Cavium's Thunder Family of SoCs
+
 config ARCH_VEXPRESS
 	bool "ARMv8 software model (Versatile Express)"
 	select ARCH_REQUIRE_GPIOLIB
-- 
1.7.1

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[PATCH v2 2/3] arm64: dts: Add initial dts for Cavium Thunder SoC

[mohun106-Re5JQEeQqe8AvxtiuMwx3w]

From: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>

Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/Makefile    |    1 +
 arch/arm64/boot/dts/thunder.dts |  160 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 161 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..9cc8740 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_THUNDER) += thunder.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
 dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
 
diff --git a/arch/arm64/boot/dts/thunder.dts b/arch/arm64/boot/dts/thunder.dts
new file mode 100644
index 0000000..190e01a
--- /dev/null
+++ b/arch/arm64/boot/dts/thunder.dts
@@ -0,0 +1,160 @@
+/*
+ * Cavium Thunder DTS file
+ *
+ * Copyright (C) 2013, Cavium Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+	model = "Cavium Thunder";
+	compatible = "cavium,thunder";
+	interrupt-parent = <&gic0>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uaa0;
+		serial1 = &uaa1;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+		cpu@4 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x4>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+		cpu@5 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x5>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+		cpu@6 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x6>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+		cpu@7 {
+			device_type = "cpu";
+			compatible = "cavium,thunder", "arm,armv8";
+			reg = <0x0 0x7>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xfff8>;
+		};
+
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	gic0: interrupt-controller@801000000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x8010 0x0 0x0 0x10000>,         /* GICD */
+		      <0x8010 0x80000000 0x0 0x100000>; /* GICR */
+		interrupts = <1 9 0xf04>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 13 0xff01>,
+		             <1 14 0xff01>,
+		             <1 11 0xff01>,
+		             <1 10 0xff01>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clocks {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			refclk50mhz: refclk50mhz {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <50000000>;
+				clock-output-names = "refclk50mhz";
+			};
+		};
+
+		ahci0: host-bus-adapter@810000000000 {
+			compatible = "snps,spear-ahci";
+			reg = <0x8100 0x0 0x0 0x1100>;
+			interrupts = <1 32 4>;
+		};
+
+		nic0: ethernet@843000000000 {
+			compatible = "smsc,lan9115";
+			reg-io-width = <4>;
+			reg = <0x8430 0x0 0x0 0x1000>;
+			interrupts = <1 31 4>;
+		};
+
+		uaa0: uart@87e024000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x87e0 0x24000000 0x0 0x1000>;
+			interrupts = <1 21 4>;
+			clocks = <&refclk50mhz>;
+			clock-names = "apb_pclk";
+		};
+
+		uaa1: uart@87e025000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x87e0 0x25000000 0x0 0x1000>;
+			interrupts = <1 22 4>;
+			clocks = <&refclk50mhz>;
+			clock-names = "apb_pclk";
+		};
+	};
+};
-- 
1.7.1

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Re: [PATCH v2 2/3] arm64: dts: Add initial dts for Cavium Thunder SoC

[Arnd Bergmann]

On Monday 24 March 2014 14:39:38 mohun106-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
> +       soc {
> +               compatible = "simple-bus";
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               clocks {
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +
> +                       refclk50mhz: refclk50mhz {
> +                               compatible = "fixed-clock";
> +                               #clock-cells = <0>;
> +                               clock-frequency = <50000000>;
> +                               clock-output-names = "refclk50mhz";
> +                       };
> +               };
> +
> +               ahci0: host-bus-adapter@810000000000 {
> +                       compatible = "snps,spear-ahci";
> +                       reg = <0x8100 0x0 0x0 0x1100>;
> +                       interrupts = <1 32 4>;
> +               };


The use of "snps,spear-ahci" by itself seems wrong here: that is
the specific implementation used in the ST "spear" SoC. I don't know
why we don't already have a "generic-ahci" binding, but please add
one so you can match against that.

I would also recommend adding a more specific string for your soc.
If you want to keep compatibility with older kernels, you can keep
the spear string as well, but it would be nicer to drop that.
If you can find out what version the synopsys macro has, that would
be ideal.

You could end up for instance with

	compatible = "cavium,thunder-123456-ahci", "snps,ahci-1.23.45",
			"snps,spear-ahci", "generic-ahci";

The driver only needs to match the last one of these, but if we
find that we have to work around some bug, it's good to have the
option of determining the exact version.

> +               nic0: ethernet@843000000000 {
> +                       compatible = "smsc,lan9115";
> +                       reg-io-width = <4>;
> +                       reg = <0x8430 0x0 0x0 0x1000>;
> +                       interrupts = <1 31 4>;
> +               };
> +
> +               uaa0: uart@87e024000000 {
> +                       compatible = "arm,pl011", "arm,primecell";
> +                       reg = <0x87e0 0x24000000 0x0 0x1000>;
> +                       interrupts = <1 21 4>;
> +                       clocks = <&refclk50mhz>;
> +                       clock-names = "apb_pclk";
> +               };
> +
> +               uaa1: uart@87e025000000 {
> +                       compatible = "arm,pl011", "arm,primecell";
> +                       reg = <0x87e0 0x25000000 0x0 0x1000>;
> +                       interrupts = <1 22 4>;
> +                       clocks = <&refclk50mhz>;
> +                       clock-names = "apb_pclk";

The generic name for uarts in DT is "serial", not "uart" (yes, a
lot of others get this wrong, too).

	Arnd
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Re: [PATCH v2 2/3] arm64: dts: Add initial dts for Cavium Thunder SoC

[Radha Mohan]

Hi Arnd

On Mon, Mar 24, 2014 at 3:25 PM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Monday 24 March 2014 14:39:38 mohun106-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
>> +       soc {
>> +               compatible = "simple-bus";
>> +               #address-cells = <2>;
>> +               #size-cells = <2>;
>> +               ranges;
>> +
>> +               clocks {
>> +                       #address-cells = <2>;
>> +                       #size-cells = <2>;
>> +                       ranges;
>> +
>> +                       refclk50mhz: refclk50mhz {
>> +                               compatible = "fixed-clock";
>> +                               #clock-cells = <0>;
>> +                               clock-frequency = <50000000>;
>> +                               clock-output-names = "refclk50mhz";
>> +                       };
>> +               };
>> +
>> +               ahci0: host-bus-adapter@810000000000 {
>> +                       compatible = "snps,spear-ahci";
>> +                       reg = <0x8100 0x0 0x0 0x1100>;
>> +                       interrupts = <1 32 4>;
>> +               };
>
>
> The use of "snps,spear-ahci" by itself seems wrong here: that is
> the specific implementation used in the ST "spear" SoC. I don't know
> why we don't already have a "generic-ahci" binding, but please add
> one so you can match against that.
>
> I would also recommend adding a more specific string for your soc.
> If you want to keep compatibility with older kernels, you can keep
> the spear string as well, but it would be nicer to drop that.
> If you can find out what version the synopsys macro has, that would
> be ideal.
>
> You could end up for instance with
>
>         compatible = "cavium,thunder-123456-ahci", "snps,ahci-1.23.45",
>                         "snps,spear-ahci", "generic-ahci";
>
> The driver only needs to match the last one of these, but if we
> find that we have to work around some bug, it's good to have the
> option of determining the exact version.

OK.

>
>> +               nic0: ethernet@843000000000 {
>> +                       compatible = "smsc,lan9115";
>> +                       reg-io-width = <4>;
>> +                       reg = <0x8430 0x0 0x0 0x1000>;
>> +                       interrupts = <1 31 4>;
>> +               };
>> +
>> +               uaa0: uart@87e024000000 {
>> +                       compatible = "arm,pl011", "arm,primecell";
>> +                       reg = <0x87e0 0x24000000 0x0 0x1000>;
>> +                       interrupts = <1 21 4>;
>> +                       clocks = <&refclk50mhz>;
>> +                       clock-names = "apb_pclk";
>> +               };
>> +
>> +               uaa1: uart@87e025000000 {
>> +                       compatible = "arm,pl011", "arm,primecell";
>> +                       reg = <0x87e0 0x25000000 0x0 0x1000>;
>> +                       interrupts = <1 22 4>;
>> +                       clocks = <&refclk50mhz>;
>> +                       clock-names = "apb_pclk";
>
> The generic name for uarts in DT is "serial", not "uart" (yes, a
> lot of others get this wrong, too).

OK :)
But I think lack of consistency in DT among various ARM platforms is
source of this confusion.

>
>         Arnd
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Re: [PATCH v2 2/3] arm64: dts: Add initial dts for Cavium Thunder SoC

[Mark Rutland]

Hi,

On Mon, Mar 24, 2014 at 09:09:38AM +0000, mohun106-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
> From: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> 
> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm64/boot/dts/Makefile    |    1 +
>  arch/arm64/boot/dts/thunder.dts |  160 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 161 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index c52bdb0..9cc8740 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_THUNDER) += thunder.dtb
>  dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
>  dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
>  
> diff --git a/arch/arm64/boot/dts/thunder.dts b/arch/arm64/boot/dts/thunder.dts
> new file mode 100644
> index 0000000..190e01a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/thunder.dts
> @@ -0,0 +1,160 @@
> +/*
> + * Cavium Thunder DTS file
> + *
> + * Copyright (C) 2013, Cavium Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +/dts-v1/;
> +
> +/memreserve/ 0x80000000 0x00010000;

Please add a comment as to what this is protecting (from the looks of
it, the spinning CPUs and the cpu release address). We are admittedly
lacking these on existing DTs (and I'll fix that up), but it would be
good to get into the habit now given it has been a source of confusion
for some.

> +
> +/ {
> +	model = "Cavium Thunder";
> +	compatible = "cavium,thunder";
> +	interrupt-parent = <&gic0>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uaa0;
> +		serial1 = &uaa1;
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "cavium,thunder", "arm,armv8";

This is the same as the compatible string for the SoC, which isn't a
good idea. Compatible strings should be globally unique.

As far as I am aware, "Thunder" is the name of the SoC, not the CPU in
the SoC. Is there a name for the CPU in the Thunder SoC?

Whatever name you have should be documented.

[...]

> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>;
> +	};
> +
> +	gic0: interrupt-controller@801000000000 {

Please break the 32-bit halves of the unit-address with a comma (e.g.
8010,00000000); it makes it easier to read the address. If you could
also do this on other unit-addresses it would be helpful.

> +		compatible = "arm,gic-v3";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0x8010 0x0 0x0 0x10000>,         /* GICD */
> +		      <0x8010 0x80000000 0x0 0x100000>; /* GICR */

For legibility it would be nice for list entries to be consistently
padded to the same length.

> +		interrupts = <1 9 0xf04>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <1 13 0xff01>,
> +		             <1 14 0xff01>,
> +		             <1 11 0xff01>,
> +		             <1 10 0xff01>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		clocks {
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			refclk50mhz: refclk50mhz {
> +				compatible = "fixed-clock";
> +				#clock-cells = <0>;
> +				clock-frequency = <50000000>;
> +				clock-output-names = "refclk50mhz";
> +			};
> +		};

I don't think the clocks node adds anything here. It's missing a
compatible string list, and as clocks isn't a special reserved node
name, it and its children aren't supposed to be probed.

Why not just put the refclk50mhz directly under the parent node (the soc
simple-bus)?

[...]

> +		uaa0: uart@87e024000000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x87e0 0x24000000 0x0 0x1000>;
> +			interrupts = <1 21 4>;
> +			clocks = <&refclk50mhz>;
> +			clock-names = "apb_pclk";

Is this also feeding the UARTCLK?

> +		};
> +
> +		uaa1: uart@87e025000000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x87e0 0x25000000 0x0 0x1000>;
> +			interrupts = <1 22 4>;
> +			clocks = <&refclk50mhz>;
> +			clock-names = "apb_pclk";

Likewise?

Cheers,
Mark.
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Re: [PATCH v2 2/3] arm64: dts: Add initial dts for Cavium Thunder SoC

[Radha Mohan]

Hi Mark,

On Mon, Mar 24, 2014 at 3:55 PM, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:
> Hi,
>
> On Mon, Mar 24, 2014 at 09:09:38AM +0000, mohun106-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
>> From: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
>>
>> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
>> ---
>>  arch/arm64/boot/dts/Makefile    |    1 +
>>  arch/arm64/boot/dts/thunder.dts |  160 +++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 161 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index c52bdb0..9cc8740 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -1,3 +1,4 @@
>> +dtb-$(CONFIG_ARCH_THUNDER) += thunder.dtb
>>  dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
>>  dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
>>
>> diff --git a/arch/arm64/boot/dts/thunder.dts b/arch/arm64/boot/dts/thunder.dts
>> new file mode 100644
>> index 0000000..190e01a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/thunder.dts
>> @@ -0,0 +1,160 @@
>> +/*
>> + * Cavium Thunder DTS file
>> + *
>> + * Copyright (C) 2013, Cavium Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + */
>> +/dts-v1/;
>> +
>> +/memreserve/ 0x80000000 0x00010000;
>
> Please add a comment as to what this is protecting (from the looks of
> it, the spinning CPUs and the cpu release address). We are admittedly
> lacking these on existing DTs (and I'll fix that up), but it would be
> good to get into the habit now given it has been a source of confusion
> for some.

OK.

>
>> +
>> +/ {
>> +     model = "Cavium Thunder";
>> +     compatible = "cavium,thunder";
>> +     interrupt-parent = <&gic0>;
>> +     #address-cells = <2>;
>> +     #size-cells = <2>;
>> +
>> +     aliases {
>> +             serial0 = &uaa0;
>> +             serial1 = &uaa1;
>> +     };
>> +
>> +     cpus {
>> +             #address-cells = <2>;
>> +             #size-cells = <0>;
>> +             cpu@0 {
>> +                     device_type = "cpu";
>> +                     compatible = "cavium,thunder", "arm,armv8";
>
> This is the same as the compatible string for the SoC, which isn't a
> good idea. Compatible strings should be globally unique.
>
> As far as I am aware, "Thunder" is the name of the SoC, not the CPU in
> the SoC. Is there a name for the CPU in the Thunder SoC?
>
> Whatever name you have should be documented.

OK. I will change it to a specific name.

>
> [...]
>
>> +     memory@0 {
>> +             device_type = "memory";
>> +             reg = <0x0 0x0 0x0 0x80000000>;
>> +     };
>> +
>> +     gic0: interrupt-controller@801000000000 {
>
> Please break the 32-bit halves of the unit-address with a comma (e.g.
> 8010,00000000); it makes it easier to read the address. If you could
> also do this on other unit-addresses it would be helpful.

OK.

>
>> +             compatible = "arm,gic-v3";
>> +             #interrupt-cells = <3>;
>> +             #address-cells = <0>;
>> +             interrupt-controller;
>> +             reg = <0x8010 0x0 0x0 0x10000>,         /* GICD */
>> +                   <0x8010 0x80000000 0x0 0x100000>; /* GICR */
>
> For legibility it would be nice for list entries to be consistently
> padded to the same length.

OK.

>
>> +             interrupts = <1 9 0xf04>;
>> +     };
>> +
>> +     timer {
>> +             compatible = "arm,armv8-timer";
>> +             interrupts = <1 13 0xff01>,
>> +                          <1 14 0xff01>,
>> +                          <1 11 0xff01>,
>> +                          <1 10 0xff01>;
>> +     };
>> +
>> +     soc {
>> +             compatible = "simple-bus";
>> +             #address-cells = <2>;
>> +             #size-cells = <2>;
>> +             ranges;
>> +
>> +             clocks {
>> +                     #address-cells = <2>;
>> +                     #size-cells = <2>;
>> +                     ranges;
>> +
>> +                     refclk50mhz: refclk50mhz {
>> +                             compatible = "fixed-clock";
>> +                             #clock-cells = <0>;
>> +                             clock-frequency = <50000000>;
>> +                             clock-output-names = "refclk50mhz";
>> +                     };
>> +             };
>
> I don't think the clocks node adds anything here. It's missing a
> compatible string list, and as clocks isn't a special reserved node
> name, it and its children aren't supposed to be probed.
>
> Why not just put the refclk50mhz directly under the parent node (the soc
> simple-bus)?

OK.

>
> [...]
>
>> +             uaa0: uart@87e024000000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x87e0 0x24000000 0x0 0x1000>;
>> +                     interrupts = <1 21 4>;
>> +                     clocks = <&refclk50mhz>;
>> +                     clock-names = "apb_pclk";
>
> Is this also feeding the UARTCLK?

Right now, this is for an internal emulation platform for our chip. So
all these clock definitions are not applicable.
In real chip, there will be other clock definitions coming.

>
>> +             };
>> +
>> +             uaa1: uart@87e025000000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x87e0 0x25000000 0x0 0x1000>;
>> +                     interrupts = <1 22 4>;
>> +                     clocks = <&refclk50mhz>;
>> +                     clock-names = "apb_pclk";
>
> Likewise?
>
> Cheers,
> Mark.
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[PATCH v2 3/3] Documentation: add devicetree bindings for Cavium Thunder SoC

[mohun106-Re5JQEeQqe8AvxtiuMwx3w]

From: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>

This patch adds documentation for the devicetree bindings used by the
DT files of Cavium Thunder SoC platforms.

Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/arm/cavium-thunder.txt     |    9 +++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |    1 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
new file mode 100644
index 0000000..6ea0a34
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
@@ -0,0 +1,9 @@
+Cavium Thunder platform device tree bindings
+---------------------------------------------
+
+Boards with Cavium's Thunder SoC shall have following properties.
+
+Root Node
+---------
+Required root node properties:
+    - compatible = "cavium,thunder";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 333f4ae..f6cadf1 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
 			    "arm,cortex-r4"
 			    "arm,cortex-r5"
 			    "arm,cortex-r7"
+			    "cavium,thunder"
 			    "faraday,fa526"
 			    "intel,sa110"
 			    "intel,sa1100"
-- 
1.7.1

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Re: [PATCH v2 3/3] Documentation: add devicetree bindings for Cavium Thunder SoC

[Arnd Bergmann]

On Monday 24 March 2014 14:39:39 mohun106-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
> diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
> new file mode 100644
> index 0000000..6ea0a34
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
> @@ -0,0 +1,9 @@
> +Cavium Thunder platform device tree bindings
> +---------------------------------------------
> +
> +Boards with Cavium's Thunder SoC shall have following properties.
> +
> +Root Node
> +---------
> +Required root node properties:
> +    - compatible = "cavium,thunder";
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 333f4ae..f6cadf1 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
>                             "arm,cortex-r4"
>                             "arm,cortex-r5"
>                             "arm,cortex-r7"
> +                           "cavium,thunder"
>                             "faraday,fa526"
>                             "intel,sa110"
>                             "intel,sa1100"


It seems very confusing to use the same name for both the SoC and the
CPU core. Can you guarantee that there will never be another SoC with
the same core, or a different CPU core in a SoC with the same name?

If not, please be more specific here and use the exact model names
rather than the product names.

	Arnd
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Re: [PATCH v2 3/3] Documentation: add devicetree bindings for Cavium Thunder SoC

[Radha Mohan]

On Mon, Mar 24, 2014 at 4:30 PM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Monday 24 March 2014 14:39:39 mohun106-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
>> diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
>> new file mode 100644
>> index 0000000..6ea0a34
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
>> @@ -0,0 +1,9 @@
>> +Cavium Thunder platform device tree bindings
>> +---------------------------------------------
>> +
>> +Boards with Cavium's Thunder SoC shall have following properties.
>> +
>> +Root Node
>> +---------
>> +Required root node properties:
>> +    - compatible = "cavium,thunder";
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 333f4ae..f6cadf1 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
>>                             "arm,cortex-r4"
>>                             "arm,cortex-r5"
>>                             "arm,cortex-r7"
>> +                           "cavium,thunder"
>>                             "faraday,fa526"
>>                             "intel,sa110"
>>                             "intel,sa1100"
>
>
> It seems very confusing to use the same name for both the SoC and the
> CPU core. Can you guarantee that there will never be another SoC with
> the same core, or a different CPU core in a SoC with the same name?
>
> If not, please be more specific here and use the exact model names
> rather than the product names.

OK, will fix this once I discuss this internally.

>
>         Arnd
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