From mboxrd@z Thu Jan 1 00:00:00 1970 From: Carlo Caione Subject: Re: [PATCH v7 0/3] ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller Date: Tue, 25 Mar 2014 22:27:35 +0100 Message-ID: <20140325212735.GA4853@localhost.fastwebnet.it> References: <1395256879-8475-1-git-send-email-carlo@caione.org> Reply-To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1395256879-8475-1-git-send-email-carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org> List-Post: , List-Help: , List-Archive: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Subscribe: , List-Unsubscribe: , Content-Disposition: inline To: tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On Wed, Mar 19, 2014 at 08:21:16PM +0100, Carlo Caione wrote: > Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. > Three register are present to (un)mask, control and acknowledge NMI. > These two patches add a new irqchip driver in cascade with GIC. Hi Thomas, Is this ok with the Maxime ACKs? -- Carlo Caione