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From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cc: "Randy Dunlap" <rdunlap@infradead.org>,
	"Emilio López" <emilio@elopez.com.ar>,
	"Mike Turquette" <mturquette@linaro.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 07/15] ARM: sunxi: dt: define A31's APB0 clk gates node
Date: Wed, 9 Apr 2014 17:08:46 +0200	[thread overview]
Message-ID: <20140409150846.GG28585@lukather> (raw)
In-Reply-To: <1397051478-4113-8-git-send-email-boris.brezillon@free-electrons.com>

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On Wed, Apr 09, 2014 at 03:51:10PM +0200, Boris BREZILLON wrote:
> Define the APB0 clk gates controlled by the PRCM (Power/Reset/Clock
> Management) block.
> 
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> ---
>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index 3858424..61e8b34 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -141,6 +141,16 @@
>  					"ahb1_drc0", "ahb1_drc1";
>  		};
>  
> +		apb0_gates: apb0_gates@01f01428 {

The node name should reflect the class of the device, so it should be
clk@<address>.

> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-apb0-gates-clk";
> +			reg = <0x01f01428 0x4>;
> +			clock-output-names = "apb0_pio", "apb0_ir",
> +					"apb0_timer01", "apb0_p2wi",
> +					"apb0_uart", "apb0_1wire",
> +					"apb0_i2c";
> +		};
> +

Hmmm, I'm not really fond of this.

There's already a PRCM node in the DT, which is used for the SMP
bringup.

I really don't want any duplicate memory regions in the DT, so you'll
have to fix the SMP code.

That being said, I can understand that you did this to be consistent
with the scheme we have for the clock controller where we chose to
make every clock a single driver.

That worked well for the CCU precisely because we only had clocks. It
doesn't for the PRCM because it's not been very well documented, and
it does clocks, resets, that fits pretty well in the existing
frameworks we have, but the SMP related functions are actually not
fitting that well.

It's mostly a power clamp and a power gating bits, that could maybe
fit in the regulator framework.

I don't really have a solution for this. Maybe someone else will.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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  parent reply	other threads:[~2014-04-09 15:08 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-09 13:51 [PATCH 00/15] ARM: sunxi: add A31 PL pins support Boris BREZILLON
2014-04-09 13:51 ` [PATCH 01/15] ARM: sunxi: dt: list all pinctrl compatible strings Boris BREZILLON
     [not found]   ` <1397051478-4113-2-git-send-email-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-04-09 14:43     ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 02/15] ARM: sunxi: dt: document pinctrl clock related properties Boris BREZILLON
2014-04-09 14:45   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 03/15] ARM: sunxi: dt: add pinctrl clock-names properties Boris BREZILLON
2014-04-09 13:51 ` [PATCH 04/15] pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk Boris BREZILLON
     [not found]   ` <1397051478-4113-5-git-send-email-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-04-10 18:14     ` Linus Walleij
2014-04-10 18:16       ` Linus Walleij
2014-04-10 21:17         ` Boris BREZILLON
2014-04-09 13:51 ` [PATCH 05/15] clk: sunxi: add A31 APB0 clk gate defintions Boris BREZILLON
2014-04-09 14:49   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation Boris BREZILLON
2014-04-09 13:59   ` Chen-Yu Tsai
2014-04-09 14:45     ` Boris BREZILLON
2014-04-09 14:51   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 07/15] ARM: sunxi: dt: define A31's APB0 clk gates node Boris BREZILLON
2014-04-09 14:06   ` Emilio López
2014-04-09 14:43     ` Boris BREZILLON
2014-04-09 15:08   ` Maxime Ripard [this message]
2014-04-09 13:51 ` [PATCH 08/15] reset: sunxi: document sunxi's reset controllers bindings Boris BREZILLON
2014-04-09 13:51 ` [PATCH 09/15] clk: sunxi: add A31 APB0 reset line defintions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 10/15] pinctrl: sunxi: add PL pin definitions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 11/15] pinctrl: sunxi: add support for A31 PL pins Boris BREZILLON
2014-04-09 13:51 ` [PATCH 12/15] pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC Boris BREZILLON
2014-04-09 15:33   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 13/15] pinctrl: sunxi: retrieve and enable PL reset line " Boris BREZILLON
2014-04-09 15:34   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 14/15] pinctrl: sunxi: define A31 PL0/PL1 pins Boris BREZILLON
2014-04-09 15:38   ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 15/15] ARM: sunxi: dt: add support for A31's PL pins Boris BREZILLON
2014-04-09 14:53 ` [PATCH 00/15] ARM: sunxi: add A31 PL pins support Chen-Yu Tsai
2014-04-09 15:17   ` Maxime Ripard
2014-04-09 15:45     ` Maxime Ripard
2014-04-09 16:27     ` Chen-Yu Tsai
2014-04-10  8:10       ` Maxime Ripard
2014-04-10  9:56         ` Chen-Yu Tsai
2014-04-09 16:14   ` Boris BREZILLON
2014-04-09 17:14     ` Chen-Yu Tsai
2014-04-09 18:04       ` Boris BREZILLON
2014-04-10  8:16       ` Maxime Ripard

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