From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: "Boris BREZILLON" <boris.brezillon@free-electrons.com>,
"Randy Dunlap" <rdunlap@infradead.org>,
"Emilio López" <emilio@elopez.com.ar>,
"Mike Turquette" <mturquette@linaro.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
devicetree <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH 00/15] ARM: sunxi: add A31 PL pins support
Date: Wed, 9 Apr 2014 17:17:47 +0200 [thread overview]
Message-ID: <20140409151747.GH28585@lukather> (raw)
In-Reply-To: <CAGb2v66XCN2ar1wj+a1+ZwdcdJ3gzJ+nDiO9bu52OwK+mBB_Hg@mail.gmail.com>
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On Wed, Apr 09, 2014 at 10:53:13PM +0800, Chen-Yu Tsai wrote:
> Hi Boris,
>
> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
> <boris.brezillon@free-electrons.com> wrote:
> > Hello,
> >
> > This series rework the sunxi pinctrl driver to support the PLx pins
> > available on the A31 SoC.
>
> Thanks for working on this. I mentioned to Maxime on IRC yesterday that
> we have complete pinctrl drivers for both A31 and A23, based on our current
> pinctrl-sunxi driver, in the A23 SDK. These have the complete pin mapping.
>
> > It also add missing A31 reset controller DT bindings documentation.
> >
> > I need those PL pins (actually I only need PL0 and PL1) to support
> > the P2WI bus, which in turn is used to communicate with the AXP221
> > PMIC.
>
> If you could, please add all the PL and PM pins.
> As I said, you can find complete definitions in the A23 SDK.
We have no idea what these PM pins are for the A31. And this code only
is of interest for the A31 for the moment. Let's not take into account
the A23 for now as far as the pin definitions are concerned.
> > Let me know if these changes are too intrusive.
>
> I wonder if we should do a separate driver for the new PIO controller.
> Clearly it's a separate IP block, with it's own clock and reset controls.
It's been merged together in the A23, hence why we did it like that.
> Allwinner sources list this block as "R_PIO". I suggest using this name.
> Clearly "pioL" does not cover all the functionality.
I'd agree with that.
> I have started to document the PRCM block: http://linux-sunxi.org/PRCM
It's quite different on the A31 and on the A23 actually :(
You don't have any of the audio thing for example, but you have the
CPUs power clamp controls, that have been moved to the
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2014-04-09 15:17 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-09 13:51 [PATCH 00/15] ARM: sunxi: add A31 PL pins support Boris BREZILLON
2014-04-09 13:51 ` [PATCH 01/15] ARM: sunxi: dt: list all pinctrl compatible strings Boris BREZILLON
[not found] ` <1397051478-4113-2-git-send-email-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-04-09 14:43 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 02/15] ARM: sunxi: dt: document pinctrl clock related properties Boris BREZILLON
2014-04-09 14:45 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 03/15] ARM: sunxi: dt: add pinctrl clock-names properties Boris BREZILLON
2014-04-09 13:51 ` [PATCH 04/15] pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk Boris BREZILLON
[not found] ` <1397051478-4113-5-git-send-email-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-04-10 18:14 ` Linus Walleij
2014-04-10 18:16 ` Linus Walleij
2014-04-10 21:17 ` Boris BREZILLON
2014-04-09 13:51 ` [PATCH 05/15] clk: sunxi: add A31 APB0 clk gate defintions Boris BREZILLON
2014-04-09 14:49 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation Boris BREZILLON
2014-04-09 13:59 ` Chen-Yu Tsai
2014-04-09 14:45 ` Boris BREZILLON
2014-04-09 14:51 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 07/15] ARM: sunxi: dt: define A31's APB0 clk gates node Boris BREZILLON
2014-04-09 14:06 ` Emilio López
2014-04-09 14:43 ` Boris BREZILLON
2014-04-09 15:08 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 08/15] reset: sunxi: document sunxi's reset controllers bindings Boris BREZILLON
2014-04-09 13:51 ` [PATCH 09/15] clk: sunxi: add A31 APB0 reset line defintions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 10/15] pinctrl: sunxi: add PL pin definitions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 11/15] pinctrl: sunxi: add support for A31 PL pins Boris BREZILLON
2014-04-09 13:51 ` [PATCH 12/15] pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC Boris BREZILLON
2014-04-09 15:33 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 13/15] pinctrl: sunxi: retrieve and enable PL reset line " Boris BREZILLON
2014-04-09 15:34 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 14/15] pinctrl: sunxi: define A31 PL0/PL1 pins Boris BREZILLON
2014-04-09 15:38 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 15/15] ARM: sunxi: dt: add support for A31's PL pins Boris BREZILLON
2014-04-09 14:53 ` [PATCH 00/15] ARM: sunxi: add A31 PL pins support Chen-Yu Tsai
2014-04-09 15:17 ` Maxime Ripard [this message]
2014-04-09 15:45 ` Maxime Ripard
2014-04-09 16:27 ` Chen-Yu Tsai
2014-04-10 8:10 ` Maxime Ripard
2014-04-10 9:56 ` Chen-Yu Tsai
2014-04-09 16:14 ` Boris BREZILLON
2014-04-09 17:14 ` Chen-Yu Tsai
2014-04-09 18:04 ` Boris BREZILLON
2014-04-10 8:16 ` Maxime Ripard
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